acp.c (1004f34d4f4a59aa5508c3b96069759efa738544) acp.c (490be7ba2a018093fbfa6c2dd80d7d0c190c4c98)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// This file is provided under a dual BSD/GPLv2 license. When using or
4// redistributing this file, you may do so under either license.
5//
6// Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
7//
8// Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>

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59
60 return data;
61}
62
63static void init_dma_descriptor(struct acp_dev_data *adata)
64{
65 struct snd_sof_dev *sdev = adata->dev;
66 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// This file is provided under a dual BSD/GPLv2 license. When using or
4// redistributing this file, you may do so under either license.
5//
6// Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
7//
8// Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>

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59
60 return data;
61}
62
63static void init_dma_descriptor(struct acp_dev_data *adata)
64{
65 struct snd_sof_dev *sdev = adata->dev;
66 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
67 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;
67 unsigned int addr;
68 unsigned int addr;
69 unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr;
68
69 addr = desc->sram_pte_offset + sdev->debug_box.offset +
70 offsetof(struct scratch_reg_conf, dma_desc);
71
70
71 addr = desc->sram_pte_offset + sdev->debug_box.offset +
72 offsetof(struct scratch_reg_conf, dma_desc);
73
72 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr);
73 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT);
74 switch (acp_data->pci_rev) {
75 case ACP70_PCI_ID:
76 acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR;
77 acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR;
78 break;
79 default:
80 acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR;
81 acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR;
82 }
83 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr);
84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT);
74}
75
76static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx,
77 struct dma_descriptor *dscr_info)
78{
79 struct snd_sof_dev *sdev = adata->dev;
80 unsigned int offset;
81

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87 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr);
88 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all);
89}
90
91static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
92 unsigned int idx, unsigned int dscr_count)
93{
94 struct snd_sof_dev *sdev = adata->dev;
85}
86
87static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx,
88 struct dma_descriptor *dscr_info)
89{
90 struct snd_sof_dev *sdev = adata->dev;
91 unsigned int offset;
92

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98 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr);
99 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all);
100}
101
102static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
103 unsigned int idx, unsigned int dscr_count)
104{
105 struct snd_sof_dev *sdev = adata->dev;
106 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;
95 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
96 unsigned int val, status;
107 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
108 unsigned int val, status;
109 unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0;
110 unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0;
97 int ret;
98
111 int ret;
112
99 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32),
113 switch (acp_data->pci_rev) {
114 case ACP70_PCI_ID:
115 acp_dma_cntl_0 = ACP70_DMA_CNTL_0;
116 acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS;
117 acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0;
118 acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0;
119 acp_dma_prio_0 = ACP70_DMA_PRIO_0;
120 acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0;
121 break;
122 default:
123 acp_dma_cntl_0 = ACP_DMA_CNTL_0;
124 acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS;
125 acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0;
126 acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0;
127 acp_dma_prio_0 = ACP_DMA_PRIO_0;
128 acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0;
129 }
130
131 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32),
100 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN);
101
132 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN);
133
102 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val,
134 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val,
103 val & (1 << ch), ACP_REG_POLL_INTERVAL,
104 ACP_REG_POLL_TIMEOUT_US);
105 if (ret < 0) {
106 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat);
135 val & (1 << ch), ACP_REG_POLL_INTERVAL,
136 ACP_REG_POLL_TIMEOUT_US);
137 if (ret < 0) {
138 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat);
107 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));
139 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 +
140 ch * sizeof(u32));
108
109 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
110 return ret;
111 }
112
141
142 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
143 return ret;
144 }
145
113 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0);
114 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count);
115 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx);
116 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0);
117 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);
146 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0);
147 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count);
148 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx);
149 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0);
150 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);
118
119 return ret;
120}
121
122static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch,
123 unsigned int dscr_count, struct dma_descriptor *dscr_info)
124{
125 struct snd_sof_dev *sdev = adata->dev;

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448 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK;
449 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK;
450 break;
451 case ACP_RMB_PCI_ID:
452 case ACP63_PCI_ID:
453 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK;
454 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK;
455 break;
151
152 return ret;
153}
154
155static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch,
156 unsigned int dscr_count, struct dma_descriptor *dscr_info)
157{
158 struct snd_sof_dev *sdev = adata->dev;

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481 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK;
482 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK;
483 break;
484 case ACP_RMB_PCI_ID:
485 case ACP63_PCI_ID:
486 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK;
487 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK;
488 break;
489 case ACP70_PCI_ID:
490 acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK;
491 acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK;
492 break;
456 default:
457 return -EINVAL;
458 }
459
460 if (val & acp_pgfsm_status_mask)
461 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,
462 acp_pgfsm_cntl_mask);
463

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556 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN);
557 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN);
558 acp_data->sdw_en_stat = sdw0_en || sdw1_en;
559 return acp_data->sdw_en_stat;
560}
561
562int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
563{
493 default:
494 return -EINVAL;
495 }
496
497 if (val & acp_pgfsm_status_mask)
498 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,
499 acp_pgfsm_cntl_mask);
500

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593 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN);
594 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN);
595 acp_data->sdw_en_stat = sdw0_en || sdw1_en;
596 return acp_data->sdw_en_stat;
597}
598
599int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
600{
601 struct acp_dev_data *acp_data;
564 int ret;
602 int ret;
603 bool enable = false;
565
604
605 acp_data = sdev->pdata->hw_pdata;
566 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and
567 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will
568 * be reset to default values which will break the ClockStop Mode functionality.
569 * Add a condition check to apply DSP reset when SoundWire ClockStop mode
570 * is selected. For the rest of the scenarios, apply acp reset sequence.
571 */
572 if (check_acp_sdw_enable_status(sdev))
573 return acp_dsp_reset(sdev);
574
575 ret = acp_reset(sdev);
576 if (ret) {
577 dev_err(sdev->dev, "ACP Reset failed\n");
578 return ret;
579 }
606 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and
607 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will
608 * be reset to default values which will break the ClockStop Mode functionality.
609 * Add a condition check to apply DSP reset when SoundWire ClockStop mode
610 * is selected. For the rest of the scenarios, apply acp reset sequence.
611 */
612 if (check_acp_sdw_enable_status(sdev))
613 return acp_dsp_reset(sdev);
614
615 ret = acp_reset(sdev);
616 if (ret) {
617 dev_err(sdev->dev, "ACP Reset failed\n");
618 return ret;
619 }
620 if (acp_data->pci_rev == ACP70_PCI_ID)
621 enable = true;
622 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable);
580
623
581 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00);
582
583 return 0;
584}
585EXPORT_SYMBOL_NS(amd_sof_acp_suspend, SND_SOC_SOF_AMD_COMMON);
586
587int amd_sof_acp_resume(struct snd_sof_dev *sdev)
588{
589 int ret;
590 struct acp_dev_data *acp_data;

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625}
626EXPORT_SYMBOL_NS(amd_sof_acp_suspend, SND_SOC_SOF_AMD_COMMON);
627
628int amd_sof_acp_resume(struct snd_sof_dev *sdev)
629{
630 int ret;
631 struct acp_dev_data *acp_data;

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