mt2701-reg.h (f26e8817b235d8764363bffcc9cbfc61867371f2) mt2701-reg.h (600b2fd4f0f7ae5ebcb604c39c9a97e573f9d23e)
1/*
2 * mt2701-reg.h -- Mediatek 2701 audio driver reg definition
3 *
4 * Copyright (c) 2016 MediaTek Inc.
5 * Author: Garlic Tseng <garlic.tseng@mediatek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 and
9 * only version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _MT2701_REG_H_
18#define _MT2701_REG_H_
19
1/*
2 * mt2701-reg.h -- Mediatek 2701 audio driver reg definition
3 *
4 * Copyright (c) 2016 MediaTek Inc.
5 * Author: Garlic Tseng <garlic.tseng@mediatek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 and
9 * only version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _MT2701_REG_H_
18#define _MT2701_REG_H_
19
20#include <linux/delay.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/pm_runtime.h>
25#include <sound/soc.h>
26#include "mt2701-afe-common.h"
27
28/*****************************************************************************
29 * R E G I S T E R D E F I N I T I O N
30 *****************************************************************************/
31#define AUDIO_TOP_CON0 0x0000
32#define AUDIO_TOP_CON4 0x0010
33#define AUDIO_TOP_CON5 0x0014
34#define AFE_DAIBT_CON0 0x001c
35#define AFE_MRGIF_CON 0x003c
36#define ASMI_TIMING_CON1 0x0100
37#define ASMO_TIMING_CON1 0x0104
38#define PWR1_ASM_CON1 0x0108

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104#define AFE_UL4_END 0x1338
105#define AFE_UL4_CUR 0x133c
106#define AFE_UL5_BASE 0x1340
107#define AFE_UL5_END 0x1348
108#define AFE_UL5_CUR 0x134c
109#define AFE_DAI_BASE 0x1370
110#define AFE_DAI_CUR 0x137c
111
20#define AUDIO_TOP_CON0 0x0000
21#define AUDIO_TOP_CON4 0x0010
22#define AUDIO_TOP_CON5 0x0014
23#define AFE_DAIBT_CON0 0x001c
24#define AFE_MRGIF_CON 0x003c
25#define ASMI_TIMING_CON1 0x0100
26#define ASMO_TIMING_CON1 0x0104
27#define PWR1_ASM_CON1 0x0108

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93#define AFE_UL4_END 0x1338
94#define AFE_UL4_CUR 0x133c
95#define AFE_UL5_BASE 0x1340
96#define AFE_UL5_END 0x1348
97#define AFE_UL5_CUR 0x134c
98#define AFE_DAI_BASE 0x1370
99#define AFE_DAI_CUR 0x137c
100
112/* AUDIO_TOP_CON0 (0x0000) */
113#define AUDIO_TOP_CON0_A1SYS_A2SYS_ON (0x3 << 0)
114#define AUDIO_TOP_CON0_PDN_AFE (0x1 << 2)
115#define AUDIO_TOP_CON0_PDN_APLL_CK (0x1 << 23)
116
117/* AUDIO_TOP_CON4 (0x0010) */
118#define AUDIO_TOP_CON4_I2SO1_PWN (0x1 << 6)
119#define AUDIO_TOP_CON4_PDN_A1SYS (0x1 << 21)
120#define AUDIO_TOP_CON4_PDN_A2SYS (0x1 << 22)
121#define AUDIO_TOP_CON4_PDN_AFE_CONN (0x1 << 23)
122#define AUDIO_TOP_CON4_PDN_MRGIF (0x1 << 25)
123
124/* AFE_DAIBT_CON0 (0x001c) */
125#define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0)
126#define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1)
127#define AFE_DAIBT_CON0_BT_FUNC_RDY (0x1 << 3)
128#define AFE_DAIBT_CON0_BT_WIDE_MODE_EN (0x1 << 9)
129#define AFE_DAIBT_CON0_MRG_USE (0x1 << 12)
130
131/* PWR1_ASM_CON1 (0x0108) */
132#define PWR1_ASM_CON1_INIT_VAL (0x492)
133
134/* AFE_MRGIF_CON (0x003c) */
135#define AFE_MRGIF_CON_MRG_EN (0x1 << 0)
136#define AFE_MRGIF_CON_MRG_I2S_EN (0x1 << 16)
137#define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20)
138#define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20)
139
101/* AFE_DAIBT_CON0 (0x001c) */
102#define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0)
103#define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1)
104#define AFE_DAIBT_CON0_BT_FUNC_RDY (0x1 << 3)
105#define AFE_DAIBT_CON0_BT_WIDE_MODE_EN (0x1 << 9)
106#define AFE_DAIBT_CON0_MRG_USE (0x1 << 12)
107
108/* PWR1_ASM_CON1 (0x0108) */
109#define PWR1_ASM_CON1_INIT_VAL (0x492)
110
111/* AFE_MRGIF_CON (0x003c) */
112#define AFE_MRGIF_CON_MRG_EN (0x1 << 0)
113#define AFE_MRGIF_CON_MRG_I2S_EN (0x1 << 16)
114#define AFE_MRGIF_CON_I2S_MODE_MASK (0xf << 20)
115#define AFE_MRGIF_CON_I2S_MODE_32K (0x4 << 20)
116
140/* ASYS_I2SO1_CON (0x061c) */
141#define ASYS_I2SO1_CON_FS (0x1f << 8)
142#define ASYS_I2SO1_CON_FS_SET(x) ((x) << 8)
143#define ASYS_I2SO1_CON_MULTI_CH (0x1 << 16)
144#define ASYS_I2SO1_CON_SIDEGEN (0x1 << 30)
145#define ASYS_I2SO1_CON_I2S_EN (0x1 << 0)
146/* 0:EIAJ 1:I2S */
147#define ASYS_I2SO1_CON_I2S_MODE (0x1 << 3)
148#define ASYS_I2SO1_CON_WIDE_MODE (0x1 << 1)
149#define ASYS_I2SO1_CON_WIDE_MODE_SET(x) ((x) << 1)
117/* ASYS_TOP_CON (0x0600) */
118#define ASYS_TOP_CON_ASYS_TIMING_ON (0x3 << 0)
150
119
151/* PWR2_TOP_CON (0x0634) */
152#define PWR2_TOP_CON_INIT_VAL (0xffe1ffff)
153
154/* ASYS_IRQ_CLR (0x07c0) */
155#define ASYS_IRQ_CLR_ALL (0xffffffff)
156
157/* PWR2_ASM_CON1 (0x1070) */
158#define PWR2_ASM_CON1_INIT_VAL (0x492492)
159
160/* AFE_DAC_CON0 (0x1200) */
161#define AFE_DAC_CON0_AFE_ON (0x1 << 0)
162
163/* AFE_MEMIF_PBUF_SIZE (0x1238) */
164#define AFE_MEMIF_PBUF_SIZE_DLM_MASK (0x1 << 29)

--- 22 unchanged lines hidden --- 		120/* PWR2_ASM_CON1 (0x1070) */
121#define PWR2_ASM_CON1_INIT_VAL (0x492492)
122
123/* AFE_DAC_CON0 (0x1200) */
124#define AFE_DAC_CON0_AFE_ON (0x1 << 0)
125
126/* AFE_MEMIF_PBUF_SIZE (0x1238) */
127#define AFE_MEMIF_PBUF_SIZE_DLM_MASK (0x1 << 29)

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