mt2701-cs42448.c (7ae9fb1b7ecbb5d85d07857943f677fd1a559b18) mt2701-cs42448.c (de9e70137f006855a540f510a2c7dfb8850bedb7)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * mt2701-cs42448.c -- MT2701 CS42448 ALSA SoC machine driver
4 *
5 * Copyright (c) 2016 MediaTek Inc.
6 * Author: Ir Lian <ir.lian@mediatek.com>
7 * Garlic Tseng <garlic.tseng@mediatek.com>
8 */

--- 113 unchanged lines hidden (view full) ---

122
123static const struct snd_soc_ops mt2701_cs42448_48k_fe_ops = {
124 .startup = mt2701_cs42448_fe_ops_startup,
125};
126
127static int mt2701_cs42448_be_ops_hw_params(struct snd_pcm_substream *substream,
128 struct snd_pcm_hw_params *params)
129{
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * mt2701-cs42448.c -- MT2701 CS42448 ALSA SoC machine driver
4 *
5 * Copyright (c) 2016 MediaTek Inc.
6 * Author: Ir Lian <ir.lian@mediatek.com>
7 * Garlic Tseng <garlic.tseng@mediatek.com>
8 */

--- 113 unchanged lines hidden (view full) ---

122
123static const struct snd_soc_ops mt2701_cs42448_48k_fe_ops = {
124 .startup = mt2701_cs42448_fe_ops_startup,
125};
126
127static int mt2701_cs42448_be_ops_hw_params(struct snd_pcm_substream *substream,
128 struct snd_pcm_hw_params *params)
129{
130 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
131 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
132 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
130 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
131 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
132 struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
133 unsigned int mclk_rate;
134 unsigned int rate = params_rate(params);
135 unsigned int div_mclk_over_bck = rate > 192000 ? 2 : 4;
136 unsigned int div_bck_over_lrck = 64;
137
138 mclk_rate = rate * div_bck_over_lrck * div_mclk_over_bck;
139
140 /* mt2701 mclk */

--- 300 unchanged lines hidden --- 		133 unsigned int mclk_rate;
134 unsigned int rate = params_rate(params);
135 unsigned int div_mclk_over_bck = rate > 192000 ? 2 : 4;
136 unsigned int div_bck_over_lrck = 64;
137
138 mclk_rate = rate * div_bck_over_lrck * div_mclk_over_bck;
139
140 /* mt2701 mclk */

--- 300 unchanged lines hidden ---