fsl_xcvr.c (14e77332e74603efab8347c89d3cda447c3b97c9) fsl_xcvr.c (107d170dc46e14cfa575d1b995107ef2f2e51dfe)
1// SPDX-License-Identifier: GPL-2.0
2// Copyright 2019 NXP
3
4#include <linux/bitrev.h>
5#include <linux/clk.h>
6#include <linux/firmware.h>
7#include <linux/interrupt.h>
8#include <linux/module.h>

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929 { FSL_XCVR_ISR, 0x00000000 },
930 { FSL_XCVR_ISR_SET, 0x00000000 },
931 { FSL_XCVR_ISR_CLR, 0x00000000 },
932 { FSL_XCVR_ISR_TOG, 0x00000000 },
933 { FSL_XCVR_RX_DPTH_CTRL, 0x00002C89 },
934 { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00002C89 },
935 { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00002C89 },
936 { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00002C89 },
1// SPDX-License-Identifier: GPL-2.0
2// Copyright 2019 NXP
3
4#include <linux/bitrev.h>
5#include <linux/clk.h>
6#include <linux/firmware.h>
7#include <linux/interrupt.h>
8#include <linux/module.h>

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929 { FSL_XCVR_ISR, 0x00000000 },
930 { FSL_XCVR_ISR_SET, 0x00000000 },
931 { FSL_XCVR_ISR_CLR, 0x00000000 },
932 { FSL_XCVR_ISR_TOG, 0x00000000 },
933 { FSL_XCVR_RX_DPTH_CTRL, 0x00002C89 },
934 { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00002C89 },
935 { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00002C89 },
936 { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00002C89 },
937 { FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 },
938 { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 },
939 { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
940 { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
941 { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 },
942 { FSL_XCVR_RX_DPTH_BCR, 0x00000000 },
943 { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 },
944 { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 },
937 { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 },
938 { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 },
939 { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 },
940 { FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 },
941 { FSL_XCVR_TX_CS_DATA_0, 0x00000000 },
942 { FSL_XCVR_TX_CS_DATA_1, 0x00000000 },
943 { FSL_XCVR_TX_CS_DATA_2, 0x00000000 },
944 { FSL_XCVR_TX_CS_DATA_3, 0x00000000 },
945 { FSL_XCVR_TX_CS_DATA_4, 0x00000000 },
946 { FSL_XCVR_TX_CS_DATA_5, 0x00000000 },
945 { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 },
946 { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 },
947 { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 },
948 { FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 },
949 { FSL_XCVR_TX_CS_DATA_0, 0x00000000 },
950 { FSL_XCVR_TX_CS_DATA_1, 0x00000000 },
951 { FSL_XCVR_TX_CS_DATA_2, 0x00000000 },
952 { FSL_XCVR_TX_CS_DATA_3, 0x00000000 },
953 { FSL_XCVR_TX_CS_DATA_4, 0x00000000 },
954 { FSL_XCVR_TX_CS_DATA_5, 0x00000000 },
955 { FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 },
956 { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 },
957 { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
958 { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
959 { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 },
960 { FSL_XCVR_TX_DPTH_BCR, 0x00000000 },
961 { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 },
962 { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 },
947 { FSL_XCVR_DEBUG_REG_0, 0x00000000 },
948 { FSL_XCVR_DEBUG_REG_1, 0x00000000 },
949};
950
951static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
952{
953 switch (reg) {
954 case FSL_XCVR_VERSION:

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970 case FSL_XCVR_PHY_AI_CTRL_CLR:
971 case FSL_XCVR_PHY_AI_CTRL_TOG:
972 case FSL_XCVR_PHY_AI_RDATA:
973 case FSL_XCVR_CLK_CTRL:
974 case FSL_XCVR_RX_DPTH_CTRL:
975 case FSL_XCVR_RX_DPTH_CTRL_SET:
976 case FSL_XCVR_RX_DPTH_CTRL_CLR:
977 case FSL_XCVR_RX_DPTH_CTRL_TOG:
963 { FSL_XCVR_DEBUG_REG_0, 0x00000000 },
964 { FSL_XCVR_DEBUG_REG_1, 0x00000000 },
965};
966
967static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
968{
969 switch (reg) {
970 case FSL_XCVR_VERSION:

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986 case FSL_XCVR_PHY_AI_CTRL_CLR:
987 case FSL_XCVR_PHY_AI_CTRL_TOG:
988 case FSL_XCVR_PHY_AI_RDATA:
989 case FSL_XCVR_CLK_CTRL:
990 case FSL_XCVR_RX_DPTH_CTRL:
991 case FSL_XCVR_RX_DPTH_CTRL_SET:
992 case FSL_XCVR_RX_DPTH_CTRL_CLR:
993 case FSL_XCVR_RX_DPTH_CTRL_TOG:
994 case FSL_XCVR_RX_DPTH_CNTR_CTRL:
995 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
996 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
997 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
998 case FSL_XCVR_RX_DPTH_TSCR:
999 case FSL_XCVR_RX_DPTH_BCR:
1000 case FSL_XCVR_RX_DPTH_BCTR:
1001 case FSL_XCVR_RX_DPTH_BCRR:
978 case FSL_XCVR_TX_DPTH_CTRL:
979 case FSL_XCVR_TX_DPTH_CTRL_SET:
980 case FSL_XCVR_TX_DPTH_CTRL_CLR:
981 case FSL_XCVR_TX_DPTH_CTRL_TOG:
982 case FSL_XCVR_TX_CS_DATA_0:
983 case FSL_XCVR_TX_CS_DATA_1:
984 case FSL_XCVR_TX_CS_DATA_2:
985 case FSL_XCVR_TX_CS_DATA_3:
986 case FSL_XCVR_TX_CS_DATA_4:
987 case FSL_XCVR_TX_CS_DATA_5:
1002 case FSL_XCVR_TX_DPTH_CTRL:
1003 case FSL_XCVR_TX_DPTH_CTRL_SET:
1004 case FSL_XCVR_TX_DPTH_CTRL_CLR:
1005 case FSL_XCVR_TX_DPTH_CTRL_TOG:
1006 case FSL_XCVR_TX_CS_DATA_0:
1007 case FSL_XCVR_TX_CS_DATA_1:
1008 case FSL_XCVR_TX_CS_DATA_2:
1009 case FSL_XCVR_TX_CS_DATA_3:
1010 case FSL_XCVR_TX_CS_DATA_4:
1011 case FSL_XCVR_TX_CS_DATA_5:
1012 case FSL_XCVR_TX_DPTH_CNTR_CTRL:
1013 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
1014 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
1015 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
1016 case FSL_XCVR_TX_DPTH_TSCR:
1017 case FSL_XCVR_TX_DPTH_BCR:
1018 case FSL_XCVR_TX_DPTH_BCTR:
1019 case FSL_XCVR_TX_DPTH_BCRR:
988 case FSL_XCVR_DEBUG_REG_0:
989 case FSL_XCVR_DEBUG_REG_1:
990 return true;
991 default:
992 return false;
993 }
994}
995

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1012 case FSL_XCVR_PHY_AI_CTRL_CLR:
1013 case FSL_XCVR_PHY_AI_CTRL_TOG:
1014 case FSL_XCVR_PHY_AI_WDATA:
1015 case FSL_XCVR_CLK_CTRL:
1016 case FSL_XCVR_RX_DPTH_CTRL:
1017 case FSL_XCVR_RX_DPTH_CTRL_SET:
1018 case FSL_XCVR_RX_DPTH_CTRL_CLR:
1019 case FSL_XCVR_RX_DPTH_CTRL_TOG:
1020 case FSL_XCVR_DEBUG_REG_0:
1021 case FSL_XCVR_DEBUG_REG_1:
1022 return true;
1023 default:
1024 return false;
1025 }
1026}
1027

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1044 case FSL_XCVR_PHY_AI_CTRL_CLR:
1045 case FSL_XCVR_PHY_AI_CTRL_TOG:
1046 case FSL_XCVR_PHY_AI_WDATA:
1047 case FSL_XCVR_CLK_CTRL:
1048 case FSL_XCVR_RX_DPTH_CTRL:
1049 case FSL_XCVR_RX_DPTH_CTRL_SET:
1050 case FSL_XCVR_RX_DPTH_CTRL_CLR:
1051 case FSL_XCVR_RX_DPTH_CTRL_TOG:
1052 case FSL_XCVR_RX_DPTH_CNTR_CTRL:
1053 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
1054 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
1055 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
1020 case FSL_XCVR_TX_DPTH_CTRL_SET:
1021 case FSL_XCVR_TX_DPTH_CTRL_CLR:
1022 case FSL_XCVR_TX_DPTH_CTRL_TOG:
1023 case FSL_XCVR_TX_CS_DATA_0:
1024 case FSL_XCVR_TX_CS_DATA_1:
1025 case FSL_XCVR_TX_CS_DATA_2:
1026 case FSL_XCVR_TX_CS_DATA_3:
1027 case FSL_XCVR_TX_CS_DATA_4:
1028 case FSL_XCVR_TX_CS_DATA_5:
1056 case FSL_XCVR_TX_DPTH_CTRL_SET:
1057 case FSL_XCVR_TX_DPTH_CTRL_CLR:
1058 case FSL_XCVR_TX_DPTH_CTRL_TOG:
1059 case FSL_XCVR_TX_CS_DATA_0:
1060 case FSL_XCVR_TX_CS_DATA_1:
1061 case FSL_XCVR_TX_CS_DATA_2:
1062 case FSL_XCVR_TX_CS_DATA_3:
1063 case FSL_XCVR_TX_CS_DATA_4:
1064 case FSL_XCVR_TX_CS_DATA_5:
1065 case FSL_XCVR_TX_DPTH_CNTR_CTRL:
1066 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
1067 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
1068 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
1029 return true;
1030 default:
1031 return false;
1032 }
1033}
1034
1035static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg)
1036{

--- 352 unchanged lines hidden --- 		1069 return true;
1070 default:
1071 return false;
1072 }
1073}
1074
1075static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg)
1076{

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