fsl_mqs.c (6f47c7ae8c7afaf9ad291d39f0d3974f191a7946) fsl_mqs.c (401a1f021bbc5a81eb63742f62005629c4f8d747)
1// SPDX-License-Identifier: GPL-2.0
2//
3// ALSA SoC IMX MQS driver
4//
5// Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
6// Copyright 2019 NXP
7
8#include <linux/clk.h>

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23#define MQS_EN_SHIFT (28)
24#define MQS_SW_RST_MASK (0x1 << 24)
25#define MQS_SW_RST_SHIFT (24)
26#define MQS_OVERSAMPLE_MASK (0x1 << 20)
27#define MQS_OVERSAMPLE_SHIFT (20)
28#define MQS_CLK_DIV_MASK (0xFF << 0)
29#define MQS_CLK_DIV_SHIFT (0)
30
1// SPDX-License-Identifier: GPL-2.0
2//
3// ALSA SoC IMX MQS driver
4//
5// Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
6// Copyright 2019 NXP
7
8#include <linux/clk.h>

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23#define MQS_EN_SHIFT (28)
24#define MQS_SW_RST_MASK (0x1 << 24)
25#define MQS_SW_RST_SHIFT (24)
26#define MQS_OVERSAMPLE_MASK (0x1 << 20)
27#define MQS_OVERSAMPLE_SHIFT (20)
28#define MQS_CLK_DIV_MASK (0xFF << 0)
29#define MQS_CLK_DIV_SHIFT (0)
30
31enum reg_type {
32 TYPE_REG_OWN, /* module own register space */
33 TYPE_REG_GPR, /* register in GPR space */
34 TYPE_REG_SM, /* System Manager controls the register */
35};
36
31/**
32 * struct fsl_mqs_soc_data - soc specific data
33 *
37/**
38 * struct fsl_mqs_soc_data - soc specific data
39 *
34 * @use_gpr: control register is in General Purpose Register group
40 * @type: control register space type
35 * @ctrl_off: control register offset
36 * @en_mask: enable bit mask
37 * @en_shift: enable bit shift
38 * @rst_mask: reset bit mask
39 * @rst_shift: reset bit shift
40 * @osr_mask: oversample bit mask
41 * @osr_shift: oversample bit shift
42 * @div_mask: clock divider mask
43 * @div_shift: clock divider bit shift
44 */
45struct fsl_mqs_soc_data {
41 * @ctrl_off: control register offset
42 * @en_mask: enable bit mask
43 * @en_shift: enable bit shift
44 * @rst_mask: reset bit mask
45 * @rst_shift: reset bit shift
46 * @osr_mask: oversample bit mask
47 * @osr_shift: oversample bit shift
48 * @div_mask: clock divider mask
49 * @div_shift: clock divider bit shift
50 */
51struct fsl_mqs_soc_data {
46 bool use_gpr;
52 enum reg_type type;
47 int ctrl_off;
48 int en_mask;
49 int en_shift;
50 int rst_mask;
51 int rst_shift;
52 int osr_mask;
53 int osr_shift;
54 int div_mask;

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195 return -ENOMEM;
196
197 /* On i.MX6sx the MQS control register is in GPR domain
198 * But in i.MX8QM/i.MX8QXP the control register is moved
199 * to its own domain.
200 */
201 mqs_priv->soc = of_device_get_match_data(&pdev->dev);
202
53 int ctrl_off;
54 int en_mask;
55 int en_shift;
56 int rst_mask;
57 int rst_shift;
58 int osr_mask;
59 int osr_shift;
60 int div_mask;

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201 return -ENOMEM;
202
203 /* On i.MX6sx the MQS control register is in GPR domain
204 * But in i.MX8QM/i.MX8QXP the control register is moved
205 * to its own domain.
206 */
207 mqs_priv->soc = of_device_get_match_data(&pdev->dev);
208
203 if (mqs_priv->soc->use_gpr) {
209 if (mqs_priv->soc->type == TYPE_REG_GPR) {
204 gpr_np = of_parse_phandle(np, "gpr", 0);
205 if (!gpr_np) {
206 dev_err(&pdev->dev, "failed to get gpr node by phandle\n");
207 return -EINVAL;
208 }
209
210 mqs_priv->regmap = syscon_node_to_regmap(gpr_np);
211 of_node_put(gpr_np);

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299 SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend,
300 fsl_mqs_runtime_resume,
301 NULL)
302 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
303 pm_runtime_force_resume)
304};
305
306static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = {
210 gpr_np = of_parse_phandle(np, "gpr", 0);
211 if (!gpr_np) {
212 dev_err(&pdev->dev, "failed to get gpr node by phandle\n");
213 return -EINVAL;
214 }
215
216 mqs_priv->regmap = syscon_node_to_regmap(gpr_np);
217 of_node_put(gpr_np);

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305 SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend,
306 fsl_mqs_runtime_resume,
307 NULL)
308 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
309 pm_runtime_force_resume)
310};
311
312static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = {
307 .use_gpr = false,
313 .type = TYPE_REG_OWN,
308 .ctrl_off = REG_MQS_CTRL,
309 .en_mask = MQS_EN_MASK,
310 .en_shift = MQS_EN_SHIFT,
311 .rst_mask = MQS_SW_RST_MASK,
312 .rst_shift = MQS_SW_RST_SHIFT,
313 .osr_mask = MQS_OVERSAMPLE_MASK,
314 .osr_shift = MQS_OVERSAMPLE_SHIFT,
315 .div_mask = MQS_CLK_DIV_MASK,
316 .div_shift = MQS_CLK_DIV_SHIFT,
317};
318
319static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = {
314 .ctrl_off = REG_MQS_CTRL,
315 .en_mask = MQS_EN_MASK,
316 .en_shift = MQS_EN_SHIFT,
317 .rst_mask = MQS_SW_RST_MASK,
318 .rst_shift = MQS_SW_RST_SHIFT,
319 .osr_mask = MQS_OVERSAMPLE_MASK,
320 .osr_shift = MQS_OVERSAMPLE_SHIFT,
321 .div_mask = MQS_CLK_DIV_MASK,
322 .div_shift = MQS_CLK_DIV_SHIFT,
323};
324
325static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = {
320 .use_gpr = true,
326 .type = TYPE_REG_GPR,
321 .ctrl_off = IOMUXC_GPR2,
322 .en_mask = IMX6SX_GPR2_MQS_EN_MASK,
323 .en_shift = IMX6SX_GPR2_MQS_EN_SHIFT,
324 .rst_mask = IMX6SX_GPR2_MQS_SW_RST_MASK,
325 .rst_shift = IMX6SX_GPR2_MQS_SW_RST_SHIFT,
326 .osr_mask = IMX6SX_GPR2_MQS_OVERSAMPLE_MASK,
327 .osr_shift = IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT,
328 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK,
329 .div_shift = IMX6SX_GPR2_MQS_CLK_DIV_SHIFT,
330};
331
332static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = {
327 .ctrl_off = IOMUXC_GPR2,
328 .en_mask = IMX6SX_GPR2_MQS_EN_MASK,
329 .en_shift = IMX6SX_GPR2_MQS_EN_SHIFT,
330 .rst_mask = IMX6SX_GPR2_MQS_SW_RST_MASK,
331 .rst_shift = IMX6SX_GPR2_MQS_SW_RST_SHIFT,
332 .osr_mask = IMX6SX_GPR2_MQS_OVERSAMPLE_MASK,
333 .osr_shift = IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT,
334 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK,
335 .div_shift = IMX6SX_GPR2_MQS_CLK_DIV_SHIFT,
336};
337
338static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = {
333 .use_gpr = true,
339 .type = TYPE_REG_GPR,
334 .ctrl_off = 0x20,
335 .en_mask = BIT(1),
336 .en_shift = 1,
337 .rst_mask = BIT(2),
338 .rst_shift = 2,
339 .osr_mask = BIT(3),
340 .osr_shift = 3,
341 .div_mask = GENMASK(15, 8),
342 .div_shift = 8,
343};
344
340 .ctrl_off = 0x20,
341 .en_mask = BIT(1),
342 .en_shift = 1,
343 .rst_mask = BIT(2),
344 .rst_shift = 2,
345 .osr_mask = BIT(3),
346 .osr_shift = 3,
347 .div_mask = GENMASK(15, 8),
348 .div_shift = 8,
349};
350
351static const struct fsl_mqs_soc_data fsl_mqs_imx95_aon_data = {
352 .type = TYPE_REG_SM,
353 .ctrl_off = 0x88,
354 .en_mask = BIT(1),
355 .en_shift = 1,
356 .rst_mask = BIT(2),
357 .rst_shift = 2,
358 .osr_mask = BIT(3),
359 .osr_shift = 3,
360 .div_mask = GENMASK(15, 8),
361 .div_shift = 8,
362};
363
364static const struct fsl_mqs_soc_data fsl_mqs_imx95_netc_data = {
365 .type = TYPE_REG_GPR,
366 .ctrl_off = 0x0,
367 .en_mask = BIT(2),
368 .en_shift = 2,
369 .rst_mask = BIT(3),
370 .rst_shift = 3,
371 .osr_mask = BIT(4),
372 .osr_shift = 4,
373 .div_mask = GENMASK(16, 9),
374 .div_shift = 9,
375};
376
345static const struct of_device_id fsl_mqs_dt_ids[] = {
346 { .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data },
347 { .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data },
348 { .compatible = "fsl,imx93-mqs", .data = &fsl_mqs_imx93_data },
377static const struct of_device_id fsl_mqs_dt_ids[] = {
378 { .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data },
379 { .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data },
380 { .compatible = "fsl,imx93-mqs", .data = &fsl_mqs_imx93_data },
381 { .compatible = "fsl,imx95-aonmix-mqs", .data = &fsl_mqs_imx95_aon_data },
382 { .compatible = "fsl,imx95-netcmix-mqs", .data = &fsl_mqs_imx95_netc_data },
349 {}
350};
351MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids);
352
353static struct platform_driver fsl_mqs_driver = {
354 .probe = fsl_mqs_probe,
355 .remove_new = fsl_mqs_remove,
356 .driver = {

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384};
385MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids);
386
387static struct platform_driver fsl_mqs_driver = {
388 .probe = fsl_mqs_probe,
389 .remove_new = fsl_mqs_remove,
390 .driver = {

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