fsl_mqs.c (00778276cf4c611882219ab7aba9664c48981f1a) fsl_mqs.c (063c915502b914a5a621458c763dfc28286f7606)
1// SPDX-License-Identifier: GPL-2.0
2//
3// ALSA SoC IMX MQS driver
4//
5// Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
6// Copyright 2019 NXP
7
8#include <linux/clk.h>
9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/mfd/syscon.h>
12#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
1// SPDX-License-Identifier: GPL-2.0
2//
3// ALSA SoC IMX MQS driver
4//
5// Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
6// Copyright 2019 NXP
7
8#include <linux/clk.h>
9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/mfd/syscon.h>
12#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
13#include <linux/of_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/of.h>
15#include <linux/pm.h>
16#include <linux/slab.h>
17#include <sound/soc.h>
18#include <sound/pcm.h>
19#include <sound/initval.h>
20
21#define REG_MQS_CTRL 0x00
22
23#define MQS_EN_MASK (0x1 << 28)
24#define MQS_EN_SHIFT (28)
25#define MQS_SW_RST_MASK (0x1 << 24)
26#define MQS_SW_RST_SHIFT (24)
27#define MQS_OVERSAMPLE_MASK (0x1 << 20)
28#define MQS_OVERSAMPLE_SHIFT (20)
29#define MQS_CLK_DIV_MASK (0xFF << 0)
30#define MQS_CLK_DIV_SHIFT (0)
31
14#include <linux/pm_runtime.h>
15#include <linux/of.h>
16#include <linux/pm.h>
17#include <linux/slab.h>
18#include <sound/soc.h>
19#include <sound/pcm.h>
20#include <sound/initval.h>
21
22#define REG_MQS_CTRL 0x00
23
24#define MQS_EN_MASK (0x1 << 28)
25#define MQS_EN_SHIFT (28)
26#define MQS_SW_RST_MASK (0x1 << 24)
27#define MQS_SW_RST_SHIFT (24)
28#define MQS_OVERSAMPLE_MASK (0x1 << 20)
29#define MQS_OVERSAMPLE_SHIFT (20)
30#define MQS_CLK_DIV_MASK (0xFF << 0)
31#define MQS_CLK_DIV_SHIFT (0)
32
33/**
34 * struct fsl_mqs_soc_data - soc specific data
35 *
36 * @use_gpr: control register is in General Purpose Register group
37 * @ctrl_off: control register offset
38 * @en_mask: enable bit mask
39 * @en_shift: enable bit shift
40 * @rst_mask: reset bit mask
41 * @rst_shift: reset bit shift
42 * @osr_mask: oversample bit mask
43 * @osr_shift: oversample bit shift
44 * @div_mask: clock divider mask
45 * @div_shift: clock divider bit shift
46 */
47struct fsl_mqs_soc_data {
48 bool use_gpr;
49 int ctrl_off;
50 int en_mask;
51 int en_shift;
52 int rst_mask;
53 int rst_shift;
54 int osr_mask;
55 int osr_shift;
56 int div_mask;
57 int div_shift;
58};
59
32/* codec private data */
33struct fsl_mqs {
34 struct regmap *regmap;
35 struct clk *mclk;
36 struct clk *ipg;
60/* codec private data */
61struct fsl_mqs {
62 struct regmap *regmap;
63 struct clk *mclk;
64 struct clk *ipg;
65 const struct fsl_mqs_soc_data *soc;
37
66
38 unsigned int reg_iomuxc_gpr2;
39 unsigned int reg_mqs_ctrl;
67 unsigned int reg_mqs_ctrl;
40 bool use_gpr;
41};
42
43#define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
44#define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE
45
46static int fsl_mqs_hw_params(struct snd_pcm_substream *substream,
47 struct snd_pcm_hw_params *params,
48 struct snd_soc_dai *dai)

--- 11 unchanged lines hidden (view full) ---

60 * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate;
61 * if repeat_rate is 8, mqs can achieve better quality.
62 * oversample rate is fix to 32 currently.
63 */
64 div = mclk_rate / (32 * lrclk * 2 * 8);
65 res = mclk_rate % (32 * lrclk * 2 * 8);
66
67 if (res == 0 && div > 0 && div <= 256) {
68};
69
70#define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
71#define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE
72
73static int fsl_mqs_hw_params(struct snd_pcm_substream *substream,
74 struct snd_pcm_hw_params *params,
75 struct snd_soc_dai *dai)

--- 11 unchanged lines hidden (view full) ---

87 * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate;
88 * if repeat_rate is 8, mqs can achieve better quality.
89 * oversample rate is fix to 32 currently.
90 */
91 div = mclk_rate / (32 * lrclk * 2 * 8);
92 res = mclk_rate % (32 * lrclk * 2 * 8);
93
94 if (res == 0 && div > 0 && div <= 256) {
68 if (mqs_priv->use_gpr) {
69 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
70 IMX6SX_GPR2_MQS_CLK_DIV_MASK,
71 (div - 1) << IMX6SX_GPR2_MQS_CLK_DIV_SHIFT);
72 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
73 IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 0);
74 } else {
75 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
76 MQS_CLK_DIV_MASK,
77 (div - 1) << MQS_CLK_DIV_SHIFT);
78 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
79 MQS_OVERSAMPLE_MASK, 0);
80 }
95 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
96 mqs_priv->soc->div_mask,
97 (div - 1) << mqs_priv->soc->div_shift);
98 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
99 mqs_priv->soc->osr_mask, 0);
81 } else {
82 dev_err(component->dev, "can't get proper divider\n");
83 }
84
85 return 0;
86}
87
88static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)

--- 9 unchanged lines hidden (view full) ---

98 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
99 case SND_SOC_DAIFMT_NB_NF:
100 break;
101 default:
102 return -EINVAL;
103 }
104
105 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
100 } else {
101 dev_err(component->dev, "can't get proper divider\n");
102 }
103
104 return 0;
105}
106
107static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)

--- 9 unchanged lines hidden (view full) ---

117 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
118 case SND_SOC_DAIFMT_NB_NF:
119 break;
120 default:
121 return -EINVAL;
122 }
123
124 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
106 case SND_SOC_DAIFMT_BP_FP:
125 case SND_SOC_DAIFMT_CBC_CFC:
107 break;
108 default:
109 return -EINVAL;
110 }
111
112 return 0;
113}
114
115static int fsl_mqs_startup(struct snd_pcm_substream *substream,
116 struct snd_soc_dai *dai)
117{
118 struct snd_soc_component *component = dai->component;
119 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
120
126 break;
127 default:
128 return -EINVAL;
129 }
130
131 return 0;
132}
133
134static int fsl_mqs_startup(struct snd_pcm_substream *substream,
135 struct snd_soc_dai *dai)
136{
137 struct snd_soc_component *component = dai->component;
138 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
139
121 if (mqs_priv->use_gpr)
122 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
123 IMX6SX_GPR2_MQS_EN_MASK,
124 1 << IMX6SX_GPR2_MQS_EN_SHIFT);
125 else
126 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
127 MQS_EN_MASK,
128 1 << MQS_EN_SHIFT);
140 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
141 mqs_priv->soc->en_mask,
142 1 << mqs_priv->soc->en_shift);
129 return 0;
130}
131
132static void fsl_mqs_shutdown(struct snd_pcm_substream *substream,
133 struct snd_soc_dai *dai)
134{
135 struct snd_soc_component *component = dai->component;
136 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
137
143 return 0;
144}
145
146static void fsl_mqs_shutdown(struct snd_pcm_substream *substream,
147 struct snd_soc_dai *dai)
148{
149 struct snd_soc_component *component = dai->component;
150 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
151
138 if (mqs_priv->use_gpr)
139 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2,
140 IMX6SX_GPR2_MQS_EN_MASK, 0);
141 else
142 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL,
143 MQS_EN_MASK, 0);
152 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
153 mqs_priv->soc->en_mask, 0);
144}
145
146static const struct snd_soc_component_driver soc_codec_fsl_mqs = {
147 .idle_bias_on = 1,
148 .non_legacy_dai_naming = 1,
149};
150
151static const struct snd_soc_dai_ops fsl_mqs_dai_ops = {

--- 34 unchanged lines hidden (view full) ---

186 mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL);
187 if (!mqs_priv)
188 return -ENOMEM;
189
190 /* On i.MX6sx the MQS control register is in GPR domain
191 * But in i.MX8QM/i.MX8QXP the control register is moved
192 * to its own domain.
193 */
154}
155
156static const struct snd_soc_component_driver soc_codec_fsl_mqs = {
157 .idle_bias_on = 1,
158 .non_legacy_dai_naming = 1,
159};
160
161static const struct snd_soc_dai_ops fsl_mqs_dai_ops = {

--- 34 unchanged lines hidden (view full) ---

196 mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL);
197 if (!mqs_priv)
198 return -ENOMEM;
199
200 /* On i.MX6sx the MQS control register is in GPR domain
201 * But in i.MX8QM/i.MX8QXP the control register is moved
202 * to its own domain.
203 */
194 if (of_device_is_compatible(np, "fsl,imx8qm-mqs"))
195 mqs_priv->use_gpr = false;
196 else
197 mqs_priv->use_gpr = true;
204 mqs_priv->soc = of_device_get_match_data(&pdev->dev);
198
205
199 if (mqs_priv->use_gpr) {
206 if (mqs_priv->soc->use_gpr) {
200 gpr_np = of_parse_phandle(np, "gpr", 0);
201 if (!gpr_np) {
202 dev_err(&pdev->dev, "failed to get gpr node by phandle\n");
203 return -EINVAL;
204 }
205
206 mqs_priv->regmap = syscon_node_to_regmap(gpr_np);
207 if (IS_ERR(mqs_priv->regmap)) {

--- 67 unchanged lines hidden (view full) ---

275
276 ret = clk_prepare_enable(mqs_priv->mclk);
277 if (ret) {
278 dev_err(dev, "failed to enable mclk clock\n");
279 clk_disable_unprepare(mqs_priv->ipg);
280 return ret;
281 }
282
207 gpr_np = of_parse_phandle(np, "gpr", 0);
208 if (!gpr_np) {
209 dev_err(&pdev->dev, "failed to get gpr node by phandle\n");
210 return -EINVAL;
211 }
212
213 mqs_priv->regmap = syscon_node_to_regmap(gpr_np);
214 if (IS_ERR(mqs_priv->regmap)) {

--- 67 unchanged lines hidden (view full) ---

282
283 ret = clk_prepare_enable(mqs_priv->mclk);
284 if (ret) {
285 dev_err(dev, "failed to enable mclk clock\n");
286 clk_disable_unprepare(mqs_priv->ipg);
287 return ret;
288 }
289
283 if (mqs_priv->use_gpr)
284 regmap_write(mqs_priv->regmap, IOMUXC_GPR2,
285 mqs_priv->reg_iomuxc_gpr2);
286 else
287 regmap_write(mqs_priv->regmap, REG_MQS_CTRL,
288 mqs_priv->reg_mqs_ctrl);
290 regmap_write(mqs_priv->regmap, mqs_priv->soc->ctrl_off, mqs_priv->reg_mqs_ctrl);
289 return 0;
290}
291
292static int fsl_mqs_runtime_suspend(struct device *dev)
293{
294 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
295
291 return 0;
292}
293
294static int fsl_mqs_runtime_suspend(struct device *dev)
295{
296 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
297
296 if (mqs_priv->use_gpr)
297 regmap_read(mqs_priv->regmap, IOMUXC_GPR2,
298 &mqs_priv->reg_iomuxc_gpr2);
299 else
300 regmap_read(mqs_priv->regmap, REG_MQS_CTRL,
301 &mqs_priv->reg_mqs_ctrl);
298 regmap_read(mqs_priv->regmap, mqs_priv->soc->ctrl_off, &mqs_priv->reg_mqs_ctrl);
302
303 clk_disable_unprepare(mqs_priv->mclk);
304 clk_disable_unprepare(mqs_priv->ipg);
305
306 return 0;
307}
308#endif
309
310static const struct dev_pm_ops fsl_mqs_pm_ops = {
311 SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend,
312 fsl_mqs_runtime_resume,
313 NULL)
314 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
315 pm_runtime_force_resume)
316};
317
299
300 clk_disable_unprepare(mqs_priv->mclk);
301 clk_disable_unprepare(mqs_priv->ipg);
302
303 return 0;
304}
305#endif
306
307static const struct dev_pm_ops fsl_mqs_pm_ops = {
308 SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend,
309 fsl_mqs_runtime_resume,
310 NULL)
311 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
312 pm_runtime_force_resume)
313};
314
315static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = {
316 .use_gpr = false,
317 .ctrl_off = REG_MQS_CTRL,
318 .en_mask = MQS_EN_MASK,
319 .en_shift = MQS_EN_SHIFT,
320 .rst_mask = MQS_SW_RST_MASK,
321 .rst_shift = MQS_SW_RST_SHIFT,
322 .osr_mask = MQS_OVERSAMPLE_MASK,
323 .osr_shift = MQS_OVERSAMPLE_SHIFT,
324 .div_mask = MQS_CLK_DIV_MASK,
325 .div_shift = MQS_CLK_DIV_SHIFT,
326};
327
328static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = {
329 .use_gpr = true,
330 .ctrl_off = IOMUXC_GPR2,
331 .en_mask = IMX6SX_GPR2_MQS_EN_MASK,
332 .en_shift = IMX6SX_GPR2_MQS_EN_SHIFT,
333 .rst_mask = IMX6SX_GPR2_MQS_SW_RST_MASK,
334 .rst_shift = IMX6SX_GPR2_MQS_SW_RST_SHIFT,
335 .osr_mask = IMX6SX_GPR2_MQS_OVERSAMPLE_MASK,
336 .osr_shift = IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT,
337 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK,
338 .div_shift = IMX6SX_GPR2_MQS_CLK_DIV_SHIFT,
339};
340
318static const struct of_device_id fsl_mqs_dt_ids[] = {
341static const struct of_device_id fsl_mqs_dt_ids[] = {
319 { .compatible = "fsl,imx8qm-mqs", },
320 { .compatible = "fsl,imx6sx-mqs", },
342 { .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data },
343 { .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data },
321 {}
322};
323MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids);
324
325static struct platform_driver fsl_mqs_driver = {
326 .probe = fsl_mqs_probe,
327 .remove = fsl_mqs_remove,
328 .driver = {

--- 12 unchanged lines hidden --- 		344 {}
345};
346MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids);
347
348static struct platform_driver fsl_mqs_driver = {
349 .probe = fsl_mqs_probe,
350 .remove = fsl_mqs_remove,
351 .driver = {

--- 12 unchanged lines hidden ---