uda1380.c (cf7af01aa77ec1b17687f5328ce0a598709efd59) uda1380.c (8614d310a2ba78cfc73ab12da112c3115801f94e)
1/*
2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>

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34#include "uda1380.h"
35
36/* codec private data */
37struct uda1380_priv {
38 struct snd_soc_codec *codec;
39 u16 reg_cache[UDA1380_CACHEREGNUM];
40 unsigned int dac_clk;
41 struct work_struct work;
1/*
2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>

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34#include "uda1380.h"
35
36/* codec private data */
37struct uda1380_priv {
38 struct snd_soc_codec *codec;
39 u16 reg_cache[UDA1380_CACHEREGNUM];
40 unsigned int dac_clk;
41 struct work_struct work;
42 void *control_data;
42};
43
44/*
45 * uda1380 register cache
46 */
47static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
48 0x0502, 0x0000, 0x0000, 0x3f3f,
49 0x0202, 0x0000, 0x0000, 0x0000,

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124 }
125 if (reg >= 0x10)
126 clear_bit(reg - 0x10, &uda1380_cache_dirty);
127 return 0;
128 } else
129 return -EIO;
130}
131
43};
44
45/*
46 * uda1380 register cache
47 */
48static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
49 0x0502, 0x0000, 0x0000, 0x3f3f,
50 0x0202, 0x0000, 0x0000, 0x0000,

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125 }
126 if (reg >= 0x10)
127 clear_bit(reg - 0x10, &uda1380_cache_dirty);
128 return 0;
129 } else
130 return -EIO;
131}
132
132#define uda1380_reset(c) uda1380_write(c, UDA1380_RESET, 0)
133static void uda1380_sync_cache(struct snd_soc_codec *codec)
134{
135 int reg;
136 u8 data[3];
137 u16 *cache = codec->reg_cache;
133
138
139 /* Sync reg_cache with the hardware */
140 for (reg = 0; reg < UDA1380_MVOL; reg++) {
141 data[0] = reg;
142 data[1] = (cache[reg] & 0xff00) >> 8;
143 data[2] = cache[reg] & 0x00ff;
144 if (codec->hw_write(codec->control_data, data, 3) != 3)
145 dev_err(codec->dev, "%s: write to reg 0x%x failed\n",
146 __func__, reg);
147 }
148}
149
150static int uda1380_reset(struct snd_soc_codec *codec)
151{
152 struct uda1380_platform_data *pdata = codec->dev->platform_data;
153
154 if (gpio_is_valid(pdata->gpio_reset)) {
155 gpio_set_value(pdata->gpio_reset, 1);
156 mdelay(1);
157 gpio_set_value(pdata->gpio_reset, 0);
158 } else {
159 u8 data[3];
160
161 data[0] = UDA1380_RESET;
162 data[1] = 0;
163 data[2] = 0;
164
165 if (codec->hw_write(codec->control_data, data, 3) != 3) {
166 dev_err(codec->dev, "%s: failed\n", __func__);
167 return -EIO;
168 }
169 }
170
171 return 0;
172}
173
134static void uda1380_flush_work(struct work_struct *work)
135{
136 struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
137 struct snd_soc_codec *uda1380_codec = uda1380->codec;
138 int bit, reg;
139
140 for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
141 reg = 0x10 + bit;

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555
556 uda1380_write(codec, UDA1380_CLK, clk);
557}
558
559static int uda1380_set_bias_level(struct snd_soc_codec *codec,
560 enum snd_soc_bias_level level)
561{
562 int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
174static void uda1380_flush_work(struct work_struct *work)
175{
176 struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
177 struct snd_soc_codec *uda1380_codec = uda1380->codec;
178 int bit, reg;
179
180 for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
181 reg = 0x10 + bit;

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595
596 uda1380_write(codec, UDA1380_CLK, clk);
597}
598
599static int uda1380_set_bias_level(struct snd_soc_codec *codec,
600 enum snd_soc_bias_level level)
601{
602 int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
603 int reg;
604 struct uda1380_platform_data *pdata = codec->dev->platform_data;
563
605
606 if (codec->bias_level == level)
607 return 0;
608
564 switch (level) {
565 case SND_SOC_BIAS_ON:
566 case SND_SOC_BIAS_PREPARE:
609 switch (level) {
610 case SND_SOC_BIAS_ON:
611 case SND_SOC_BIAS_PREPARE:
612 /* ADC, DAC on */
567 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
568 break;
569 case SND_SOC_BIAS_STANDBY:
613 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
614 break;
615 case SND_SOC_BIAS_STANDBY:
570 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS);
571 break;
572 case SND_SOC_BIAS_OFF:
616 if (codec->bias_level == SND_SOC_BIAS_OFF) {
617 if (gpio_is_valid(pdata->gpio_power)) {
618 gpio_set_value(pdata->gpio_power, 1);
619 uda1380_reset(codec);
620 }
621
622 uda1380_sync_cache(codec);
623 }
573 uda1380_write(codec, UDA1380_PM, 0x0);
574 break;
624 uda1380_write(codec, UDA1380_PM, 0x0);
625 break;
626 case SND_SOC_BIAS_OFF:
627 if (!gpio_is_valid(pdata->gpio_power))
628 break;
629
630 gpio_set_value(pdata->gpio_power, 0);
631
632 /* Mark mixer regs cache dirty to sync them with
633 * codec regs on power on.
634 */
635 for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
636 set_bit(reg - 0x10, &uda1380_cache_dirty);
575 }
576 codec->bias_level = level;
577 return 0;
578}
579
580#define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
581 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
582 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)

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646static int uda1380_suspend(struct snd_soc_codec *codec, pm_message_t state)
647{
648 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
649 return 0;
650}
651
652static int uda1380_resume(struct snd_soc_codec *codec)
653{
637 }
638 codec->bias_level = level;
639 return 0;
640}
641
642#define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
643 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
644 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)

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708static int uda1380_suspend(struct snd_soc_codec *codec, pm_message_t state)
709{
710 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
711 return 0;
712}
713
714static int uda1380_resume(struct snd_soc_codec *codec)
715{
654 int i;
655 u8 data[2];
656 u16 *cache = codec->reg_cache;
657
658 /* Sync reg_cache with the hardware */
659 for (i = 0; i < ARRAY_SIZE(uda1380_reg); i++) {
660 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
661 data[1] = cache[i] & 0x00ff;
662 codec->hw_write(codec->control_data, data, 2);
663 }
664 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
665 return 0;
666}
667
668static int uda1380_probe(struct snd_soc_codec *codec)
669{
670 struct uda1380_platform_data *pdata =codec->dev->platform_data;
671 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
672 int ret;
673
716 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
717 return 0;
718}
719
720static int uda1380_probe(struct snd_soc_codec *codec)
721{
722 struct uda1380_platform_data *pdata =codec->dev->platform_data;
723 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
724 int ret;
725
726 uda1380->codec = codec;
727
674 codec->hw_write = (hw_write_t)i2c_master_send;
728 codec->hw_write = (hw_write_t)i2c_master_send;
729 codec->control_data = uda1380->control_data;
675
730
676 if (!pdata || !pdata->gpio_power || !pdata->gpio_reset)
731 if (!pdata)
677 return -EINVAL;
678
732 return -EINVAL;
733
679 ret = gpio_request(pdata->gpio_power, "uda1380 power");
680 if (ret)
681 return ret;
682 ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
683 if (ret)
684 goto err_gpio;
734 if (gpio_is_valid(pdata->gpio_reset)) {
735 ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
736 if (ret)
737 goto err_out;
738 ret = gpio_direction_output(pdata->gpio_reset, 0);
739 if (ret)
740 goto err_gpio_reset_conf;
741 }
685
742
686 gpio_direction_output(pdata->gpio_power, 1);
687
688 /* we may need to have the clock running here - pH5 */
689 gpio_direction_output(pdata->gpio_reset, 1);
690 udelay(5);
691 gpio_set_value(pdata->gpio_reset, 0);
692
693 ret = uda1380_reset(codec);
694 if (ret < 0) {
695 dev_err(codec->dev, "Failed to issue reset\n");
696 goto err_reset;
743 if (gpio_is_valid(pdata->gpio_power)) {
744 ret = gpio_request(pdata->gpio_power, "uda1380 power");
745 if (ret)
746 goto err_gpio;
747 ret = gpio_direction_output(pdata->gpio_power, 0);
748 if (ret)
749 goto err_gpio_power_conf;
750 } else {
751 ret = uda1380_reset(codec);
752 if (ret) {
753 dev_err(codec->dev, "Failed to issue reset\n");
754 goto err_reset;
755 }
697 }
698
699 INIT_WORK(&uda1380->work, uda1380_flush_work);
700
701 /* power on device */
702 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
703 /* set clock input */
704 switch (pdata->dac_clk) {
705 case UDA1380_DAC_CLK_SYSCLK:
756 }
757
758 INIT_WORK(&uda1380->work, uda1380_flush_work);
759
760 /* power on device */
761 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
762 /* set clock input */
763 switch (pdata->dac_clk) {
764 case UDA1380_DAC_CLK_SYSCLK:
706 uda1380_write(codec, UDA1380_CLK, 0);
765 uda1380_write_reg_cache(codec, UDA1380_CLK, 0);
707 break;
708 case UDA1380_DAC_CLK_WSPLL:
766 break;
767 case UDA1380_DAC_CLK_WSPLL:
709 uda1380_write(codec, UDA1380_CLK, R00_DAC_CLK);
768 uda1380_write_reg_cache(codec, UDA1380_CLK,
769 R00_DAC_CLK);
710 break;
711 }
712
713 snd_soc_add_controls(codec, uda1380_snd_controls,
714 ARRAY_SIZE(uda1380_snd_controls));
715 uda1380_add_widgets(codec);
716
717 return 0;
718
719err_reset:
770 break;
771 }
772
773 snd_soc_add_controls(codec, uda1380_snd_controls,
774 ARRAY_SIZE(uda1380_snd_controls));
775 uda1380_add_widgets(codec);
776
777 return 0;
778
779err_reset:
720 gpio_set_value(pdata->gpio_power, 0);
721 gpio_free(pdata->gpio_reset);
780err_gpio_power_conf:
781 if (gpio_is_valid(pdata->gpio_power))
782 gpio_free(pdata->gpio_power);
783
784err_gpio_reset_conf:
722err_gpio:
785err_gpio:
723 gpio_free(pdata->gpio_power);
786 if (gpio_is_valid(pdata->gpio_reset))
787 gpio_free(pdata->gpio_reset);
788err_out:
724 return ret;
725}
726
727/* power down chip */
728static int uda1380_remove(struct snd_soc_codec *codec)
729{
730 struct uda1380_platform_data *pdata =codec->dev->platform_data;
731
732 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
733
789 return ret;
790}
791
792/* power down chip */
793static int uda1380_remove(struct snd_soc_codec *codec)
794{
795 struct uda1380_platform_data *pdata =codec->dev->platform_data;
796
797 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
798
734 gpio_set_value(pdata->gpio_power, 0);
735 gpio_free(pdata->gpio_reset);
736 gpio_free(pdata->gpio_power);
737
738 return 0;
739}
740
741static struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
742 .probe = uda1380_probe,
743 .remove = uda1380_remove,
744 .suspend = uda1380_suspend,
745 .resume = uda1380_resume,
799 gpio_free(pdata->gpio_reset);
800 gpio_free(pdata->gpio_power);
801
802 return 0;
803}
804
805static struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
806 .probe = uda1380_probe,
807 .remove = uda1380_remove,
808 .suspend = uda1380_suspend,
809 .resume = uda1380_resume,
746 .read = uda1380_read_reg_cache,
747 .write = uda1380_write,
810 .read = uda1380_read_reg_cache,
811 .write = uda1380_write,
748 .set_bias_level = uda1380_set_bias_level,
749 .reg_cache_size = ARRAY_SIZE(uda1380_reg),
750 .reg_word_size = sizeof(u16),
751 .reg_cache_default = uda1380_reg,
752 .reg_cache_step = 1,
753};
754
755#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
756static __devinit int uda1380_i2c_probe(struct i2c_client *i2c,
757 const struct i2c_device_id *id)
758{
759 struct uda1380_priv *uda1380;
760 int ret;
761
762 uda1380 = kzalloc(sizeof(struct uda1380_priv), GFP_KERNEL);
763 if (uda1380 == NULL)
764 return -ENOMEM;
765
766 i2c_set_clientdata(i2c, uda1380);
812 .set_bias_level = uda1380_set_bias_level,
813 .reg_cache_size = ARRAY_SIZE(uda1380_reg),
814 .reg_word_size = sizeof(u16),
815 .reg_cache_default = uda1380_reg,
816 .reg_cache_step = 1,
817};
818
819#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
820static __devinit int uda1380_i2c_probe(struct i2c_client *i2c,
821 const struct i2c_device_id *id)
822{
823 struct uda1380_priv *uda1380;
824 int ret;
825
826 uda1380 = kzalloc(sizeof(struct uda1380_priv), GFP_KERNEL);
827 if (uda1380 == NULL)
828 return -ENOMEM;
829
830 i2c_set_clientdata(i2c, uda1380);
831 uda1380->control_data = i2c;
767
768 ret = snd_soc_register_codec(&i2c->dev,
769 &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
770 if (ret < 0)
771 kfree(uda1380);
772 return ret;
773}
774

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833 ret = snd_soc_register_codec(&i2c->dev,
834 &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
835 if (ret < 0)
836 kfree(uda1380);
837 return ret;
838}
839

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