uda1380.c (ce8ee02d519ab20c5b87d3b3929b5e44ad89e26f) uda1380.c (b40822d9e8bc7fe43de1c68ab3ea5a485ba6a4fa)
1/*
2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>

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29#include <sound/soc.h>
30#include <sound/tlv.h>
31#include <sound/uda1380.h>
32
33#include "uda1380.h"
34
35/* codec private data */
36struct uda1380_priv {
1/*
2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>

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29#include <sound/soc.h>
30#include <sound/tlv.h>
31#include <sound/uda1380.h>
32
33#include "uda1380.h"
34
35/* codec private data */
36struct uda1380_priv {
37 struct snd_soc_codec *codec;
37 struct snd_soc_component *component;
38 unsigned int dac_clk;
39 struct work_struct work;
40 struct i2c_client *i2c;
41 u16 *reg_cache;
42};
43
44/*
45 * uda1380 register cache

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56 0x0000, 0x8000, 0x0002, 0x0000,
57};
58
59static unsigned long uda1380_cache_dirty;
60
61/*
62 * read uda1380 register cache
63 */
38 unsigned int dac_clk;
39 struct work_struct work;
40 struct i2c_client *i2c;
41 u16 *reg_cache;
42};
43
44/*
45 * uda1380 register cache

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56 0x0000, 0x8000, 0x0002, 0x0000,
57};
58
59static unsigned long uda1380_cache_dirty;
60
61/*
62 * read uda1380 register cache
63 */
64static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
64static inline unsigned int uda1380_read_reg_cache(struct snd_soc_component *component,
65 unsigned int reg)
66{
65 unsigned int reg)
66{
67 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
67 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
68 u16 *cache = uda1380->reg_cache;
69
70 if (reg == UDA1380_RESET)
71 return 0;
72 if (reg >= UDA1380_CACHEREGNUM)
73 return -1;
74 return cache[reg];
75}
76
77/*
78 * write uda1380 register cache
79 */
68 u16 *cache = uda1380->reg_cache;
69
70 if (reg == UDA1380_RESET)
71 return 0;
72 if (reg >= UDA1380_CACHEREGNUM)
73 return -1;
74 return cache[reg];
75}
76
77/*
78 * write uda1380 register cache
79 */
80static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
80static inline void uda1380_write_reg_cache(struct snd_soc_component *component,
81 u16 reg, unsigned int value)
82{
81 u16 reg, unsigned int value)
82{
83 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
83 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
84 u16 *cache = uda1380->reg_cache;
85
86 if (reg >= UDA1380_CACHEREGNUM)
87 return;
88 if ((reg >= 0x10) && (cache[reg] != value))
89 set_bit(reg - 0x10, &uda1380_cache_dirty);
90 cache[reg] = value;
91}
92
93/*
94 * write to the UDA1380 register space
95 */
84 u16 *cache = uda1380->reg_cache;
85
86 if (reg >= UDA1380_CACHEREGNUM)
87 return;
88 if ((reg >= 0x10) && (cache[reg] != value))
89 set_bit(reg - 0x10, &uda1380_cache_dirty);
90 cache[reg] = value;
91}
92
93/*
94 * write to the UDA1380 register space
95 */
96static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
96static int uda1380_write(struct snd_soc_component *component, unsigned int reg,
97 unsigned int value)
98{
97 unsigned int value)
98{
99 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
99 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
100 u8 data[3];
101
102 /* data is
103 * data[0] is register offset
104 * data[1] is MS byte
105 * data[2] is LS byte
106 */
107 data[0] = reg;
108 data[1] = (value & 0xff00) >> 8;
109 data[2] = value & 0x00ff;
110
100 u8 data[3];
101
102 /* data is
103 * data[0] is register offset
104 * data[1] is MS byte
105 * data[2] is LS byte
106 */
107 data[0] = reg;
108 data[1] = (value & 0xff00) >> 8;
109 data[2] = value & 0x00ff;
110
111 uda1380_write_reg_cache(codec, reg, value);
111 uda1380_write_reg_cache(component, reg, value);
112
113 /* the interpolator & decimator regs must only be written when the
114 * codec DAI is active.
115 */
112
113 /* the interpolator & decimator regs must only be written when the
114 * codec DAI is active.
115 */
116 if (!snd_soc_codec_is_active(codec) && (reg >= UDA1380_MVOL))
116 if (!snd_soc_component_is_active(component) && (reg >= UDA1380_MVOL))
117 return 0;
118 pr_debug("uda1380: hw write %x val %x\n", reg, value);
119 if (i2c_master_send(uda1380->i2c, data, 3) == 3) {
120 unsigned int val;
121 i2c_master_send(uda1380->i2c, data, 1);
122 i2c_master_recv(uda1380->i2c, data, 2);
123 val = (data[0]<<8) | data[1];
124 if (val != value) {
125 pr_debug("uda1380: READ BACK VAL %x\n",
126 (data[0]<<8) | data[1]);
127 return -EIO;
128 }
129 if (reg >= 0x10)
130 clear_bit(reg - 0x10, &uda1380_cache_dirty);
131 return 0;
132 } else
133 return -EIO;
134}
135
117 return 0;
118 pr_debug("uda1380: hw write %x val %x\n", reg, value);
119 if (i2c_master_send(uda1380->i2c, data, 3) == 3) {
120 unsigned int val;
121 i2c_master_send(uda1380->i2c, data, 1);
122 i2c_master_recv(uda1380->i2c, data, 2);
123 val = (data[0]<<8) | data[1];
124 if (val != value) {
125 pr_debug("uda1380: READ BACK VAL %x\n",
126 (data[0]<<8) | data[1]);
127 return -EIO;
128 }
129 if (reg >= 0x10)
130 clear_bit(reg - 0x10, &uda1380_cache_dirty);
131 return 0;
132 } else
133 return -EIO;
134}
135
136static void uda1380_sync_cache(struct snd_soc_codec *codec)
136static void uda1380_sync_cache(struct snd_soc_component *component)
137{
137{
138 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
138 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
139 int reg;
140 u8 data[3];
141 u16 *cache = uda1380->reg_cache;
142
143 /* Sync reg_cache with the hardware */
144 for (reg = 0; reg < UDA1380_MVOL; reg++) {
145 data[0] = reg;
146 data[1] = (cache[reg] & 0xff00) >> 8;
147 data[2] = cache[reg] & 0x00ff;
148 if (i2c_master_send(uda1380->i2c, data, 3) != 3)
139 int reg;
140 u8 data[3];
141 u16 *cache = uda1380->reg_cache;
142
143 /* Sync reg_cache with the hardware */
144 for (reg = 0; reg < UDA1380_MVOL; reg++) {
145 data[0] = reg;
146 data[1] = (cache[reg] & 0xff00) >> 8;
147 data[2] = cache[reg] & 0x00ff;
148 if (i2c_master_send(uda1380->i2c, data, 3) != 3)
149 dev_err(codec->dev, "%s: write to reg 0x%x failed\n",
149 dev_err(component->dev, "%s: write to reg 0x%x failed\n",
150 __func__, reg);
151 }
152}
153
150 __func__, reg);
151 }
152}
153
154static int uda1380_reset(struct snd_soc_codec *codec)
154static int uda1380_reset(struct snd_soc_component *component)
155{
155{
156 struct uda1380_platform_data *pdata = codec->dev->platform_data;
157 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
156 struct uda1380_platform_data *pdata = component->dev->platform_data;
157 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
158
159 if (gpio_is_valid(pdata->gpio_reset)) {
160 gpio_set_value(pdata->gpio_reset, 1);
161 mdelay(1);
162 gpio_set_value(pdata->gpio_reset, 0);
163 } else {
164 u8 data[3];
165
166 data[0] = UDA1380_RESET;
167 data[1] = 0;
168 data[2] = 0;
169
170 if (i2c_master_send(uda1380->i2c, data, 3) != 3) {
158
159 if (gpio_is_valid(pdata->gpio_reset)) {
160 gpio_set_value(pdata->gpio_reset, 1);
161 mdelay(1);
162 gpio_set_value(pdata->gpio_reset, 0);
163 } else {
164 u8 data[3];
165
166 data[0] = UDA1380_RESET;
167 data[1] = 0;
168 data[2] = 0;
169
170 if (i2c_master_send(uda1380->i2c, data, 3) != 3) {
171 dev_err(codec->dev, "%s: failed\n", __func__);
171 dev_err(component->dev, "%s: failed\n", __func__);
172 return -EIO;
173 }
174 }
175
176 return 0;
177}
178
179static void uda1380_flush_work(struct work_struct *work)
180{
181 struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
172 return -EIO;
173 }
174 }
175
176 return 0;
177}
178
179static void uda1380_flush_work(struct work_struct *work)
180{
181 struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
182 struct snd_soc_codec *uda1380_codec = uda1380->codec;
182 struct snd_soc_component *uda1380_component = uda1380->component;
183 int bit, reg;
184
185 for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
186 reg = 0x10 + bit;
187 pr_debug("uda1380: flush reg %x val %x:\n", reg,
183 int bit, reg;
184
185 for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
186 reg = 0x10 + bit;
187 pr_debug("uda1380: flush reg %x val %x:\n", reg,
188 uda1380_read_reg_cache(uda1380_codec, reg));
189 uda1380_write(uda1380_codec, reg,
190 uda1380_read_reg_cache(uda1380_codec, reg));
188 uda1380_read_reg_cache(uda1380_component, reg));
189 uda1380_write(uda1380_component, reg,
190 uda1380_read_reg_cache(uda1380_component, reg));
191 clear_bit(bit, &uda1380_cache_dirty);
192 }
193
194}
195
196/* declarations of ALSA reg_elem_REAL controls */
197static const char *uda1380_deemp[] = {
198 "None",

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415 {"Mic LNA", NULL, "VINM"},
416 {"Left PGA", NULL, "VINL"},
417 {"Right PGA", NULL, "VINR"},
418};
419
420static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
421 unsigned int fmt)
422{
191 clear_bit(bit, &uda1380_cache_dirty);
192 }
193
194}
195
196/* declarations of ALSA reg_elem_REAL controls */
197static const char *uda1380_deemp[] = {
198 "None",

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415 {"Mic LNA", NULL, "VINM"},
416 {"Left PGA", NULL, "VINL"},
417 {"Right PGA", NULL, "VINR"},
418};
419
420static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
421 unsigned int fmt)
422{
423 struct snd_soc_codec *codec = codec_dai->codec;
423 struct snd_soc_component *component = codec_dai->component;
424 int iface;
425
426 /* set up DAI based upon fmt */
424 int iface;
425
426 /* set up DAI based upon fmt */
427 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
427 iface = uda1380_read_reg_cache(component, UDA1380_IFACE);
428 iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
429
430 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
431 case SND_SOC_DAIFMT_I2S:
432 iface |= R01_SFORI_I2S | R01_SFORO_I2S;
433 break;
434 case SND_SOC_DAIFMT_LSB:
435 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
436 break;
437 case SND_SOC_DAIFMT_MSB:
438 iface |= R01_SFORI_MSB | R01_SFORO_MSB;
439 }
440
441 /* DATAI is slave only, so in single-link mode, this has to be slave */
442 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
443 return -EINVAL;
444
428 iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
429
430 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
431 case SND_SOC_DAIFMT_I2S:
432 iface |= R01_SFORI_I2S | R01_SFORO_I2S;
433 break;
434 case SND_SOC_DAIFMT_LSB:
435 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
436 break;
437 case SND_SOC_DAIFMT_MSB:
438 iface |= R01_SFORI_MSB | R01_SFORO_MSB;
439 }
440
441 /* DATAI is slave only, so in single-link mode, this has to be slave */
442 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
443 return -EINVAL;
444
445 uda1380_write_reg_cache(codec, UDA1380_IFACE, iface);
445 uda1380_write_reg_cache(component, UDA1380_IFACE, iface);
446
447 return 0;
448}
449
450static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
451 unsigned int fmt)
452{
446
447 return 0;
448}
449
450static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
451 unsigned int fmt)
452{
453 struct snd_soc_codec *codec = codec_dai->codec;
453 struct snd_soc_component *component = codec_dai->component;
454 int iface;
455
456 /* set up DAI based upon fmt */
454 int iface;
455
456 /* set up DAI based upon fmt */
457 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
457 iface = uda1380_read_reg_cache(component, UDA1380_IFACE);
458 iface &= ~R01_SFORI_MASK;
459
460 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
461 case SND_SOC_DAIFMT_I2S:
462 iface |= R01_SFORI_I2S;
463 break;
464 case SND_SOC_DAIFMT_LSB:
465 iface |= R01_SFORI_LSB16;
466 break;
467 case SND_SOC_DAIFMT_MSB:
468 iface |= R01_SFORI_MSB;
469 }
470
471 /* DATAI is slave only, so this has to be slave */
472 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
473 return -EINVAL;
474
458 iface &= ~R01_SFORI_MASK;
459
460 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
461 case SND_SOC_DAIFMT_I2S:
462 iface |= R01_SFORI_I2S;
463 break;
464 case SND_SOC_DAIFMT_LSB:
465 iface |= R01_SFORI_LSB16;
466 break;
467 case SND_SOC_DAIFMT_MSB:
468 iface |= R01_SFORI_MSB;
469 }
470
471 /* DATAI is slave only, so this has to be slave */
472 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
473 return -EINVAL;
474
475 uda1380_write(codec, UDA1380_IFACE, iface);
475 uda1380_write(component, UDA1380_IFACE, iface);
476
477 return 0;
478}
479
480static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
481 unsigned int fmt)
482{
476
477 return 0;
478}
479
480static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
481 unsigned int fmt)
482{
483 struct snd_soc_codec *codec = codec_dai->codec;
483 struct snd_soc_component *component = codec_dai->component;
484 int iface;
485
486 /* set up DAI based upon fmt */
484 int iface;
485
486 /* set up DAI based upon fmt */
487 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
487 iface = uda1380_read_reg_cache(component, UDA1380_IFACE);
488 iface &= ~(R01_SIM | R01_SFORO_MASK);
489
490 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
491 case SND_SOC_DAIFMT_I2S:
492 iface |= R01_SFORO_I2S;
493 break;
494 case SND_SOC_DAIFMT_LSB:
495 iface |= R01_SFORO_LSB16;
496 break;
497 case SND_SOC_DAIFMT_MSB:
498 iface |= R01_SFORO_MSB;
499 }
500
501 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
502 iface |= R01_SIM;
503
488 iface &= ~(R01_SIM | R01_SFORO_MASK);
489
490 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
491 case SND_SOC_DAIFMT_I2S:
492 iface |= R01_SFORO_I2S;
493 break;
494 case SND_SOC_DAIFMT_LSB:
495 iface |= R01_SFORO_LSB16;
496 break;
497 case SND_SOC_DAIFMT_MSB:
498 iface |= R01_SFORO_MSB;
499 }
500
501 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
502 iface |= R01_SIM;
503
504 uda1380_write(codec, UDA1380_IFACE, iface);
504 uda1380_write(component, UDA1380_IFACE, iface);
505
506 return 0;
507}
508
509static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
510 struct snd_soc_dai *dai)
511{
505
506 return 0;
507}
508
509static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
510 struct snd_soc_dai *dai)
511{
512 struct snd_soc_codec *codec = dai->codec;
513 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
514 int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
512 struct snd_soc_component *component = dai->component;
513 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
514 int mixer = uda1380_read_reg_cache(component, UDA1380_MIXER);
515
516 switch (cmd) {
517 case SNDRV_PCM_TRIGGER_START:
518 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
515
516 switch (cmd) {
517 case SNDRV_PCM_TRIGGER_START:
518 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
519 uda1380_write_reg_cache(codec, UDA1380_MIXER,
519 uda1380_write_reg_cache(component, UDA1380_MIXER,
520 mixer & ~R14_SILENCE);
521 schedule_work(&uda1380->work);
522 break;
523 case SNDRV_PCM_TRIGGER_STOP:
524 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
520 mixer & ~R14_SILENCE);
521 schedule_work(&uda1380->work);
522 break;
523 case SNDRV_PCM_TRIGGER_STOP:
524 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
525 uda1380_write_reg_cache(codec, UDA1380_MIXER,
525 uda1380_write_reg_cache(component, UDA1380_MIXER,
526 mixer | R14_SILENCE);
527 schedule_work(&uda1380->work);
528 break;
529 }
530 return 0;
531}
532
533static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
534 struct snd_pcm_hw_params *params,
535 struct snd_soc_dai *dai)
536{
526 mixer | R14_SILENCE);
527 schedule_work(&uda1380->work);
528 break;
529 }
530 return 0;
531}
532
533static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
534 struct snd_pcm_hw_params *params,
535 struct snd_soc_dai *dai)
536{
537 struct snd_soc_codec *codec = dai->codec;
538 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
537 struct snd_soc_component *component = dai->component;
538 u16 clk = uda1380_read_reg_cache(component, UDA1380_CLK);
539
540 /* set WSPLL power and divider if running from this clock */
541 if (clk & R00_DAC_CLK) {
542 int rate = params_rate(params);
539
540 /* set WSPLL power and divider if running from this clock */
541 if (clk & R00_DAC_CLK) {
542 int rate = params_rate(params);
543 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
543 u16 pm = uda1380_read_reg_cache(component, UDA1380_PM);
544 clk &= ~0x3; /* clear SEL_LOOP_DIV */
545 switch (rate) {
546 case 6250 ... 12500:
547 clk |= 0x0;
548 break;
549 case 12501 ... 25000:
550 clk |= 0x1;
551 break;
552 case 25001 ... 50000:
553 clk |= 0x2;
554 break;
555 case 50001 ... 100000:
556 clk |= 0x3;
557 break;
558 }
544 clk &= ~0x3; /* clear SEL_LOOP_DIV */
545 switch (rate) {
546 case 6250 ... 12500:
547 clk |= 0x0;
548 break;
549 case 12501 ... 25000:
550 clk |= 0x1;
551 break;
552 case 25001 ... 50000:
553 clk |= 0x2;
554 break;
555 case 50001 ... 100000:
556 clk |= 0x3;
557 break;
558 }
559 uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
559 uda1380_write(component, UDA1380_PM, R02_PON_PLL | pm);
560 }
561
562 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
563 clk |= R00_EN_DAC | R00_EN_INT;
564 else
565 clk |= R00_EN_ADC | R00_EN_DEC;
566
560 }
561
562 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
563 clk |= R00_EN_DAC | R00_EN_INT;
564 else
565 clk |= R00_EN_ADC | R00_EN_DEC;
566
567 uda1380_write(codec, UDA1380_CLK, clk);
567 uda1380_write(component, UDA1380_CLK, clk);
568 return 0;
569}
570
571static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
572 struct snd_soc_dai *dai)
573{
568 return 0;
569}
570
571static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
572 struct snd_soc_dai *dai)
573{
574 struct snd_soc_codec *codec = dai->codec;
575 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
574 struct snd_soc_component *component = dai->component;
575 u16 clk = uda1380_read_reg_cache(component, UDA1380_CLK);
576
577 /* shut down WSPLL power if running from this clock */
578 if (clk & R00_DAC_CLK) {
576
577 /* shut down WSPLL power if running from this clock */
578 if (clk & R00_DAC_CLK) {
579 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
580 uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
579 u16 pm = uda1380_read_reg_cache(component, UDA1380_PM);
580 uda1380_write(component, UDA1380_PM, ~R02_PON_PLL & pm);
581 }
582
583 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
584 clk &= ~(R00_EN_DAC | R00_EN_INT);
585 else
586 clk &= ~(R00_EN_ADC | R00_EN_DEC);
587
581 }
582
583 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
584 clk &= ~(R00_EN_DAC | R00_EN_INT);
585 else
586 clk &= ~(R00_EN_ADC | R00_EN_DEC);
587
588 uda1380_write(codec, UDA1380_CLK, clk);
588 uda1380_write(component, UDA1380_CLK, clk);
589}
590
589}
590
591static int uda1380_set_bias_level(struct snd_soc_codec *codec,
591static int uda1380_set_bias_level(struct snd_soc_component *component,
592 enum snd_soc_bias_level level)
593{
592 enum snd_soc_bias_level level)
593{
594 int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
594 int pm = uda1380_read_reg_cache(component, UDA1380_PM);
595 int reg;
595 int reg;
596 struct uda1380_platform_data *pdata = codec->dev->platform_data;
596 struct uda1380_platform_data *pdata = component->dev->platform_data;
597
598 switch (level) {
599 case SND_SOC_BIAS_ON:
600 case SND_SOC_BIAS_PREPARE:
601 /* ADC, DAC on */
597
598 switch (level) {
599 case SND_SOC_BIAS_ON:
600 case SND_SOC_BIAS_PREPARE:
601 /* ADC, DAC on */
602 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
602 uda1380_write(component, UDA1380_PM, R02_PON_BIAS | pm);
603 break;
604 case SND_SOC_BIAS_STANDBY:
603 break;
604 case SND_SOC_BIAS_STANDBY:
605 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
605 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
606 if (gpio_is_valid(pdata->gpio_power)) {
607 gpio_set_value(pdata->gpio_power, 1);
608 mdelay(1);
606 if (gpio_is_valid(pdata->gpio_power)) {
607 gpio_set_value(pdata->gpio_power, 1);
608 mdelay(1);
609 uda1380_reset(codec);
609 uda1380_reset(component);
610 }
611
610 }
611
612 uda1380_sync_cache(codec);
612 uda1380_sync_cache(component);
613 }
613 }
614 uda1380_write(codec, UDA1380_PM, 0x0);
614 uda1380_write(component, UDA1380_PM, 0x0);
615 break;
616 case SND_SOC_BIAS_OFF:
617 if (!gpio_is_valid(pdata->gpio_power))
618 break;
619
620 gpio_set_value(pdata->gpio_power, 0);
621
622 /* Mark mixer regs cache dirty to sync them with

--- 66 unchanged lines hidden (view full) ---

689 .channels_max = 2,
690 .rates = UDA1380_RATES,
691 .formats = SNDRV_PCM_FMTBIT_S16_LE,
692 },
693 .ops = &uda1380_dai_ops_capture,
694},
695};
696
615 break;
616 case SND_SOC_BIAS_OFF:
617 if (!gpio_is_valid(pdata->gpio_power))
618 break;
619
620 gpio_set_value(pdata->gpio_power, 0);
621
622 /* Mark mixer regs cache dirty to sync them with

--- 66 unchanged lines hidden (view full) ---

689 .channels_max = 2,
690 .rates = UDA1380_RATES,
691 .formats = SNDRV_PCM_FMTBIT_S16_LE,
692 },
693 .ops = &uda1380_dai_ops_capture,
694},
695};
696
697static int uda1380_probe(struct snd_soc_codec *codec)
697static int uda1380_probe(struct snd_soc_component *component)
698{
698{
699 struct uda1380_platform_data *pdata =codec->dev->platform_data;
700 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
699 struct uda1380_platform_data *pdata =component->dev->platform_data;
700 struct uda1380_priv *uda1380 = snd_soc_component_get_drvdata(component);
701 int ret;
702
701 int ret;
702
703 uda1380->codec = codec;
703 uda1380->component = component;
704
705 if (!gpio_is_valid(pdata->gpio_power)) {
704
705 if (!gpio_is_valid(pdata->gpio_power)) {
706 ret = uda1380_reset(codec);
706 ret = uda1380_reset(component);
707 if (ret)
708 return ret;
709 }
710
711 INIT_WORK(&uda1380->work, uda1380_flush_work);
712
713 /* set clock input */
714 switch (pdata->dac_clk) {
715 case UDA1380_DAC_CLK_SYSCLK:
707 if (ret)
708 return ret;
709 }
710
711 INIT_WORK(&uda1380->work, uda1380_flush_work);
712
713 /* set clock input */
714 switch (pdata->dac_clk) {
715 case UDA1380_DAC_CLK_SYSCLK:
716 uda1380_write_reg_cache(codec, UDA1380_CLK, 0);
716 uda1380_write_reg_cache(component, UDA1380_CLK, 0);
717 break;
718 case UDA1380_DAC_CLK_WSPLL:
717 break;
718 case UDA1380_DAC_CLK_WSPLL:
719 uda1380_write_reg_cache(codec, UDA1380_CLK,
719 uda1380_write_reg_cache(component, UDA1380_CLK,
720 R00_DAC_CLK);
721 break;
722 }
723
724 return 0;
725}
726
720 R00_DAC_CLK);
721 break;
722 }
723
724 return 0;
725}
726
727static const struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
728 .probe = uda1380_probe,
729 .set_bias_level = uda1380_set_bias_level,
730 .suspend_bias_off = true,
731
732 .component_driver = {
733 .controls = uda1380_snd_controls,
734 .num_controls = ARRAY_SIZE(uda1380_snd_controls),
735 .dapm_widgets = uda1380_dapm_widgets,
736 .num_dapm_widgets = ARRAY_SIZE(uda1380_dapm_widgets),
737 .dapm_routes = uda1380_dapm_routes,
738 .num_dapm_routes = ARRAY_SIZE(uda1380_dapm_routes),
739 },
727static const struct snd_soc_component_driver soc_component_dev_uda1380 = {
728 .probe = uda1380_probe,
729 .read = uda1380_read_reg_cache,
730 .write = uda1380_write,
731 .set_bias_level = uda1380_set_bias_level,
732 .controls = uda1380_snd_controls,
733 .num_controls = ARRAY_SIZE(uda1380_snd_controls),
734 .dapm_widgets = uda1380_dapm_widgets,
735 .num_dapm_widgets = ARRAY_SIZE(uda1380_dapm_widgets),
736 .dapm_routes = uda1380_dapm_routes,
737 .num_dapm_routes = ARRAY_SIZE(uda1380_dapm_routes),
738 .suspend_bias_off = 1,
739 .idle_bias_on = 1,
740 .use_pmdown_time = 1,
741 .endianness = 1,
742 .non_legacy_dai_naming = 1,
740};
741
742static int uda1380_i2c_probe(struct i2c_client *i2c,
743 const struct i2c_device_id *id)
744{
745 struct uda1380_platform_data *pdata = i2c->dev.platform_data;
746 struct uda1380_priv *uda1380;
747 int ret;

--- 25 unchanged lines hidden (view full) ---

773 ARRAY_SIZE(uda1380_reg) * sizeof(u16),
774 GFP_KERNEL);
775 if (!uda1380->reg_cache)
776 return -ENOMEM;
777
778 i2c_set_clientdata(i2c, uda1380);
779 uda1380->i2c = i2c;
780
743};
744
745static int uda1380_i2c_probe(struct i2c_client *i2c,
746 const struct i2c_device_id *id)
747{
748 struct uda1380_platform_data *pdata = i2c->dev.platform_data;
749 struct uda1380_priv *uda1380;
750 int ret;

--- 25 unchanged lines hidden (view full) ---

776 ARRAY_SIZE(uda1380_reg) * sizeof(u16),
777 GFP_KERNEL);
778 if (!uda1380->reg_cache)
779 return -ENOMEM;
780
781 i2c_set_clientdata(i2c, uda1380);
782 uda1380->i2c = i2c;
783
781 ret = snd_soc_register_codec(&i2c->dev,
782 &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
784 ret = devm_snd_soc_register_component(&i2c->dev,
785 &soc_component_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
783 return ret;
784}
785
786 return ret;
787}
788
786static int uda1380_i2c_remove(struct i2c_client *i2c)
787{
788 snd_soc_unregister_codec(&i2c->dev);
789 return 0;
790}
791
792static const struct i2c_device_id uda1380_i2c_id[] = {
793 { "uda1380", 0 },
794 { }
795};
796MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
797
798static const struct of_device_id uda1380_of_match[] = {
799 { .compatible = "nxp,uda1380", },
800 { }
801};
802MODULE_DEVICE_TABLE(of, uda1380_of_match);
803
804static struct i2c_driver uda1380_i2c_driver = {
805 .driver = {
806 .name = "uda1380-codec",
807 .of_match_table = uda1380_of_match,
808 },
809 .probe = uda1380_i2c_probe,
789static const struct i2c_device_id uda1380_i2c_id[] = {
790 { "uda1380", 0 },
791 { }
792};
793MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
794
795static const struct of_device_id uda1380_of_match[] = {
796 { .compatible = "nxp,uda1380", },
797 { }
798};
799MODULE_DEVICE_TABLE(of, uda1380_of_match);
800
801static struct i2c_driver uda1380_i2c_driver = {
802 .driver = {
803 .name = "uda1380-codec",
804 .of_match_table = uda1380_of_match,
805 },
806 .probe = uda1380_i2c_probe,
810 .remove = uda1380_i2c_remove,
811 .id_table = uda1380_i2c_id,
812};
813
814module_i2c_driver(uda1380_i2c_driver);
815
816MODULE_AUTHOR("Giorgio Padrin");
817MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
818MODULE_LICENSE("GPL");
807 .id_table = uda1380_i2c_id,
808};
809
810module_i2c_driver(uda1380_i2c_driver);
811
812MODULE_AUTHOR("Giorgio Padrin");
813MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
814MODULE_LICENSE("GPL");