uda1380.c (a3c7729e6c5d41bbeb3e13befbcf8e4ef76e55dc) uda1380.c (ef9e5e5c31cb2c6254760611289ac13e4e41b964)
1/*
2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>

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20#include <linux/init.h>
21#include <linux/types.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/errno.h>
25#include <linux/ioctl.h>
26#include <linux/delay.h>
27#include <linux/i2c.h>
1/*
2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>

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20#include <linux/init.h>
21#include <linux/types.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/errno.h>
25#include <linux/ioctl.h>
26#include <linux/delay.h>
27#include <linux/i2c.h>
28#include <linux/workqueue.h>
28#include <sound/core.h>
29#include <sound/control.h>
30#include <sound/initval.h>
31#include <sound/info.h>
32#include <sound/soc.h>
33#include <sound/soc-dapm.h>
34#include <sound/tlv.h>
35
36#include "uda1380.h"
37
29#include <sound/core.h>
30#include <sound/control.h>
31#include <sound/initval.h>
32#include <sound/info.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/tlv.h>
36
37#include "uda1380.h"
38
39static struct work_struct uda1380_work;
40static struct snd_soc_codec *uda1380_codec;
41
38/*
39 * uda1380 register cache
40 */
41static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
42 0x0502, 0x0000, 0x0000, 0x3f3f,
43 0x0202, 0x0000, 0x0000, 0x0000,
44 0x0000, 0x0000, 0x0000, 0x0000,
45 0x0000, 0x0000, 0x0000, 0x0000,
46 0x0000, 0xff00, 0x0000, 0x4800,
47 0x0000, 0x0000, 0x0000, 0x0000,
48 0x0000, 0x0000, 0x0000, 0x0000,
49 0x0000, 0x0000, 0x0000, 0x0000,
50 0x0000, 0x8000, 0x0002, 0x0000,
51};
52
42/*
43 * uda1380 register cache
44 */
45static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
46 0x0502, 0x0000, 0x0000, 0x3f3f,
47 0x0202, 0x0000, 0x0000, 0x0000,
48 0x0000, 0x0000, 0x0000, 0x0000,
49 0x0000, 0x0000, 0x0000, 0x0000,
50 0x0000, 0xff00, 0x0000, 0x4800,
51 0x0000, 0x0000, 0x0000, 0x0000,
52 0x0000, 0x0000, 0x0000, 0x0000,
53 0x0000, 0x0000, 0x0000, 0x0000,
54 0x0000, 0x8000, 0x0002, 0x0000,
55};
56
57static unsigned long uda1380_cache_dirty;
58
53/*
54 * read uda1380 register cache
55 */
56static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
57 unsigned int reg)
58{
59 u16 *cache = codec->reg_cache;
60 if (reg == UDA1380_RESET)

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66
67/*
68 * write uda1380 register cache
69 */
70static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
71 u16 reg, unsigned int value)
72{
73 u16 *cache = codec->reg_cache;
59/*
60 * read uda1380 register cache
61 */
62static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
63 unsigned int reg)
64{
65 u16 *cache = codec->reg_cache;
66 if (reg == UDA1380_RESET)

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72
73/*
74 * write uda1380 register cache
75 */
76static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
77 u16 reg, unsigned int value)
78{
79 u16 *cache = codec->reg_cache;
80
74 if (reg >= UDA1380_CACHEREGNUM)
75 return;
81 if (reg >= UDA1380_CACHEREGNUM)
82 return;
83 if ((reg >= 0x10) && (cache[reg] != value))
84 set_bit(reg - 0x10, &uda1380_cache_dirty);
76 cache[reg] = value;
77}
78
79/*
80 * write to the UDA1380 register space
81 */
82static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
83 unsigned int value)

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106 i2c_master_send(codec->control_data, data, 1);
107 i2c_master_recv(codec->control_data, data, 2);
108 val = (data[0]<<8) | data[1];
109 if (val != value) {
110 pr_debug("uda1380: READ BACK VAL %x\n",
111 (data[0]<<8) | data[1]);
112 return -EIO;
113 }
85 cache[reg] = value;
86}
87
88/*
89 * write to the UDA1380 register space
90 */
91static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
92 unsigned int value)

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115 i2c_master_send(codec->control_data, data, 1);
116 i2c_master_recv(codec->control_data, data, 2);
117 val = (data[0]<<8) | data[1];
118 if (val != value) {
119 pr_debug("uda1380: READ BACK VAL %x\n",
120 (data[0]<<8) | data[1]);
121 return -EIO;
122 }
123 if (reg >= 0x10)
124 clear_bit(reg - 0x10, &uda1380_cache_dirty);
114 return 0;
115 } else
116 return -EIO;
117}
118
119#define uda1380_reset(c) uda1380_write(c, UDA1380_RESET, 0)
120
125 return 0;
126 } else
127 return -EIO;
128}
129
130#define uda1380_reset(c) uda1380_write(c, UDA1380_RESET, 0)
131
132static void uda1380_flush_work(struct work_struct *work)
133{
134 int bit, reg;
135
136 for_each_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
137 reg = 0x10 + bit;
138 pr_debug("uda1380: flush reg %x val %x:\n", reg,
139 uda1380_read_reg_cache(uda1380_codec, reg));
140 uda1380_write(uda1380_codec, reg,
141 uda1380_read_reg_cache(uda1380_codec, reg));
142 clear_bit(bit, &uda1380_cache_dirty);
143 }
144}
145
121/* declarations of ALSA reg_elem_REAL controls */
122static const char *uda1380_deemp[] = {
123 "None",
124 "32kHz",
125 "44.1kHz",
126 "48kHz",
127 "96kHz",
128};

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247/**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */
248 SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */
249 SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */
250 SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */
251 SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */
252 SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
253 SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
254 SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
146/* declarations of ALSA reg_elem_REAL controls */
147static const char *uda1380_deemp[] = {
148 "None",
149 "32kHz",
150 "44.1kHz",
151 "48kHz",
152 "96kHz",
153};

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272/**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */
273 SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */
274 SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */
275 SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */
276 SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */
277 SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
278 SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
279 SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
255 SOC_SINGLE("Silence Switch", UDA1380_MIXER, 7, 1, 0), /* SILENCE, force DAC output to silence */
256 SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
257 SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
258 SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
259 SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */
260/**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */
261 SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
262 SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
263 SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */

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433 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
434 iface |= R01_SIM;
435
436 uda1380_write(codec, UDA1380_IFACE, iface);
437
438 return 0;
439}
440
280 SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
281 SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
282 SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
283 SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */
284/**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */
285 SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
286 SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
287 SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */

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457 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
458 iface |= R01_SIM;
459
460 uda1380_write(codec, UDA1380_IFACE, iface);
461
462 return 0;
463}
464
441/*
442 * Flush reg cache
443 * We can only write the interpolator and decimator registers
444 * when the DAI is being clocked by the CPU DAI. It's up to the
445 * machine and cpu DAI driver to do this before we are called.
446 */
447static int uda1380_pcm_prepare(struct snd_pcm_substream *substream,
448 struct snd_soc_dai *dai)
465static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
466 struct snd_soc_dai *dai)
449{
450 struct snd_soc_pcm_runtime *rtd = substream->private_data;
451 struct snd_soc_device *socdev = rtd->socdev;
452 struct snd_soc_codec *codec = socdev->card->codec;
467{
468 struct snd_soc_pcm_runtime *rtd = substream->private_data;
469 struct snd_soc_device *socdev = rtd->socdev;
470 struct snd_soc_codec *codec = socdev->card->codec;
453 int reg, reg_start, reg_end, clk;
471 int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
454
472
455 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
456 reg_start = UDA1380_MVOL;
457 reg_end = UDA1380_MIXER;
458 } else {
459 reg_start = UDA1380_DEC;
460 reg_end = UDA1380_AGC;
473 switch (cmd) {
474 case SNDRV_PCM_TRIGGER_START:
475 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
476 uda1380_write_reg_cache(codec, UDA1380_MIXER,
477 mixer & ~R14_SILENCE);
478 schedule_work(&uda1380_work);
479 break;
480 case SNDRV_PCM_TRIGGER_STOP:
481 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
482 uda1380_write_reg_cache(codec, UDA1380_MIXER,
483 mixer | R14_SILENCE);
484 schedule_work(&uda1380_work);
485 break;
461 }
486 }
462
463 /* FIXME disable DAC_CLK */
464 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
465 uda1380_write(codec, UDA1380_CLK, clk & ~R00_DAC_CLK);
466
467 for (reg = reg_start; reg <= reg_end; reg++) {
468 pr_debug("uda1380: flush reg %x val %x:", reg,
469 uda1380_read_reg_cache(codec, reg));
470 uda1380_write(codec, reg, uda1380_read_reg_cache(codec, reg));
471 }
472
473 /* FIXME restore DAC_CLK */
474 uda1380_write(codec, UDA1380_CLK, clk);
475
476 return 0;
477}
478
479static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
480 struct snd_pcm_hw_params *params,
481 struct snd_soc_dai *dai)
482{
483 struct snd_soc_pcm_runtime *rtd = substream->private_data;

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533 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
534 clk &= ~(R00_EN_DAC | R00_EN_INT);
535 else
536 clk &= ~(R00_EN_ADC | R00_EN_DEC);
537
538 uda1380_write(codec, UDA1380_CLK, clk);
539}
540
487 return 0;
488}
489
490static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
491 struct snd_pcm_hw_params *params,
492 struct snd_soc_dai *dai)
493{
494 struct snd_soc_pcm_runtime *rtd = substream->private_data;

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544 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
545 clk &= ~(R00_EN_DAC | R00_EN_INT);
546 else
547 clk &= ~(R00_EN_ADC | R00_EN_DEC);
548
549 uda1380_write(codec, UDA1380_CLK, clk);
550}
551
541static int uda1380_mute(struct snd_soc_dai *codec_dai, int mute)
542{
543 struct snd_soc_codec *codec = codec_dai->codec;
544 u16 mute_reg = uda1380_read_reg_cache(codec, UDA1380_DEEMP) & ~R13_MTM;
545
546 /* FIXME: mute(codec,0) is called when the magician clock is already
547 * set to WSPLL, but for some unknown reason writing to interpolator
548 * registers works only when clocked by SYSCLK */
549 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
550 uda1380_write(codec, UDA1380_CLK, ~R00_DAC_CLK & clk);
551 if (mute)
552 uda1380_write(codec, UDA1380_DEEMP, mute_reg | R13_MTM);
553 else
554 uda1380_write(codec, UDA1380_DEEMP, mute_reg);
555 uda1380_write(codec, UDA1380_CLK, clk);
556 return 0;
557}
558
559static int uda1380_set_bias_level(struct snd_soc_codec *codec,
560 enum snd_soc_bias_level level)
561{
562 int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
563
564 switch (level) {
565 case SND_SOC_BIAS_ON:
566 case SND_SOC_BIAS_PREPARE:

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592 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
593 .capture = {
594 .stream_name = "Capture",
595 .channels_min = 1,
596 .channels_max = 2,
597 .rates = UDA1380_RATES,
598 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
599 .ops = {
552static int uda1380_set_bias_level(struct snd_soc_codec *codec,
553 enum snd_soc_bias_level level)
554{
555 int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
556
557 switch (level) {
558 case SND_SOC_BIAS_ON:
559 case SND_SOC_BIAS_PREPARE:

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585 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
586 .capture = {
587 .stream_name = "Capture",
588 .channels_min = 1,
589 .channels_max = 2,
590 .rates = UDA1380_RATES,
591 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
592 .ops = {
593 .trigger = uda1380_trigger,
600 .hw_params = uda1380_pcm_hw_params,
601 .shutdown = uda1380_pcm_shutdown,
594 .hw_params = uda1380_pcm_hw_params,
595 .shutdown = uda1380_pcm_shutdown,
602 .prepare = uda1380_pcm_prepare,
603 .digital_mute = uda1380_mute,
604 .set_fmt = uda1380_set_dai_fmt_both,
605 },
606},
607{ /* playback only - dual interface */
608 .name = "UDA1380",
609 .playback = {
610 .stream_name = "Playback",
611 .channels_min = 1,
612 .channels_max = 2,
613 .rates = UDA1380_RATES,
614 .formats = SNDRV_PCM_FMTBIT_S16_LE,
615 },
616 .ops = {
596 .set_fmt = uda1380_set_dai_fmt_both,
597 },
598},
599{ /* playback only - dual interface */
600 .name = "UDA1380",
601 .playback = {
602 .stream_name = "Playback",
603 .channels_min = 1,
604 .channels_max = 2,
605 .rates = UDA1380_RATES,
606 .formats = SNDRV_PCM_FMTBIT_S16_LE,
607 },
608 .ops = {
609 .trigger = uda1380_trigger,
617 .hw_params = uda1380_pcm_hw_params,
618 .shutdown = uda1380_pcm_shutdown,
610 .hw_params = uda1380_pcm_hw_params,
611 .shutdown = uda1380_pcm_shutdown,
619 .prepare = uda1380_pcm_prepare,
620 .digital_mute = uda1380_mute,
621 .set_fmt = uda1380_set_dai_fmt_playback,
622 },
623},
624{ /* capture only - dual interface*/
625 .name = "UDA1380",
626 .capture = {
627 .stream_name = "Capture",
628 .channels_min = 1,
629 .channels_max = 2,
630 .rates = UDA1380_RATES,
631 .formats = SNDRV_PCM_FMTBIT_S16_LE,
632 },
633 .ops = {
612 .set_fmt = uda1380_set_dai_fmt_playback,
613 },
614},
615{ /* capture only - dual interface*/
616 .name = "UDA1380",
617 .capture = {
618 .stream_name = "Capture",
619 .channels_min = 1,
620 .channels_max = 2,
621 .rates = UDA1380_RATES,
622 .formats = SNDRV_PCM_FMTBIT_S16_LE,
623 },
624 .ops = {
625 .trigger = uda1380_trigger,
634 .hw_params = uda1380_pcm_hw_params,
635 .shutdown = uda1380_pcm_shutdown,
626 .hw_params = uda1380_pcm_hw_params,
627 .shutdown = uda1380_pcm_shutdown,
636 .prepare = uda1380_pcm_prepare,
637 .set_fmt = uda1380_set_dai_fmt_capture,
638 },
639},
640};
641EXPORT_SYMBOL_GPL(uda1380_dai);
642
643static int uda1380_suspend(struct platform_device *pdev, pm_message_t state)
644{

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687 codec->reg_cache = kmemdup(uda1380_reg, sizeof(uda1380_reg),
688 GFP_KERNEL);
689 if (codec->reg_cache == NULL)
690 return -ENOMEM;
691 codec->reg_cache_size = ARRAY_SIZE(uda1380_reg);
692 codec->reg_cache_step = 1;
693 uda1380_reset(codec);
694
628 .set_fmt = uda1380_set_dai_fmt_capture,
629 },
630},
631};
632EXPORT_SYMBOL_GPL(uda1380_dai);
633
634static int uda1380_suspend(struct platform_device *pdev, pm_message_t state)
635{

--- 42 unchanged lines hidden (view full) ---

678 codec->reg_cache = kmemdup(uda1380_reg, sizeof(uda1380_reg),
679 GFP_KERNEL);
680 if (codec->reg_cache == NULL)
681 return -ENOMEM;
682 codec->reg_cache_size = ARRAY_SIZE(uda1380_reg);
683 codec->reg_cache_step = 1;
684 uda1380_reset(codec);
685
686 uda1380_codec = codec;
687 INIT_WORK(&uda1380_work, uda1380_flush_work);
688
695 /* register pcms */
696 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
697 if (ret < 0) {
698 pr_err("uda1380: failed to create pcms\n");
699 goto pcm_err;
700 }
701
702 /* power on device */

--- 192 unchanged lines hidden --- 		689 /* register pcms */
690 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
691 if (ret < 0) {
692 pr_err("uda1380: failed to create pcms\n");
693 goto pcm_err;
694 }
695
696 /* power on device */

--- 192 unchanged lines hidden ---