tlv320aic31xx.c (bdd0c277d9846977ec3f175341d4e7475ed26ef7) tlv320aic31xx.c (5856d8bd308f9467cefa65d04e184a56a3977559)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ALSA SoC TLV320AIC31xx CODEC Driver
4 *
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ALSA SoC TLV320AIC31xx CODEC Driver
4 *
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
6 * Jyri Sarha <jsarha@ti.com>
7 *
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
9 *
10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
11 * high performance codecs which provides a stereo DAC, a mono ADC,
12 * and mono/stereo Class-D speaker driver.
13 */

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872 return -EINVAL;
873 }
874 if (bclk_score != 0) {
875 dev_warn(component->dev, "Can not produce exact bitclock");
876 /* This is fine if using dsp format, but if using i2s
877 there may be trouble. To fix the issue edit the
878 aic31xx_divs table for your mclk and sample
879 rate. Details can be found from:
6 * Jyri Sarha <jsarha@ti.com>
7 *
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
9 *
10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
11 * high performance codecs which provides a stereo DAC, a mono ADC,
12 * and mono/stereo Class-D speaker driver.
13 */

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872 return -EINVAL;
873 }
874 if (bclk_score != 0) {
875 dev_warn(component->dev, "Can not produce exact bitclock");
876 /* This is fine if using dsp format, but if using i2s
877 there may be trouble. To fix the issue edit the
878 aic31xx_divs table for your mclk and sample
879 rate. Details can be found from:
880 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
880 https://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
881 Section: 5.6 CLOCK Generation and PLL
882 */
883 }
884 i = match;
885
886 /* PLL configuration */
887 snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
888 (aic31xx->p_div << 4) | 0x01);

--- 829 unchanged lines hidden --- 		881 Section: 5.6 CLOCK Generation and PLL
882 */
883 }
884 i = match;
885
886 /* PLL configuration */
887 snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
888 (aic31xx->p_div << 4) | 0x01);

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