mt6359.h (cdd38c5f1ce4398ec58fec95904b75824daab7b5) mt6359.h (eef07b9e0925e16457ab9444b56a7f93b541aee3)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Argus Lin <argus.lin@mediatek.com>
5 */
6
7#ifndef _MT6359_H_
8#define _MT6359_H_
9
10/*************Register Bit Define*************/
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 * Author: Argus Lin <argus.lin@mediatek.com>
5 */
6
7#ifndef _MT6359_H_
8#define _MT6359_H_
9
10/*************Register Bit Define*************/
11#define PMIC_ACCDET_IRQ_SHIFT 0
12#define PMIC_ACCDET_EINT0_IRQ_SHIFT 2
13#define PMIC_ACCDET_EINT1_IRQ_SHIFT 3
14#define PMIC_ACCDET_IRQ_CLR_SHIFT 8
15#define PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT 10
16#define PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT 11
17#define PMIC_RG_INT_STATUS_ACCDET_SHIFT 5
18#define PMIC_RG_INT_STATUS_ACCDET_EINT0_SHIFT 6
19#define PMIC_RG_INT_STATUS_ACCDET_EINT1_SHIFT 7
20#define PMIC_RG_EINT0CONFIGACCDET_SHIFT 11
21#define PMIC_RG_EINT1CONFIGACCDET_SHIFT 0
22#define PMIC_ACCDET_EINT0_INVERTER_SW_EN_SHIFT 6
23#define PMIC_ACCDET_EINT1_INVERTER_SW_EN_SHIFT 8
24#define PMIC_RG_MTEST_EN_SHIFT 8
25#define PMIC_RG_MTEST_SEL_SHIFT 9
26#define PMIC_ACCDET_EINT0_M_SW_EN_SHIFT 10
27#define PMIC_ACCDET_EINT1_M_SW_EN_SHIFT 11
28#define PMIC_ACCDET_EINT0_CEN_STABLE_SHIFT 5
29#define PMIC_ACCDET_EINT1_CEN_STABLE_SHIFT 10
30#define PMIC_ACCDET_DA_STABLE_SHIFT 0
31#define PMIC_ACCDET_EINT0_EN_STABLE_SHIFT 1
32#define PMIC_ACCDET_EINT0_CMPEN_STABLE_SHIFT 2
33#define PMIC_ACCDET_EINT1_EN_STABLE_SHIFT 6
34#define PMIC_ACCDET_EINT1_CMPEN_STABLE_SHIFT 7
35#define PMIC_ACCDET_EINT_CTURBO_SEL_SHIFT 7
36#define PMIC_ACCDET_EINT0_CTURBO_SW_SHIFT 7
37#define PMIC_RG_EINTCOMPVTH_SHIFT 4
38#define PMIC_RG_EINT0HIRENB_SHIFT 12
39#define PMIC_RG_EINT0NOHYS_SHIFT 10
40#define PMIC_ACCDET_SW_EN_SHIFT 0
41#define PMIC_ACCDET_EINT0_MEM_IN_SHIFT 6
42#define PMIC_ACCDET_MEM_IN_SHIFT 6
43#define PMIC_ACCDET_EINT_DEBOUNCE0_SHIFT 0
44#define PMIC_ACCDET_EINT_DEBOUNCE1_SHIFT 4
45#define PMIC_ACCDET_EINT_DEBOUNCE2_SHIFT 8
46#define PMIC_ACCDET_EINT_DEBOUNCE3_SHIFT 12
47#define PMIC_RG_ACCDET2AUXSWEN_SHIFT 14
48#define PMIC_AUDACCDETAUXADCSWCTRL_SEL_SHIFT 9
49#define PMIC_AUDACCDETAUXADCSWCTRL_SW_SHIFT 10
50#define PMIC_RG_EINT0CTURBO_SHIFT 5
51#define PMIC_RG_EINT1CTURBO_SHIFT 13
52#define PMIC_ACCDET_EINT_M_PLUG_IN_NUM_SHIFT 12
53#define PMIC_ACCDET_EINT_M_DETECT_EN_SHIFT 12
54#define PMIC_ACCDET_EINT0_SW_EN_SHIFT 2
55#define PMIC_ACCDET_EINT1_SW_EN_SHIFT 4
56#define PMIC_ACCDET_EINT_CMPMOUT_SEL_SHIFT 12
57#define PMIC_ACCDET_EINT_CMPMEN_SEL_SHIFT 6
58#define PMIC_RG_HPLOUTPUTSTBENH_VAUDP32_SHIFT 0
59#define PMIC_RG_HPROUTPUTSTBENH_VAUDP32_SHIFT 4
60#define PMIC_RG_EINT0EN_SHIFT 2
61#define PMIC_RG_EINT1EN_SHIFT 10
62#define PMIC_RG_NCP_PDDIS_EN_SHIFT 0
63#define PMIC_RG_ACCDETSPARE_SHIFT 0
64#define PMIC_RG_ACCDET_RST_SHIFT 1
65#define PMIC_RG_AUDMICBIAS1HVEN_SHIFT 12
66#define PMIC_RG_AUDMICBIAS1VREF_SHIFT 4
67#define PMIC_RG_ANALOGFDEN_SHIFT 12
68#define PMIC_RG_AUDMICBIAS1DCSW1PEN_SHIFT 8
69#define PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT 2
70#define PMIC_ACCDET_SEQ_INIT_SHIFT 1
71#define PMIC_RG_EINTCOMPVTH_MASK 0xf
72#define PMIC_ACCDET_EINT0_MEM_IN_MASK 0x3
73#define PMIC_ACCDET_EINT_DEBOUNCE0_MASK 0xf
74#define PMIC_ACCDET_EINT_DEBOUNCE1_MASK 0xf
75#define PMIC_ACCDET_EINT_DEBOUNCE2_MASK 0xf
76#define PMIC_ACCDET_EINT_DEBOUNCE3_MASK 0xf
77#define PMIC_ACCDET_EINT0_IRQ_SHIFT 2
78#define PMIC_ACCDET_EINT1_IRQ_SHIFT 3
11#define MT6359_TOP0_ID 0x0
12#define MT6359_SMT_CON1 0x32
13#define MT6359_DRV_CON2 0x3c
14#define MT6359_DRV_CON3 0x3e
15#define MT6359_DRV_CON4 0x40
16#define MT6359_TOP_CKPDN_CON0 0x10c
17#define MT6359_TOP_CKPDN_CON0_SET 0x10e
18#define MT6359_TOP_CKPDN_CON0_CLR 0x110
19#define MT6359_AUXADC_RQST0 0x1108
20#define MT6359_AUXADC_CON10 0x11a0
21#define MT6359_AUXADC_ACCDET 0x11ba
22#define MT6359_LDO_VUSB_OP_EN 0x1d0c
23#define MT6359_LDO_VUSB_OP_EN_SET 0x1d0e
24#define MT6359_LDO_VUSB_OP_EN_CLR 0x1d10
25#define MT6359_AUD_TOP_CKPDN_CON0 0x230c
26#define MT6359_AUD_TOP_CKPDN_CON0_SET 0x230e
27#define MT6359_AUD_TOP_CKPDN_CON0_CLR 0x2310
28#define MT6359_AUD_TOP_RST_CON0 0x2320
29#define MT6359_AUD_TOP_RST_CON0_SET 0x2322
30#define MT6359_AUD_TOP_RST_CON0_CLR 0x2324
31#define MT6359_AUD_TOP_INT_CON0 0x2328
32#define MT6359_AUD_TOP_INT_CON0_SET 0x232a
33#define MT6359_AUD_TOP_INT_CON0_CLR 0x232c
34#define MT6359_AUD_TOP_INT_MASK_CON0 0x232e
35#define MT6359_AUD_TOP_INT_MASK_CON0_SET 0x2330
36#define MT6359_AUD_TOP_INT_MASK_CON0_CLR 0x2332
37#define MT6359_AUD_TOP_INT_STATUS0 0x2334
38#define MT6359_AFE_NCP_CFG2 0x24e2
39#define MT6359_AUDENC_DSN_ID 0x2500
40#define MT6359_AUDENC_DSN_REV0 0x2502
41#define MT6359_AUDENC_DSN_DBI 0x2504
42#define MT6359_AUDENC_DSN_FPI 0x2506
43#define MT6359_AUDENC_ANA_CON0 0x2508
44#define MT6359_AUDENC_ANA_CON1 0x250a
45#define MT6359_AUDENC_ANA_CON2 0x250c
46#define MT6359_AUDENC_ANA_CON3 0x250e
47#define MT6359_AUDENC_ANA_CON4 0x2510
48#define MT6359_AUDENC_ANA_CON5 0x2512
49#define MT6359_AUDENC_ANA_CON6 0x2514
50#define MT6359_AUDENC_ANA_CON7 0x2516
51#define MT6359_AUDENC_ANA_CON8 0x2518
52#define MT6359_AUDENC_ANA_CON9 0x251a
53#define MT6359_AUDENC_ANA_CON10 0x251c
54#define MT6359_AUDENC_ANA_CON11 0x251e
55#define MT6359_AUDENC_ANA_CON12 0x2520
56#define MT6359_AUDENC_ANA_CON13 0x2522
57#define MT6359_AUDENC_ANA_CON14 0x2524
58#define MT6359_AUDENC_ANA_CON15 0x2526
59#define MT6359_AUDENC_ANA_CON16 0x2528
60#define MT6359_AUDENC_ANA_CON17 0x252a
61#define MT6359_AUDENC_ANA_CON18 0x252c
62#define MT6359_AUDENC_ANA_CON19 0x252e
63#define MT6359_AUDENC_ANA_CON20 0x2530
64#define MT6359_AUDENC_ANA_CON21 0x2532
65#define MT6359_AUDENC_ANA_CON22 0x2534
66#define MT6359_AUDENC_ANA_CON23 0x2536
67#define MT6359_AUDDEC_DSN_ID 0x2580
68#define MT6359_AUDDEC_DSN_REV0 0x2582
69#define MT6359_AUDDEC_DSN_DBI 0x2584
70#define MT6359_AUDDEC_DSN_FPI 0x2586
71#define MT6359_AUDDEC_ANA_CON0 0x2588
72#define MT6359_AUDDEC_ANA_CON1 0x258a
73#define MT6359_AUDDEC_ANA_CON2 0x258c
74#define MT6359_AUDDEC_ANA_CON3 0x258e
75#define MT6359_AUDDEC_ANA_CON4 0x2590
76#define MT6359_AUDDEC_ANA_CON5 0x2592
77#define MT6359_AUDDEC_ANA_CON6 0x2594
78#define MT6359_AUDDEC_ANA_CON7 0x2596
79#define MT6359_AUDDEC_ANA_CON8 0x2598
80#define MT6359_AUDDEC_ANA_CON9 0x259a
81#define MT6359_AUDDEC_ANA_CON10 0x259c
82#define MT6359_AUDDEC_ANA_CON11 0x259e
83#define MT6359_AUDDEC_ANA_CON12 0x25a0
84#define MT6359_AUDDEC_ANA_CON13 0x25a2
85#define MT6359_AUDDEC_ANA_CON14 0x25a4
86#define MT6359_ACCDET_DSN_DIG_ID 0x2680
87#define MT6359_ACCDET_DSN_DIG_REV0 0x2682
88#define MT6359_ACCDET_DSN_DBI 0x2684
89#define MT6359_ACCDET_DSN_FPI 0x2686
90#define MT6359_ACCDET_CON0 0x2688
91#define MT6359_ACCDET_CON1 0x268a
92#define MT6359_ACCDET_CON2 0x268c
93#define MT6359_ACCDET_CON3 0x268e
94#define MT6359_ACCDET_CON4 0x2690
95#define MT6359_ACCDET_CON5 0x2692
96#define MT6359_ACCDET_CON6 0x2694
97#define MT6359_ACCDET_CON7 0x2696
98#define MT6359_ACCDET_CON8 0x2698
99#define MT6359_ACCDET_CON9 0x269a
100#define MT6359_ACCDET_CON10 0x269c
101#define MT6359_ACCDET_CON11 0x269e
102#define MT6359_ACCDET_CON12 0x26a0
103#define MT6359_ACCDET_CON13 0x26a2
104#define MT6359_ACCDET_CON14 0x26a4
105#define MT6359_ACCDET_CON15 0x26a6
106#define MT6359_ACCDET_CON16 0x26a8
107#define MT6359_ACCDET_CON17 0x26aa
108#define MT6359_ACCDET_CON18 0x26ac
109#define MT6359_ACCDET_CON19 0x26ae
110#define MT6359_ACCDET_CON20 0x26b0
111#define MT6359_ACCDET_CON21 0x26b2
112#define MT6359_ACCDET_CON22 0x26b4
113#define MT6359_ACCDET_CON23 0x26b6
114#define MT6359_ACCDET_CON24 0x26b8
115#define MT6359_ACCDET_CON25 0x26ba
116#define MT6359_ACCDET_CON26 0x26bc
117#define MT6359_ACCDET_CON27 0x26be
118#define MT6359_ACCDET_CON28 0x26c0
119#define MT6359_ACCDET_CON29 0x26c2
120#define MT6359_ACCDET_CON30 0x26c4
121#define MT6359_ACCDET_CON31 0x26c6
122#define MT6359_ACCDET_CON32 0x26c8
123#define MT6359_ACCDET_CON33 0x26ca
124#define MT6359_ACCDET_CON34 0x26cc
125#define MT6359_ACCDET_CON35 0x26ce
126#define MT6359_ACCDET_CON36 0x26d0
127#define MT6359_ACCDET_CON37 0x26d2
128#define MT6359_ACCDET_CON38 0x26d4
129#define MT6359_ACCDET_CON39 0x26d6
130#define MT6359_ACCDET_CON40 0x26d8
79
131
80/* AUDENC_ANA_CON16: */
81#define RG_AUD_MICBIAS1_LOWP_EN BIT(PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT)
132#define TOP0_ANA_ID_ADDR \
133 MT6359_TOP0_ID
134#define TOP0_ANA_ID_SFT 0
135#define TOP0_ANA_ID_MASK 0xFF
136#define TOP0_ANA_ID_MASK_SFT (0xFF << 0)
137#define AUXADC_RQST_CH0_ADDR \
138 MT6359_AUXADC_RQST0
139#define AUXADC_RQST_CH0_SFT 0
140#define AUXADC_RQST_CH0_MASK 0x1
141#define AUXADC_RQST_CH0_MASK_SFT (0x1 << 0)
142#define AUXADC_ACCDET_ANASWCTRL_EN_ADDR \
143 MT6359_AUXADC_CON15
144#define AUXADC_ACCDET_ANASWCTRL_EN_SFT 6
145#define AUXADC_ACCDET_ANASWCTRL_EN_MASK 0x1
146#define AUXADC_ACCDET_ANASWCTRL_EN_MASK_SFT (0x1 << 6)
82
147
148#define AUXADC_ACCDET_AUTO_SPL_ADDR \
149 MT6359_AUXADC_ACCDET
150#define AUXADC_ACCDET_AUTO_SPL_SFT 0
151#define AUXADC_ACCDET_AUTO_SPL_MASK 0x1
152#define AUXADC_ACCDET_AUTO_SPL_MASK_SFT (0x1 << 0)
153#define AUXADC_ACCDET_AUTO_RQST_CLR_ADDR \
154 MT6359_AUXADC_ACCDET
155#define AUXADC_ACCDET_AUTO_RQST_CLR_SFT 1
156#define AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1
157#define AUXADC_ACCDET_AUTO_RQST_CLR_MASK_SFT (0x1 << 1)
158#define AUXADC_ACCDET_DIG1_RSV0_ADDR \
159 MT6359_AUXADC_ACCDET
160#define AUXADC_ACCDET_DIG1_RSV0_SFT 2
161#define AUXADC_ACCDET_DIG1_RSV0_MASK 0x3F
162#define AUXADC_ACCDET_DIG1_RSV0_MASK_SFT (0x3F << 2)
163#define AUXADC_ACCDET_DIG0_RSV0_ADDR \
164 MT6359_AUXADC_ACCDET
165#define AUXADC_ACCDET_DIG0_RSV0_SFT 8
166#define AUXADC_ACCDET_DIG0_RSV0_MASK 0xFF
167#define AUXADC_ACCDET_DIG0_RSV0_MASK_SFT (0xFF << 8)
168
169#define RG_ACCDET_CK_PDN_ADDR \
170 MT6359_AUD_TOP_CKPDN_CON0
171#define RG_ACCDET_CK_PDN_SFT 0
172#define RG_ACCDET_CK_PDN_MASK 0x1
173#define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
174
175#define RG_ACCDET_RST_ADDR \
176 MT6359_AUD_TOP_RST_CON0
177#define RG_ACCDET_RST_SFT 1
178#define RG_ACCDET_RST_MASK 0x1
179#define RG_ACCDET_RST_MASK_SFT (0x1 << 1)
180#define BANK_ACCDET_SWRST_ADDR \
181 MT6359_AUD_TOP_RST_BANK_CON0
182#define BANK_ACCDET_SWRST_SFT 0
183#define BANK_ACCDET_SWRST_MASK 0x1
184#define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)
185
186#define RG_INT_EN_ACCDET_ADDR \
187 MT6359_AUD_TOP_INT_CON0
188#define RG_INT_EN_ACCDET_SFT 5
189#define RG_INT_EN_ACCDET_MASK 0x1
190#define RG_INT_EN_ACCDET_MASK_SFT (0x1 << 5)
191#define RG_INT_EN_ACCDET_EINT0_ADDR \
192 MT6359_AUD_TOP_INT_CON0
193#define RG_INT_EN_ACCDET_EINT0_SFT 6
194#define RG_INT_EN_ACCDET_EINT0_MASK 0x1
195#define RG_INT_EN_ACCDET_EINT0_MASK_SFT (0x1 << 6)
196#define RG_INT_EN_ACCDET_EINT1_ADDR \
197 MT6359_AUD_TOP_INT_CON0
198#define RG_INT_EN_ACCDET_EINT1_SFT 7
199#define RG_INT_EN_ACCDET_EINT1_MASK 0x1
200#define RG_INT_EN_ACCDET_EINT1_MASK_SFT (0x1 << 7)
201
202#define RG_INT_MASK_ACCDET_ADDR \
203 MT6359_AUD_TOP_INT_MASK_CON0
204#define RG_INT_MASK_ACCDET_SFT 5
205#define RG_INT_MASK_ACCDET_MASK 0x1
206#define RG_INT_MASK_ACCDET_MASK_SFT (0x1 << 5)
207#define RG_INT_MASK_ACCDET_EINT0_ADDR \
208 MT6359_AUD_TOP_INT_MASK_CON0
209#define RG_INT_MASK_ACCDET_EINT0_SFT 6
210#define RG_INT_MASK_ACCDET_EINT0_MASK 0x1
211#define RG_INT_MASK_ACCDET_EINT0_MASK_SFT (0x1 << 6)
212#define RG_INT_MASK_ACCDET_EINT1_ADDR \
213 MT6359_AUD_TOP_INT_MASK_CON0
214#define RG_INT_MASK_ACCDET_EINT1_SFT 7
215#define RG_INT_MASK_ACCDET_EINT1_MASK 0x1
216#define RG_INT_MASK_ACCDET_EINT1_MASK_SFT (0x1 << 7)
217
218#define RG_INT_STATUS_ACCDET_ADDR \
219 MT6359_AUD_TOP_INT_STATUS0
220#define RG_INT_STATUS_ACCDET_SFT 5
221#define RG_INT_STATUS_ACCDET_MASK 0x1
222#define RG_INT_STATUS_ACCDET_MASK_SFT (0x1 << 5)
223#define RG_INT_STATUS_ACCDET_EINT0_ADDR \
224 MT6359_AUD_TOP_INT_STATUS0
225#define RG_INT_STATUS_ACCDET_EINT0_SFT 6
226#define RG_INT_STATUS_ACCDET_EINT0_MASK 0x1
227#define RG_INT_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
228#define RG_INT_STATUS_ACCDET_EINT1_ADDR \
229 MT6359_AUD_TOP_INT_STATUS0
230#define RG_INT_STATUS_ACCDET_EINT1_SFT 7
231#define RG_INT_STATUS_ACCDET_EINT1_MASK 0x1
232#define RG_INT_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
233
234#define RG_INT_RAW_STATUS_ACCDET_ADDR \
235 MT6359_AUD_TOP_INT_RAW_STATUS0
236#define RG_INT_RAW_STATUS_ACCDET_SFT 5
237#define RG_INT_RAW_STATUS_ACCDET_MASK 0x1
238#define RG_INT_RAW_STATUS_ACCDET_MASK_SFT (0x1 << 5)
239#define RG_INT_RAW_STATUS_ACCDET_EINT0_ADDR \
240 MT6359_AUD_TOP_INT_RAW_STATUS0
241#define RG_INT_RAW_STATUS_ACCDET_EINT0_SFT 6
242#define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK 0x1
243#define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
244#define RG_INT_RAW_STATUS_ACCDET_EINT1_ADDR \
245 MT6359_AUD_TOP_INT_RAW_STATUS0
246#define RG_INT_RAW_STATUS_ACCDET_EINT1_SFT 7
247#define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK 0x1
248#define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
249
250#define RG_AUDACCDETMICBIAS0PULLLOW_ADDR \
251 MT6359_AUDENC_ANA_CON18
252#define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0
253#define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
254#define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)
255#define RG_AUDACCDETMICBIAS1PULLLOW_ADDR \
256 MT6359_AUDENC_ANA_CON18
257#define RG_AUDACCDETMICBIAS1PULLLOW_SFT 1
258#define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
259#define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)
260#define RG_AUDACCDETMICBIAS2PULLLOW_ADDR \
261 MT6359_AUDENC_ANA_CON18
262#define RG_AUDACCDETMICBIAS2PULLLOW_SFT 2
263#define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1
264#define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2)
265#define RG_AUDACCDETVIN1PULLLOW_ADDR \
266 MT6359_AUDENC_ANA_CON18
267#define RG_AUDACCDETVIN1PULLLOW_SFT 3
268#define RG_AUDACCDETVIN1PULLLOW_MASK 0x1
269#define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
270#define RG_AUDACCDETVTHACAL_ADDR \
271 MT6359_AUDENC_ANA_CON18
272#define RG_AUDACCDETVTHACAL_SFT 4
273#define RG_AUDACCDETVTHACAL_MASK 0x1
274#define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)
275#define RG_AUDACCDETVTHBCAL_ADDR \
276 MT6359_AUDENC_ANA_CON18
277#define RG_AUDACCDETVTHBCAL_SFT 5
278#define RG_AUDACCDETVTHBCAL_MASK 0x1
279#define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)
280#define RG_AUDACCDETTVDET_ADDR \
281 MT6359_AUDENC_ANA_CON18
282#define RG_AUDACCDETTVDET_SFT 6
283#define RG_AUDACCDETTVDET_MASK 0x1
284#define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)
285#define RG_ACCDETSEL_ADDR \
286 MT6359_AUDENC_ANA_CON18
287#define RG_ACCDETSEL_SFT 7
288#define RG_ACCDETSEL_MASK 0x1
289#define RG_ACCDETSEL_MASK_SFT (0x1 << 7)
290
291#define RG_AUDPWDBMICBIAS1_ADDR \
292 MT6359_AUDENC_ANA_CON16
293#define RG_AUDPWDBMICBIAS1_SFT 0
294#define RG_AUDPWDBMICBIAS1_MASK 0x1
295#define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)
296#define RG_AUDMICBIAS1BYPASSEN_ADDR \
297 MT6359_AUDENC_ANA_CON16
298#define RG_AUDMICBIAS1BYPASSEN_SFT 1
299#define RG_AUDMICBIAS1BYPASSEN_MASK 0x1
300#define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)
301#define RG_AUDMICBIAS1LOWPEN_ADDR \
302 MT6359_AUDENC_ANA_CON16
303#define RG_AUDMICBIAS1LOWPEN_SFT 2
304#define RG_AUDMICBIAS1LOWPEN_MASK 0x1
305#define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)
306#define RG_AUDMICBIAS1VREF_ADDR \
307 MT6359_AUDENC_ANA_CON16
308#define RG_AUDMICBIAS1VREF_SFT 4
309#define RG_AUDMICBIAS1VREF_MASK 0x7
310#define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)
311#define RG_AUDMICBIAS1DCSW1PEN_ADDR \
312 MT6359_AUDENC_ANA_CON16
313#define RG_AUDMICBIAS1DCSW1PEN_SFT 8
314#define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1
315#define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)
316#define RG_AUDMICBIAS1DCSW1NEN_ADDR \
317 MT6359_AUDENC_ANA_CON16
318#define RG_AUDMICBIAS1DCSW1NEN_SFT 9
319#define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1
320#define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)
321#define RG_BANDGAPGEN_ADDR \
322 MT6359_AUDENC_ANA_CON16
323#define RG_BANDGAPGEN_SFT 10
324#define RG_BANDGAPGEN_MASK 0x1
325#define RG_BANDGAPGEN_MASK_SFT (0x1 << 10)
326#define RG_AUDMICBIAS1HVEN_ADDR \
327 MT6359_AUDENC_ANA_CON16
328#define RG_AUDMICBIAS1HVEN_SFT 12
329#define RG_AUDMICBIAS1HVEN_MASK 0x1
330#define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 12)
331#define RG_AUDMICBIAS1HVVREF_ADDR \
332 MT6359_AUDENC_ANA_CON16
333#define RG_AUDMICBIAS1HVVREF_SFT 13
334#define RG_AUDMICBIAS1HVVREF_MASK 0x1
335#define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 13)
336
337#define RG_EINT0NOHYS_ADDR \
338 MT6359_AUDENC_ANA_CON18
339#define RG_EINT0NOHYS_SFT 10
340#define RG_EINT0NOHYS_MASK 0x1
341#define RG_EINT0NOHYS_MASK_SFT (0x1 << 10)
342#define RG_EINT0CONFIGACCDET_ADDR \
343 MT6359_AUDENC_ANA_CON18
344#define RG_EINT0CONFIGACCDET_SFT 11
345#define RG_EINT0CONFIGACCDET_MASK 0x1
346#define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 11)
347#define RG_EINT0HIRENB_ADDR \
348 MT6359_AUDENC_ANA_CON18
349#define RG_EINT0HIRENB_SFT 12
350#define RG_EINT0HIRENB_MASK 0x1
351#define RG_EINT0HIRENB_MASK_SFT (0x1 << 12)
352#define RG_ACCDET2AUXRESBYPASS_ADDR \
353 MT6359_AUDENC_ANA_CON18
354#define RG_ACCDET2AUXRESBYPASS_SFT 13
355#define RG_ACCDET2AUXRESBYPASS_MASK 0x1
356#define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)
357#define RG_ACCDET2AUXSWEN_ADDR \
358 MT6359_AUDENC_ANA_CON18
359#define RG_ACCDET2AUXSWEN_SFT 14
360#define RG_ACCDET2AUXSWEN_MASK 0x1
361#define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 14)
362#define RG_AUDACCDETMICBIAS3PULLLOW_ADDR \
363 MT6359_AUDENC_ANA_CON18
364#define RG_AUDACCDETMICBIAS3PULLLOW_SFT 15
365#define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1
366#define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 15)
367#define RG_EINT1CONFIGACCDET_ADDR \
368 MT6359_AUDENC_ANA_CON19
369#define RG_EINT1CONFIGACCDET_SFT 0
370#define RG_EINT1CONFIGACCDET_MASK 0x1
371#define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0)
372#define RG_EINT1HIRENB_ADDR \
373 MT6359_AUDENC_ANA_CON19
374#define RG_EINT1HIRENB_SFT 1
375#define RG_EINT1HIRENB_MASK 0x1
376#define RG_EINT1HIRENB_MASK_SFT (0x1 << 1)
377#define RG_EINT1NOHYS_ADDR \
378 MT6359_AUDENC_ANA_CON19
379#define RG_EINT1NOHYS_SFT 2
380#define RG_EINT1NOHYS_MASK 0x1
381#define RG_EINT1NOHYS_MASK_SFT (0x1 << 2)
382#define RG_EINTCOMPVTH_ADDR \
383 MT6359_AUDENC_ANA_CON19
384#define RG_MTEST_EN_ADDR \
385 MT6359_AUDENC_ANA_CON19
386#define RG_MTEST_EN_SFT 8
387#define RG_MTEST_EN_MASK 0x1
388#define RG_MTEST_EN_MASK_SFT (0x1 << 8)
389#define RG_MTEST_SEL_ADDR \
390 MT6359_AUDENC_ANA_CON19
391#define RG_MTEST_SEL_SFT 9
392#define RG_MTEST_SEL_MASK 0x1
393#define RG_MTEST_SEL_MASK_SFT (0x1 << 9)
394#define RG_MTEST_CURRENT_ADDR \
395 MT6359_AUDENC_ANA_CON19
396#define RG_MTEST_CURRENT_SFT 10
397#define RG_MTEST_CURRENT_MASK 0x1
398#define RG_MTEST_CURRENT_MASK_SFT (0x1 << 10)
399#define RG_ANALOGFDEN_ADDR \
400 MT6359_AUDENC_ANA_CON19
401#define RG_ANALOGFDEN_SFT 12
402#define RG_ANALOGFDEN_MASK 0x1
403#define RG_ANALOGFDEN_MASK_SFT (0x1 << 12)
404#define RG_FDVIN1PPULLLOW_ADDR \
405 MT6359_AUDENC_ANA_CON19
406#define RG_FDVIN1PPULLLOW_SFT 13
407#define RG_FDVIN1PPULLLOW_MASK 0x1
408#define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 13)
409#define RG_FDEINT0TYPE_ADDR \
410 MT6359_AUDENC_ANA_CON19
411#define RG_FDEINT0TYPE_SFT 14
412#define RG_FDEINT0TYPE_MASK 0x1
413#define RG_FDEINT0TYPE_MASK_SFT (0x1 << 14)
414#define RG_FDEINT1TYPE_ADDR \
415 MT6359_AUDENC_ANA_CON19
416#define RG_FDEINT1TYPE_SFT 15
417#define RG_FDEINT1TYPE_MASK 0x1
418#define RG_FDEINT1TYPE_MASK_SFT (0x1 << 15)
419#define RG_EINT0CMPEN_ADDR \
420 MT6359_AUDENC_ANA_CON20
421#define RG_EINT0CMPEN_SFT 0
422#define RG_EINT0CMPEN_MASK 0x1
423#define RG_EINT0CMPEN_MASK_SFT (0x1 << 0)
424#define RG_EINT0CMPMEN_ADDR \
425 MT6359_AUDENC_ANA_CON20
426#define RG_EINT0CMPMEN_SFT 1
427#define RG_EINT0CMPMEN_MASK 0x1
428#define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1)
429#define RG_EINT0EN_ADDR \
430 MT6359_AUDENC_ANA_CON20
431#define RG_EINT0EN_SFT 2
432#define RG_EINT0EN_MASK 0x1
433#define RG_EINT0EN_MASK_SFT (0x1 << 2)
434#define RG_EINT0CEN_ADDR \
435 MT6359_AUDENC_ANA_CON20
436#define RG_EINT0CEN_SFT 3
437#define RG_EINT0CEN_MASK 0x1
438#define RG_EINT0CEN_MASK_SFT (0x1 << 3)
439#define RG_EINT0INVEN_ADDR \
440 MT6359_AUDENC_ANA_CON20
441#define RG_EINT0INVEN_SFT 4
442#define RG_EINT0INVEN_MASK 0x1
443#define RG_EINT0INVEN_MASK_SFT (0x1 << 4)
444#define RG_EINT0CTURBO_ADDR \
445 MT6359_AUDENC_ANA_CON20
446#define RG_EINT0CTURBO_SFT 5
447#define RG_EINT0CTURBO_MASK 0x7
448#define RG_EINT0CTURBO_MASK_SFT (0x7 << 5)
449#define RG_EINT1CMPEN_ADDR \
450 MT6359_AUDENC_ANA_CON20
451#define RG_EINT1CMPEN_SFT 8
452#define RG_EINT1CMPEN_MASK 0x1
453#define RG_EINT1CMPEN_MASK_SFT (0x1 << 8)
454#define RG_EINT1CMPMEN_ADDR \
455 MT6359_AUDENC_ANA_CON20
456#define RG_EINT1CMPMEN_SFT 9
457#define RG_EINT1CMPMEN_MASK 0x1
458#define RG_EINT1CMPMEN_MASK_SFT (0x1 << 9)
459#define RG_EINT1EN_ADDR \
460 MT6359_AUDENC_ANA_CON20
461#define RG_EINT1EN_SFT 10
462#define RG_EINT1EN_MASK 0x1
463#define RG_EINT1EN_MASK_SFT (0x1 << 10)
464#define RG_EINT1CEN_ADDR \
465 MT6359_AUDENC_ANA_CON20
466#define RG_EINT1CEN_SFT 11
467#define RG_EINT1CEN_MASK 0x1
468#define RG_EINT1CEN_MASK_SFT (0x1 << 11)
469#define RG_EINT1INVEN_ADDR \
470 MT6359_AUDENC_ANA_CON20
471#define RG_EINT1INVEN_SFT 12
472#define RG_EINT1INVEN_MASK 0x1
473#define RG_EINT1INVEN_MASK_SFT (0x1 << 12)
474#define RG_EINT1CTURBO_ADDR \
475 MT6359_AUDENC_ANA_CON20
476#define RG_EINT1CTURBO_SFT 13
477#define RG_EINT1CTURBO_MASK 0x7
478#define RG_EINT1CTURBO_MASK_SFT (0x7 << 13)
479#define RG_ACCDETSPARE_ADDR \
480 MT6359_AUDENC_ANA_CON21
481
482#define ACCDET_ANA_ID_ADDR \
483 MT6359_ACCDET_DSN_DIG_ID
484#define ACCDET_ANA_ID_SFT 0
485#define ACCDET_ANA_ID_MASK 0xFF
486#define ACCDET_ANA_ID_MASK_SFT (0xFF << 0)
487#define ACCDET_DIG_ID_ADDR \
488 MT6359_ACCDET_DSN_DIG_ID
489#define ACCDET_DIG_ID_SFT 8
490#define ACCDET_DIG_ID_MASK 0xFF
491#define ACCDET_DIG_ID_MASK_SFT (0xFF << 8)
492#define ACCDET_ANA_MINOR_REV_ADDR \
493 MT6359_ACCDET_DSN_DIG_REV0
494#define ACCDET_ANA_MINOR_REV_SFT 0
495#define ACCDET_ANA_MINOR_REV_MASK 0xF
496#define ACCDET_ANA_MINOR_REV_MASK_SFT (0xF << 0)
497#define ACCDET_ANA_MAJOR_REV_ADDR \
498 MT6359_ACCDET_DSN_DIG_REV0
499#define ACCDET_ANA_MAJOR_REV_SFT 4
500#define ACCDET_ANA_MAJOR_REV_MASK 0xF
501#define ACCDET_ANA_MAJOR_REV_MASK_SFT (0xF << 4)
502#define ACCDET_DIG_MINOR_REV_ADDR \
503 MT6359_ACCDET_DSN_DIG_REV0
504#define ACCDET_DIG_MINOR_REV_SFT 8
505#define ACCDET_DIG_MINOR_REV_MASK 0xF
506#define ACCDET_DIG_MINOR_REV_MASK_SFT (0xF << 8)
507#define ACCDET_DIG_MAJOR_REV_ADDR \
508 MT6359_ACCDET_DSN_DIG_REV0
509#define ACCDET_DIG_MAJOR_REV_SFT 12
510#define ACCDET_DIG_MAJOR_REV_MASK 0xF
511#define ACCDET_DIG_MAJOR_REV_MASK_SFT (0xF << 12)
512#define ACCDET_DSN_CBS_ADDR \
513 MT6359_ACCDET_DSN_DBI
514#define ACCDET_DSN_CBS_SFT 0
515#define ACCDET_DSN_CBS_MASK 0x3
516#define ACCDET_DSN_CBS_MASK_SFT (0x3 << 0)
517#define ACCDET_DSN_BIX_ADDR \
518 MT6359_ACCDET_DSN_DBI
519#define ACCDET_DSN_BIX_SFT 2
520#define ACCDET_DSN_BIX_MASK 0x3
521#define ACCDET_DSN_BIX_MASK_SFT (0x3 << 2)
522#define ACCDET_ESP_ADDR \
523 MT6359_ACCDET_DSN_DBI
524#define ACCDET_ESP_SFT 8
525#define ACCDET_ESP_MASK 0xFF
526#define ACCDET_ESP_MASK_SFT (0xFF << 8)
527#define ACCDET_DSN_FPI_ADDR \
528 MT6359_ACCDET_DSN_FPI
529#define ACCDET_DSN_FPI_SFT 0
530#define ACCDET_DSN_FPI_MASK 0xFF
531#define ACCDET_DSN_FPI_MASK_SFT (0xFF << 0)
532#define ACCDET_AUXADC_SEL_ADDR \
533 MT6359_ACCDET_CON0
534#define ACCDET_AUXADC_SEL_SFT 0
535#define ACCDET_AUXADC_SEL_MASK 0x1
536#define ACCDET_AUXADC_SEL_MASK_SFT (0x1 << 0)
537#define ACCDET_AUXADC_SW_ADDR \
538 MT6359_ACCDET_CON0
539#define ACCDET_AUXADC_SW_SFT 1
540#define ACCDET_AUXADC_SW_MASK 0x1
541#define ACCDET_AUXADC_SW_MASK_SFT (0x1 << 1)
542#define ACCDET_TEST_AUXADC_ADDR \
543 MT6359_ACCDET_CON0
544#define ACCDET_TEST_AUXADC_SFT 2
545#define ACCDET_TEST_AUXADC_MASK 0x1
546#define ACCDET_TEST_AUXADC_MASK_SFT (0x1 << 2)
547#define ACCDET_AUXADC_ANASWCTRL_SEL_ADDR \
548 MT6359_ACCDET_CON0
549#define ACCDET_AUXADC_ANASWCTRL_SEL_SFT 8
550#define ACCDET_AUXADC_ANASWCTRL_SEL_MASK 0x1
551#define ACCDET_AUXADC_ANASWCTRL_SEL_MASK_SFT (0x1 << 8)
552#define AUDACCDETAUXADCSWCTRL_SEL_ADDR \
553 MT6359_ACCDET_CON0
554#define AUDACCDETAUXADCSWCTRL_SEL_SFT 9
555#define AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1
556#define AUDACCDETAUXADCSWCTRL_SEL_MASK_SFT (0x1 << 9)
557#define AUDACCDETAUXADCSWCTRL_SW_ADDR \
558 MT6359_ACCDET_CON0
559#define AUDACCDETAUXADCSWCTRL_SW_SFT 10
560#define AUDACCDETAUXADCSWCTRL_SW_MASK 0x1
561#define AUDACCDETAUXADCSWCTRL_SW_MASK_SFT (0x1 << 10)
562#define ACCDET_TEST_ANA_ADDR \
563 MT6359_ACCDET_CON0
564#define ACCDET_TEST_ANA_SFT 11
565#define ACCDET_TEST_ANA_MASK 0x1
566#define ACCDET_TEST_ANA_MASK_SFT (0x1 << 11)
567#define RG_AUDACCDETRSV_ADDR \
568 MT6359_ACCDET_CON0
569#define RG_AUDACCDETRSV_SFT 13
570#define RG_AUDACCDETRSV_MASK 0x3
571#define RG_AUDACCDETRSV_MASK_SFT (0x3 << 13)
572#define ACCDET_SW_EN_ADDR \
573 MT6359_ACCDET_CON1
574#define ACCDET_SW_EN_SFT 0
575#define ACCDET_SW_EN_MASK 0x1
576#define ACCDET_SW_EN_MASK_SFT (0x1 << 0)
577#define ACCDET_SEQ_INIT_ADDR \
578 MT6359_ACCDET_CON1
579#define ACCDET_SEQ_INIT_SFT 1
580#define ACCDET_SEQ_INIT_MASK 0x1
581#define ACCDET_SEQ_INIT_MASK_SFT (0x1 << 1)
582#define ACCDET_EINT0_SW_EN_ADDR \
583 MT6359_ACCDET_CON1
584#define ACCDET_EINT0_SW_EN_SFT 2
585#define ACCDET_EINT0_SW_EN_MASK 0x1
586#define ACCDET_EINT0_SW_EN_MASK_SFT (0x1 << 2)
587#define ACCDET_EINT0_SEQ_INIT_ADDR \
588 MT6359_ACCDET_CON1
589#define ACCDET_EINT0_SEQ_INIT_SFT 3
590#define ACCDET_EINT0_SEQ_INIT_MASK 0x1
591#define ACCDET_EINT0_SEQ_INIT_MASK_SFT (0x1 << 3)
592#define ACCDET_EINT1_SW_EN_ADDR \
593 MT6359_ACCDET_CON1
594#define ACCDET_EINT1_SW_EN_SFT 4
595#define ACCDET_EINT1_SW_EN_MASK 0x1
596#define ACCDET_EINT1_SW_EN_MASK_SFT (0x1 << 4)
597#define ACCDET_EINT1_SEQ_INIT_ADDR \
598 MT6359_ACCDET_CON1
599#define ACCDET_EINT1_SEQ_INIT_SFT 5
600#define ACCDET_EINT1_SEQ_INIT_MASK 0x1
601#define ACCDET_EINT1_SEQ_INIT_MASK_SFT (0x1 << 5)
602#define ACCDET_EINT0_INVERTER_SW_EN_ADDR \
603 MT6359_ACCDET_CON1
604#define ACCDET_EINT0_INVERTER_SW_EN_SFT 6
605#define ACCDET_EINT0_INVERTER_SW_EN_MASK 0x1
606#define ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT (0x1 << 6)
607#define ACCDET_EINT0_INVERTER_SEQ_INIT_ADDR \
608 MT6359_ACCDET_CON1
609#define ACCDET_EINT0_INVERTER_SEQ_INIT_SFT 7
610#define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK 0x1
611#define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 7)
612#define ACCDET_EINT1_INVERTER_SW_EN_ADDR \
613 MT6359_ACCDET_CON1
614#define ACCDET_EINT1_INVERTER_SW_EN_SFT 8
615#define ACCDET_EINT1_INVERTER_SW_EN_MASK 0x1
616#define ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT (0x1 << 8)
617#define ACCDET_EINT1_INVERTER_SEQ_INIT_ADDR \
618 MT6359_ACCDET_CON1
619#define ACCDET_EINT1_INVERTER_SEQ_INIT_SFT 9
620#define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK 0x1
621#define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 9)
622#define ACCDET_EINT0_M_SW_EN_ADDR \
623 MT6359_ACCDET_CON1
624#define ACCDET_EINT0_M_SW_EN_SFT 10
625#define ACCDET_EINT0_M_SW_EN_MASK 0x1
626#define ACCDET_EINT0_M_SW_EN_MASK_SFT (0x1 << 10)
627#define ACCDET_EINT1_M_SW_EN_ADDR \
628 MT6359_ACCDET_CON1
629#define ACCDET_EINT1_M_SW_EN_SFT 11
630#define ACCDET_EINT1_M_SW_EN_MASK 0x1
631#define ACCDET_EINT1_M_SW_EN_MASK_SFT (0x1 << 11)
632#define ACCDET_EINT_M_DETECT_EN_ADDR \
633 MT6359_ACCDET_CON1
634#define ACCDET_EINT_M_DETECT_EN_SFT 12
635#define ACCDET_EINT_M_DETECT_EN_MASK 0x1
636#define ACCDET_EINT_M_DETECT_EN_MASK_SFT (0x1 << 12)
637#define ACCDET_CMP_PWM_EN_ADDR \
638 MT6359_ACCDET_CON2
639#define ACCDET_CMP_PWM_EN_SFT 0
640#define ACCDET_CMP_PWM_EN_MASK 0x1
641#define ACCDET_CMP_PWM_EN_MASK_SFT (0x1 << 0)
642#define ACCDET_VTH_PWM_EN_ADDR \
643 MT6359_ACCDET_CON2
644#define ACCDET_VTH_PWM_EN_SFT 1
645#define ACCDET_VTH_PWM_EN_MASK 0x1
646#define ACCDET_VTH_PWM_EN_MASK_SFT (0x1 << 1)
647#define ACCDET_MBIAS_PWM_EN_ADDR \
648 MT6359_ACCDET_CON2
649#define ACCDET_MBIAS_PWM_EN_SFT 2
650#define ACCDET_MBIAS_PWM_EN_MASK 0x1
651#define ACCDET_MBIAS_PWM_EN_MASK_SFT (0x1 << 2)
652#define ACCDET_EINT_EN_PWM_EN_ADDR \
653 MT6359_ACCDET_CON2
654#define ACCDET_EINT_EN_PWM_EN_SFT 3
655#define ACCDET_EINT_EN_PWM_EN_MASK 0x1
656#define ACCDET_EINT_EN_PWM_EN_MASK_SFT (0x1 << 3)
657#define ACCDET_EINT_CMPEN_PWM_EN_ADDR \
658 MT6359_ACCDET_CON2
659#define ACCDET_EINT_CMPEN_PWM_EN_SFT 4
660#define ACCDET_EINT_CMPEN_PWM_EN_MASK 0x1
661#define ACCDET_EINT_CMPEN_PWM_EN_MASK_SFT (0x1 << 4)
662#define ACCDET_EINT_CMPMEN_PWM_EN_ADDR \
663 MT6359_ACCDET_CON2
664#define ACCDET_EINT_CMPMEN_PWM_EN_SFT 5
665#define ACCDET_EINT_CMPMEN_PWM_EN_MASK 0x1
666#define ACCDET_EINT_CMPMEN_PWM_EN_MASK_SFT (0x1 << 5)
667#define ACCDET_EINT_CTURBO_PWM_EN_ADDR \
668 MT6359_ACCDET_CON2
669#define ACCDET_EINT_CTURBO_PWM_EN_SFT 6
670#define ACCDET_EINT_CTURBO_PWM_EN_MASK 0x1
671#define ACCDET_EINT_CTURBO_PWM_EN_MASK_SFT (0x1 << 6)
672#define ACCDET_CMP_PWM_IDLE_ADDR \
673 MT6359_ACCDET_CON2
674#define ACCDET_CMP_PWM_IDLE_SFT 8
675#define ACCDET_CMP_PWM_IDLE_MASK 0x1
676#define ACCDET_CMP_PWM_IDLE_MASK_SFT (0x1 << 8)
677#define ACCDET_VTH_PWM_IDLE_ADDR \
678 MT6359_ACCDET_CON2
679#define ACCDET_VTH_PWM_IDLE_SFT 9
680#define ACCDET_VTH_PWM_IDLE_MASK 0x1
681#define ACCDET_VTH_PWM_IDLE_MASK_SFT (0x1 << 9)
682#define ACCDET_MBIAS_PWM_IDLE_ADDR \
683 MT6359_ACCDET_CON2
684#define ACCDET_MBIAS_PWM_IDLE_SFT 10
685#define ACCDET_MBIAS_PWM_IDLE_MASK 0x1
686#define ACCDET_MBIAS_PWM_IDLE_MASK_SFT (0x1 << 10)
687#define ACCDET_EINT0_CMPEN_PWM_IDLE_ADDR \
688 MT6359_ACCDET_CON2
689#define ACCDET_EINT0_CMPEN_PWM_IDLE_SFT 11
690#define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK 0x1
691#define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 11)
692#define ACCDET_EINT1_CMPEN_PWM_IDLE_ADDR \
693 MT6359_ACCDET_CON2
694#define ACCDET_EINT1_CMPEN_PWM_IDLE_SFT 12
695#define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK 0x1
696#define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 12)
697#define ACCDET_PWM_EN_SW_ADDR \
698 MT6359_ACCDET_CON2
699#define ACCDET_PWM_EN_SW_SFT 13
700#define ACCDET_PWM_EN_SW_MASK 0x1
701#define ACCDET_PWM_EN_SW_MASK_SFT (0x1 << 13)
702#define ACCDET_PWM_EN_SEL_ADDR \
703 MT6359_ACCDET_CON2
704#define ACCDET_PWM_EN_SEL_SFT 14
705#define ACCDET_PWM_EN_SEL_MASK 0x3
706#define ACCDET_PWM_EN_SEL_MASK_SFT (0x3 << 14)
707#define ACCDET_PWM_WIDTH_ADDR \
708 MT6359_ACCDET_CON3
709#define ACCDET_PWM_WIDTH_SFT 0
710#define ACCDET_PWM_WIDTH_MASK 0xFFFF
711#define ACCDET_PWM_WIDTH_MASK_SFT (0xFFFF << 0)
712#define ACCDET_PWM_THRESH_ADDR \
713 MT6359_ACCDET_CON4
714#define ACCDET_PWM_THRESH_SFT 0
715#define ACCDET_PWM_THRESH_MASK 0xFFFF
716#define ACCDET_PWM_THRESH_MASK_SFT (0xFFFF << 0)
717#define ACCDET_RISE_DELAY_ADDR \
718 MT6359_ACCDET_CON5
719#define ACCDET_RISE_DELAY_SFT 0
720#define ACCDET_RISE_DELAY_MASK 0x7FFF
721#define ACCDET_RISE_DELAY_MASK_SFT (0x7FFF << 0)
722#define ACCDET_FALL_DELAY_ADDR \
723 MT6359_ACCDET_CON5
724#define ACCDET_FALL_DELAY_SFT 15
725#define ACCDET_FALL_DELAY_MASK 0x1
726#define ACCDET_FALL_DELAY_MASK_SFT (0x1 << 15)
727#define ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR \
728 MT6359_ACCDET_CON6
729#define ACCDET_EINT_CMPMEN_PWM_THRESH_SFT 0
730#define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK 0x7
731#define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK_SFT (0x7 << 0)
732#define ACCDET_EINT_CMPMEN_PWM_WIDTH_ADDR \
733 MT6359_ACCDET_CON6
734#define ACCDET_EINT_CMPMEN_PWM_WIDTH_SFT 4
735#define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK 0x7
736#define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK_SFT (0x7 << 4)
737#define ACCDET_EINT_EN_PWM_THRESH_ADDR \
738 MT6359_ACCDET_CON7
739#define ACCDET_EINT_EN_PWM_THRESH_SFT 0
740#define ACCDET_EINT_EN_PWM_THRESH_MASK 0x7
741#define ACCDET_EINT_EN_PWM_THRESH_MASK_SFT (0x7 << 0)
742#define ACCDET_EINT_EN_PWM_WIDTH_ADDR \
743 MT6359_ACCDET_CON7
744#define ACCDET_EINT_EN_PWM_WIDTH_SFT 4
745#define ACCDET_EINT_EN_PWM_WIDTH_MASK 0x3
746#define ACCDET_EINT_EN_PWM_WIDTH_MASK_SFT (0x3 << 4)
747#define ACCDET_EINT_CMPEN_PWM_THRESH_ADDR \
748 MT6359_ACCDET_CON7
749#define ACCDET_EINT_CMPEN_PWM_THRESH_SFT 8
750#define ACCDET_EINT_CMPEN_PWM_THRESH_MASK 0x7
751#define ACCDET_EINT_CMPEN_PWM_THRESH_MASK_SFT (0x7 << 8)
752#define ACCDET_EINT_CMPEN_PWM_WIDTH_ADDR \
753 MT6359_ACCDET_CON7
754#define ACCDET_EINT_CMPEN_PWM_WIDTH_SFT 12
755#define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK 0x3
756#define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK_SFT (0x3 << 12)
757#define ACCDET_DEBOUNCE0_ADDR \
758 MT6359_ACCDET_CON8
759#define ACCDET_DEBOUNCE0_SFT 0
760#define ACCDET_DEBOUNCE0_MASK 0xFFFF
761#define ACCDET_DEBOUNCE0_MASK_SFT (0xFFFF << 0)
762#define ACCDET_DEBOUNCE1_ADDR \
763 MT6359_ACCDET_CON9
764#define ACCDET_DEBOUNCE1_SFT 0
765#define ACCDET_DEBOUNCE1_MASK 0xFFFF
766#define ACCDET_DEBOUNCE1_MASK_SFT (0xFFFF << 0)
767#define ACCDET_DEBOUNCE2_ADDR \
768 MT6359_ACCDET_CON10
769#define ACCDET_DEBOUNCE2_SFT 0
770#define ACCDET_DEBOUNCE2_MASK 0xFFFF
771#define ACCDET_DEBOUNCE2_MASK_SFT (0xFFFF << 0)
772#define ACCDET_DEBOUNCE3_ADDR \
773 MT6359_ACCDET_CON11
774#define ACCDET_DEBOUNCE3_SFT 0
775#define ACCDET_DEBOUNCE3_MASK 0xFFFF
776#define ACCDET_DEBOUNCE3_MASK_SFT (0xFFFF << 0)
777#define ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR \
778 MT6359_ACCDET_CON12
779#define ACCDET_CONNECT_AUXADC_TIME_DIG_SFT 0
780#define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK 0xFFFF
781#define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK_SFT (0xFFFF << 0)
782#define ACCDET_CONNECT_AUXADC_TIME_ANA_ADDR \
783 MT6359_ACCDET_CON13
784#define ACCDET_CONNECT_AUXADC_TIME_ANA_SFT 0
785#define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK 0xFFFF
786#define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK_SFT (0xFFFF << 0)
787#define ACCDET_EINT_DEBOUNCE0_ADDR \
788 MT6359_ACCDET_CON14
789#define ACCDET_EINT_DEBOUNCE0_SFT 0
790#define ACCDET_EINT_DEBOUNCE0_MASK 0xF
791#define ACCDET_EINT_DEBOUNCE0_MASK_SFT (0xF << 0)
792#define ACCDET_EINT_DEBOUNCE1_ADDR \
793 MT6359_ACCDET_CON14
794#define ACCDET_EINT_DEBOUNCE1_SFT 4
795#define ACCDET_EINT_DEBOUNCE1_MASK 0xF
796#define ACCDET_EINT_DEBOUNCE1_MASK_SFT (0xF << 4)
797#define ACCDET_EINT_DEBOUNCE2_ADDR \
798 MT6359_ACCDET_CON14
799#define ACCDET_EINT_DEBOUNCE2_SFT 8
800#define ACCDET_EINT_DEBOUNCE2_MASK 0xF
801#define ACCDET_EINT_DEBOUNCE2_MASK_SFT (0xF << 8)
802#define ACCDET_EINT_DEBOUNCE3_ADDR \
803 MT6359_ACCDET_CON14
804#define ACCDET_EINT_DEBOUNCE3_SFT 12
805#define ACCDET_EINT_DEBOUNCE3_MASK 0xF
806#define ACCDET_EINT_DEBOUNCE3_MASK_SFT (0xF << 12)
807#define ACCDET_EINT_INVERTER_DEBOUNCE_ADDR \
808 MT6359_ACCDET_CON15
809#define ACCDET_EINT_INVERTER_DEBOUNCE_SFT 0
810#define ACCDET_EINT_INVERTER_DEBOUNCE_MASK 0xF
811#define ACCDET_EINT_INVERTER_DEBOUNCE_MASK_SFT (0xF << 0)
812#define ACCDET_IVAL_CUR_IN_ADDR \
813 MT6359_ACCDET_CON16
814#define ACCDET_IVAL_CUR_IN_SFT 0
815#define ACCDET_IVAL_CUR_IN_MASK 0x3
816#define ACCDET_IVAL_CUR_IN_MASK_SFT (0x3 << 0)
817#define ACCDET_IVAL_SAM_IN_ADDR \
818 MT6359_ACCDET_CON16
819#define ACCDET_IVAL_SAM_IN_SFT 2
820#define ACCDET_IVAL_SAM_IN_MASK 0x3
821#define ACCDET_IVAL_SAM_IN_MASK_SFT (0x3 << 2)
822#define ACCDET_IVAL_MEM_IN_ADDR \
823 MT6359_ACCDET_CON16
824#define ACCDET_IVAL_MEM_IN_SFT 4
825#define ACCDET_IVAL_MEM_IN_MASK 0x3
826#define ACCDET_IVAL_MEM_IN_MASK_SFT (0x3 << 4)
827#define ACCDET_EINT_IVAL_CUR_IN_ADDR \
828 MT6359_ACCDET_CON16
829#define ACCDET_EINT_IVAL_CUR_IN_SFT 6
830#define ACCDET_EINT_IVAL_CUR_IN_MASK 0x3
831#define ACCDET_EINT_IVAL_CUR_IN_MASK_SFT (0x3 << 6)
832#define ACCDET_EINT_IVAL_SAM_IN_ADDR \
833 MT6359_ACCDET_CON16
834#define ACCDET_EINT_IVAL_SAM_IN_SFT 8
835#define ACCDET_EINT_IVAL_SAM_IN_MASK 0x3
836#define ACCDET_EINT_IVAL_SAM_IN_MASK_SFT (0x3 << 8)
837#define ACCDET_EINT_IVAL_MEM_IN_ADDR \
838 MT6359_ACCDET_CON16
839#define ACCDET_EINT_IVAL_MEM_IN_SFT 10
840#define ACCDET_EINT_IVAL_MEM_IN_MASK 0x3
841#define ACCDET_EINT_IVAL_MEM_IN_MASK_SFT (0x3 << 10)
842#define ACCDET_IVAL_SEL_ADDR \
843 MT6359_ACCDET_CON16
844#define ACCDET_IVAL_SEL_SFT 12
845#define ACCDET_IVAL_SEL_MASK 0x1
846#define ACCDET_IVAL_SEL_MASK_SFT (0x1 << 12)
847#define ACCDET_EINT_IVAL_SEL_ADDR \
848 MT6359_ACCDET_CON16
849#define ACCDET_EINT_IVAL_SEL_SFT 13
850#define ACCDET_EINT_IVAL_SEL_MASK 0x1
851#define ACCDET_EINT_IVAL_SEL_MASK_SFT (0x1 << 13)
852#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_ADDR \
853 MT6359_ACCDET_CON17
854#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_SFT 0
855#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK 0x1
856#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK_SFT (0x1 << 0)
857#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_ADDR \
858 MT6359_ACCDET_CON17
859#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_SFT 1
860#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK 0x1
861#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK_SFT (0x1 << 1)
862#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_ADDR \
863 MT6359_ACCDET_CON17
864#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_SFT 2
865#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK 0x1
866#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK_SFT (0x1 << 2)
867#define ACCDET_EINT_INVERTER_IVAL_SEL_ADDR \
868 MT6359_ACCDET_CON17
869#define ACCDET_EINT_INVERTER_IVAL_SEL_SFT 3
870#define ACCDET_EINT_INVERTER_IVAL_SEL_MASK 0x1
871#define ACCDET_EINT_INVERTER_IVAL_SEL_MASK_SFT (0x1 << 3)
872#define ACCDET_IRQ_ADDR \
873 MT6359_ACCDET_CON18
874#define ACCDET_IRQ_SFT 0
875#define ACCDET_IRQ_MASK 0x1
876#define ACCDET_IRQ_MASK_SFT (0x1 << 0)
877#define ACCDET_EINT0_IRQ_ADDR \
878 MT6359_ACCDET_CON18
879#define ACCDET_EINT0_IRQ_SFT 2
880#define ACCDET_EINT0_IRQ_MASK 0x1
881#define ACCDET_EINT0_IRQ_MASK_SFT (0x1 << 2)
882#define ACCDET_EINT1_IRQ_ADDR \
883 MT6359_ACCDET_CON18
884#define ACCDET_EINT1_IRQ_SFT 3
885#define ACCDET_EINT1_IRQ_MASK 0x1
886#define ACCDET_EINT1_IRQ_MASK_SFT (0x1 << 3)
887#define ACCDET_EINT_IN_INVERSE_ADDR \
888 MT6359_ACCDET_CON18
889#define ACCDET_EINT_IN_INVERSE_SFT 4
890#define ACCDET_EINT_IN_INVERSE_MASK 0x1
891#define ACCDET_EINT_IN_INVERSE_MASK_SFT (0x1 << 4)
892#define ACCDET_IRQ_CLR_ADDR \
893 MT6359_ACCDET_CON18
894#define ACCDET_IRQ_CLR_SFT 8
895#define ACCDET_IRQ_CLR_MASK 0x1
896#define ACCDET_IRQ_CLR_MASK_SFT (0x1 << 8)
897#define ACCDET_EINT0_IRQ_CLR_ADDR \
898 MT6359_ACCDET_CON18
899#define ACCDET_EINT0_IRQ_CLR_SFT 10
900#define ACCDET_EINT0_IRQ_CLR_MASK 0x1
901#define ACCDET_EINT0_IRQ_CLR_MASK_SFT (0x1 << 10)
902#define ACCDET_EINT1_IRQ_CLR_ADDR \
903 MT6359_ACCDET_CON18
904#define ACCDET_EINT1_IRQ_CLR_SFT 11
905#define ACCDET_EINT1_IRQ_CLR_MASK 0x1
906#define ACCDET_EINT1_IRQ_CLR_MASK_SFT (0x1 << 11)
907#define ACCDET_EINT_M_PLUG_IN_NUM_ADDR \
908 MT6359_ACCDET_CON18
909#define ACCDET_EINT_M_PLUG_IN_NUM_SFT 12
910#define ACCDET_EINT_M_PLUG_IN_NUM_MASK 0x7
911#define ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT (0x7 << 12)
912#define ACCDET_DA_STABLE_ADDR \
913 MT6359_ACCDET_CON19
914#define ACCDET_DA_STABLE_SFT 0
915#define ACCDET_DA_STABLE_MASK 0x1
916#define ACCDET_DA_STABLE_MASK_SFT (0x1 << 0)
917#define ACCDET_EINT0_EN_STABLE_ADDR \
918 MT6359_ACCDET_CON19
919#define ACCDET_EINT0_EN_STABLE_SFT 1
920#define ACCDET_EINT0_EN_STABLE_MASK 0x1
921#define ACCDET_EINT0_EN_STABLE_MASK_SFT (0x1 << 1)
922#define ACCDET_EINT0_CMPEN_STABLE_ADDR \
923 MT6359_ACCDET_CON19
924#define ACCDET_EINT0_CMPEN_STABLE_SFT 2
925#define ACCDET_EINT0_CMPEN_STABLE_MASK 0x1
926#define ACCDET_EINT0_CMPEN_STABLE_MASK_SFT (0x1 << 2)
927#define ACCDET_EINT0_CMPMEN_STABLE_ADDR \
928 MT6359_ACCDET_CON19
929#define ACCDET_EINT0_CMPMEN_STABLE_SFT 3
930#define ACCDET_EINT0_CMPMEN_STABLE_MASK 0x1
931#define ACCDET_EINT0_CMPMEN_STABLE_MASK_SFT (0x1 << 3)
932#define ACCDET_EINT0_CTURBO_STABLE_ADDR \
933 MT6359_ACCDET_CON19
934#define ACCDET_EINT0_CTURBO_STABLE_SFT 4
935#define ACCDET_EINT0_CTURBO_STABLE_MASK 0x1
936#define ACCDET_EINT0_CTURBO_STABLE_MASK_SFT (0x1 << 4)
937#define ACCDET_EINT0_CEN_STABLE_ADDR \
938 MT6359_ACCDET_CON19
939#define ACCDET_EINT0_CEN_STABLE_SFT 5
940#define ACCDET_EINT0_CEN_STABLE_MASK 0x1
941#define ACCDET_EINT0_CEN_STABLE_MASK_SFT (0x1 << 5)
942#define ACCDET_EINT1_EN_STABLE_ADDR \
943 MT6359_ACCDET_CON19
944#define ACCDET_EINT1_EN_STABLE_SFT 6
945#define ACCDET_EINT1_EN_STABLE_MASK 0x1
946#define ACCDET_EINT1_EN_STABLE_MASK_SFT (0x1 << 6)
947#define ACCDET_EINT1_CMPEN_STABLE_ADDR \
948 MT6359_ACCDET_CON19
949#define ACCDET_EINT1_CMPEN_STABLE_SFT 7
950#define ACCDET_EINT1_CMPEN_STABLE_MASK 0x1
951#define ACCDET_EINT1_CMPEN_STABLE_MASK_SFT (0x1 << 7)
952#define ACCDET_EINT1_CMPMEN_STABLE_ADDR \
953 MT6359_ACCDET_CON19
954#define ACCDET_EINT1_CMPMEN_STABLE_SFT 8
955#define ACCDET_EINT1_CMPMEN_STABLE_MASK 0x1
956#define ACCDET_EINT1_CMPMEN_STABLE_MASK_SFT (0x1 << 8)
957#define ACCDET_EINT1_CTURBO_STABLE_ADDR \
958 MT6359_ACCDET_CON19
959#define ACCDET_EINT1_CTURBO_STABLE_SFT 9
960#define ACCDET_EINT1_CTURBO_STABLE_MASK 0x1
961#define ACCDET_EINT1_CTURBO_STABLE_MASK_SFT (0x1 << 9)
962#define ACCDET_EINT1_CEN_STABLE_ADDR \
963 MT6359_ACCDET_CON19
964#define ACCDET_EINT1_CEN_STABLE_SFT 10
965#define ACCDET_EINT1_CEN_STABLE_MASK 0x1
966#define ACCDET_EINT1_CEN_STABLE_MASK_SFT (0x1 << 10)
967#define ACCDET_HWMODE_EN_ADDR \
968 MT6359_ACCDET_CON20
969#define ACCDET_HWMODE_EN_SFT 0
970#define ACCDET_HWMODE_EN_MASK 0x1
971#define ACCDET_HWMODE_EN_MASK_SFT (0x1 << 0)
972#define ACCDET_HWMODE_SEL_ADDR \
973 MT6359_ACCDET_CON20
974#define ACCDET_HWMODE_SEL_SFT 1
975#define ACCDET_HWMODE_SEL_MASK 0x3
976#define ACCDET_HWMODE_SEL_MASK_SFT (0x3 << 1)
977#define ACCDET_PLUG_OUT_DETECT_ADDR \
978 MT6359_ACCDET_CON20
979#define ACCDET_PLUG_OUT_DETECT_SFT 3
980#define ACCDET_PLUG_OUT_DETECT_MASK 0x1
981#define ACCDET_PLUG_OUT_DETECT_MASK_SFT (0x1 << 3)
982#define ACCDET_EINT0_REVERSE_ADDR \
983 MT6359_ACCDET_CON20
984#define ACCDET_EINT0_REVERSE_SFT 4
985#define ACCDET_EINT0_REVERSE_MASK 0x1
986#define ACCDET_EINT0_REVERSE_MASK_SFT (0x1 << 4)
987#define ACCDET_EINT1_REVERSE_ADDR \
988 MT6359_ACCDET_CON20
989#define ACCDET_EINT1_REVERSE_SFT 5
990#define ACCDET_EINT1_REVERSE_MASK 0x1
991#define ACCDET_EINT1_REVERSE_MASK_SFT (0x1 << 5)
992#define ACCDET_EINT_HWMODE_EN_ADDR \
993 MT6359_ACCDET_CON20
994#define ACCDET_EINT_HWMODE_EN_SFT 8
995#define ACCDET_EINT_HWMODE_EN_MASK 0x1
996#define ACCDET_EINT_HWMODE_EN_MASK_SFT (0x1 << 8)
997#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_ADDR \
998 MT6359_ACCDET_CON20
999#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_SFT 9
1000#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK 0x1
1001#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK_SFT (0x1 << 9)
1002#define ACCDET_EINT_M_PLUG_IN_EN_ADDR \
1003 MT6359_ACCDET_CON20
1004#define ACCDET_EINT_M_PLUG_IN_EN_SFT 10
1005#define ACCDET_EINT_M_PLUG_IN_EN_MASK 0x1
1006#define ACCDET_EINT_M_PLUG_IN_EN_MASK_SFT (0x1 << 10)
1007#define ACCDET_EINT_M_HWMODE_EN_ADDR \
1008 MT6359_ACCDET_CON20
1009#define ACCDET_EINT_M_HWMODE_EN_SFT 11
1010#define ACCDET_EINT_M_HWMODE_EN_MASK 0x1
1011#define ACCDET_EINT_M_HWMODE_EN_MASK_SFT (0x1 << 11)
1012#define ACCDET_TEST_CMPEN_ADDR \
1013 MT6359_ACCDET_CON21
1014#define ACCDET_TEST_CMPEN_SFT 0
1015#define ACCDET_TEST_CMPEN_MASK 0x1
1016#define ACCDET_TEST_CMPEN_MASK_SFT (0x1 << 0)
1017#define ACCDET_TEST_VTHEN_ADDR \
1018 MT6359_ACCDET_CON21
1019#define ACCDET_TEST_VTHEN_SFT 1
1020#define ACCDET_TEST_VTHEN_MASK 0x1
1021#define ACCDET_TEST_VTHEN_MASK_SFT (0x1 << 1)
1022#define ACCDET_TEST_MBIASEN_ADDR \
1023 MT6359_ACCDET_CON21
1024#define ACCDET_TEST_MBIASEN_SFT 2
1025#define ACCDET_TEST_MBIASEN_MASK 0x1
1026#define ACCDET_TEST_MBIASEN_MASK_SFT (0x1 << 2)
1027#define ACCDET_EINT_TEST_EN_ADDR \
1028 MT6359_ACCDET_CON21
1029#define ACCDET_EINT_TEST_EN_SFT 3
1030#define ACCDET_EINT_TEST_EN_MASK 0x1
1031#define ACCDET_EINT_TEST_EN_MASK_SFT (0x1 << 3)
1032#define ACCDET_EINT_TEST_INVEN_ADDR \
1033 MT6359_ACCDET_CON21
1034#define ACCDET_EINT_TEST_INVEN_SFT 4
1035#define ACCDET_EINT_TEST_INVEN_MASK 0x1
1036#define ACCDET_EINT_TEST_INVEN_MASK_SFT (0x1 << 4)
1037#define ACCDET_EINT_TEST_CMPEN_ADDR \
1038 MT6359_ACCDET_CON21
1039#define ACCDET_EINT_TEST_CMPEN_SFT 5
1040#define ACCDET_EINT_TEST_CMPEN_MASK 0x1
1041#define ACCDET_EINT_TEST_CMPEN_MASK_SFT (0x1 << 5)
1042#define ACCDET_EINT_TEST_CMPMEN_ADDR \
1043 MT6359_ACCDET_CON21
1044#define ACCDET_EINT_TEST_CMPMEN_SFT 6
1045#define ACCDET_EINT_TEST_CMPMEN_MASK 0x1
1046#define ACCDET_EINT_TEST_CMPMEN_MASK_SFT (0x1 << 6)
1047#define ACCDET_EINT_TEST_CTURBO_ADDR \
1048 MT6359_ACCDET_CON21
1049#define ACCDET_EINT_TEST_CTURBO_SFT 7
1050#define ACCDET_EINT_TEST_CTURBO_MASK 0x1
1051#define ACCDET_EINT_TEST_CTURBO_MASK_SFT (0x1 << 7)
1052#define ACCDET_EINT_TEST_CEN_ADDR \
1053 MT6359_ACCDET_CON21
1054#define ACCDET_EINT_TEST_CEN_SFT 8
1055#define ACCDET_EINT_TEST_CEN_MASK 0x1
1056#define ACCDET_EINT_TEST_CEN_MASK_SFT (0x1 << 8)
1057#define ACCDET_TEST_B_ADDR \
1058 MT6359_ACCDET_CON21
1059#define ACCDET_TEST_B_SFT 9
1060#define ACCDET_TEST_B_MASK 0x1
1061#define ACCDET_TEST_B_MASK_SFT (0x1 << 9)
1062#define ACCDET_TEST_A_ADDR \
1063 MT6359_ACCDET_CON21
1064#define ACCDET_TEST_A_SFT 10
1065#define ACCDET_TEST_A_MASK 0x1
1066#define ACCDET_TEST_A_MASK_SFT (0x1 << 10)
1067#define ACCDET_EINT_TEST_CMPOUT_ADDR \
1068 MT6359_ACCDET_CON21
1069#define ACCDET_EINT_TEST_CMPOUT_SFT 11
1070#define ACCDET_EINT_TEST_CMPOUT_MASK 0x1
1071#define ACCDET_EINT_TEST_CMPOUT_MASK_SFT (0x1 << 11)
1072#define ACCDET_EINT_TEST_CMPMOUT_ADDR \
1073 MT6359_ACCDET_CON21
1074#define ACCDET_EINT_TEST_CMPMOUT_SFT 12
1075#define ACCDET_EINT_TEST_CMPMOUT_MASK 0x1
1076#define ACCDET_EINT_TEST_CMPMOUT_MASK_SFT (0x1 << 12)
1077#define ACCDET_EINT_TEST_INVOUT_ADDR \
1078 MT6359_ACCDET_CON21
1079#define ACCDET_EINT_TEST_INVOUT_SFT 13
1080#define ACCDET_EINT_TEST_INVOUT_MASK 0x1
1081#define ACCDET_EINT_TEST_INVOUT_MASK_SFT (0x1 << 13)
1082#define ACCDET_CMPEN_SEL_ADDR \
1083 MT6359_ACCDET_CON22
1084#define ACCDET_CMPEN_SEL_SFT 0
1085#define ACCDET_CMPEN_SEL_MASK 0x1
1086#define ACCDET_CMPEN_SEL_MASK_SFT (0x1 << 0)
1087#define ACCDET_VTHEN_SEL_ADDR \
1088 MT6359_ACCDET_CON22
1089#define ACCDET_VTHEN_SEL_SFT 1
1090#define ACCDET_VTHEN_SEL_MASK 0x1
1091#define ACCDET_VTHEN_SEL_MASK_SFT (0x1 << 1)
1092#define ACCDET_MBIASEN_SEL_ADDR \
1093 MT6359_ACCDET_CON22
1094#define ACCDET_MBIASEN_SEL_SFT 2
1095#define ACCDET_MBIASEN_SEL_MASK 0x1
1096#define ACCDET_MBIASEN_SEL_MASK_SFT (0x1 << 2)
1097#define ACCDET_EINT_EN_SEL_ADDR \
1098 MT6359_ACCDET_CON22
1099#define ACCDET_EINT_EN_SEL_SFT 3
1100#define ACCDET_EINT_EN_SEL_MASK 0x1
1101#define ACCDET_EINT_EN_SEL_MASK_SFT (0x1 << 3)
1102#define ACCDET_EINT_INVEN_SEL_ADDR \
1103 MT6359_ACCDET_CON22
1104#define ACCDET_EINT_INVEN_SEL_SFT 4
1105#define ACCDET_EINT_INVEN_SEL_MASK 0x1
1106#define ACCDET_EINT_INVEN_SEL_MASK_SFT (0x1 << 4)
1107#define ACCDET_EINT_CMPEN_SEL_ADDR \
1108 MT6359_ACCDET_CON22
1109#define ACCDET_EINT_CMPEN_SEL_SFT 5
1110#define ACCDET_EINT_CMPEN_SEL_MASK 0x1
1111#define ACCDET_EINT_CMPEN_SEL_MASK_SFT (0x1 << 5)
1112#define ACCDET_EINT_CMPMEN_SEL_ADDR \
1113 MT6359_ACCDET_CON22
1114#define ACCDET_EINT_CMPMEN_SEL_SFT 6
1115#define ACCDET_EINT_CMPMEN_SEL_MASK 0x1
1116#define ACCDET_EINT_CMPMEN_SEL_MASK_SFT (0x1 << 6)
1117#define ACCDET_EINT_CTURBO_SEL_ADDR \
1118 MT6359_ACCDET_CON22
1119#define ACCDET_EINT_CTURBO_SEL_SFT 7
1120#define ACCDET_EINT_CTURBO_SEL_MASK 0x1
1121#define ACCDET_EINT_CTURBO_SEL_MASK_SFT (0x1 << 7)
1122#define ACCDET_B_SEL_ADDR \
1123 MT6359_ACCDET_CON22
1124#define ACCDET_B_SEL_SFT 9
1125#define ACCDET_B_SEL_MASK 0x1
1126#define ACCDET_B_SEL_MASK_SFT (0x1 << 9)
1127#define ACCDET_A_SEL_ADDR \
1128 MT6359_ACCDET_CON22
1129#define ACCDET_A_SEL_SFT 10
1130#define ACCDET_A_SEL_MASK 0x1
1131#define ACCDET_A_SEL_MASK_SFT (0x1 << 10)
1132#define ACCDET_EINT_CMPOUT_SEL_ADDR \
1133 MT6359_ACCDET_CON22
1134#define ACCDET_EINT_CMPOUT_SEL_SFT 11
1135#define ACCDET_EINT_CMPOUT_SEL_MASK 0x1
1136#define ACCDET_EINT_CMPOUT_SEL_MASK_SFT (0x1 << 11)
1137#define ACCDET_EINT_CMPMOUT_SEL_ADDR \
1138 MT6359_ACCDET_CON22
1139#define ACCDET_EINT_CMPMOUT_SEL_SFT 12
1140#define ACCDET_EINT_CMPMOUT_SEL_MASK 0x1
1141#define ACCDET_EINT_CMPMOUT_SEL_MASK_SFT (0x1 << 12)
1142#define ACCDET_EINT_INVOUT_SEL_ADDR \
1143 MT6359_ACCDET_CON22
1144#define ACCDET_EINT_INVOUT_SEL_SFT 13
1145#define ACCDET_EINT_INVOUT_SEL_MASK 0x1
1146#define ACCDET_EINT_INVOUT_SEL_MASK_SFT (0x1 << 13)
1147#define ACCDET_CMPEN_SW_ADDR \
1148 MT6359_ACCDET_CON23
1149#define ACCDET_CMPEN_SW_SFT 0
1150#define ACCDET_CMPEN_SW_MASK 0x1
1151#define ACCDET_CMPEN_SW_MASK_SFT (0x1 << 0)
1152#define ACCDET_VTHEN_SW_ADDR \
1153 MT6359_ACCDET_CON23
1154#define ACCDET_VTHEN_SW_SFT 1
1155#define ACCDET_VTHEN_SW_MASK 0x1
1156#define ACCDET_VTHEN_SW_MASK_SFT (0x1 << 1)
1157#define ACCDET_MBIASEN_SW_ADDR \
1158 MT6359_ACCDET_CON23
1159#define ACCDET_MBIASEN_SW_SFT 2
1160#define ACCDET_MBIASEN_SW_MASK 0x1
1161#define ACCDET_MBIASEN_SW_MASK_SFT (0x1 << 2)
1162#define ACCDET_EINT0_EN_SW_ADDR \
1163 MT6359_ACCDET_CON23
1164#define ACCDET_EINT0_EN_SW_SFT 3
1165#define ACCDET_EINT0_EN_SW_MASK 0x1
1166#define ACCDET_EINT0_EN_SW_MASK_SFT (0x1 << 3)
1167#define ACCDET_EINT0_INVEN_SW_ADDR \
1168 MT6359_ACCDET_CON23
1169#define ACCDET_EINT0_INVEN_SW_SFT 4
1170#define ACCDET_EINT0_INVEN_SW_MASK 0x1
1171#define ACCDET_EINT0_INVEN_SW_MASK_SFT (0x1 << 4)
1172#define ACCDET_EINT0_CMPEN_SW_ADDR \
1173 MT6359_ACCDET_CON23
1174#define ACCDET_EINT0_CMPEN_SW_SFT 5
1175#define ACCDET_EINT0_CMPEN_SW_MASK 0x1
1176#define ACCDET_EINT0_CMPEN_SW_MASK_SFT (0x1 << 5)
1177#define ACCDET_EINT0_CMPMEN_SW_ADDR \
1178 MT6359_ACCDET_CON23
1179#define ACCDET_EINT0_CMPMEN_SW_SFT 6
1180#define ACCDET_EINT0_CMPMEN_SW_MASK 0x1
1181#define ACCDET_EINT0_CMPMEN_SW_MASK_SFT (0x1 << 6)
1182#define ACCDET_EINT0_CTURBO_SW_ADDR \
1183 MT6359_ACCDET_CON23
1184#define ACCDET_EINT0_CTURBO_SW_SFT 7
1185#define ACCDET_EINT0_CTURBO_SW_MASK 0x1
1186#define ACCDET_EINT0_CTURBO_SW_MASK_SFT (0x1 << 7)
1187#define ACCDET_EINT1_EN_SW_ADDR \
1188 MT6359_ACCDET_CON23
1189#define ACCDET_EINT1_EN_SW_SFT 8
1190#define ACCDET_EINT1_EN_SW_MASK 0x1
1191#define ACCDET_EINT1_EN_SW_MASK_SFT (0x1 << 8)
1192#define ACCDET_EINT1_INVEN_SW_ADDR \
1193 MT6359_ACCDET_CON23
1194#define ACCDET_EINT1_INVEN_SW_SFT 9
1195#define ACCDET_EINT1_INVEN_SW_MASK 0x1
1196#define ACCDET_EINT1_INVEN_SW_MASK_SFT (0x1 << 9)
1197#define ACCDET_EINT1_CMPEN_SW_ADDR \
1198 MT6359_ACCDET_CON23
1199#define ACCDET_EINT1_CMPEN_SW_SFT 10
1200#define ACCDET_EINT1_CMPEN_SW_MASK 0x1
1201#define ACCDET_EINT1_CMPEN_SW_MASK_SFT (0x1 << 10)
1202#define ACCDET_EINT1_CMPMEN_SW_ADDR \
1203 MT6359_ACCDET_CON23
1204#define ACCDET_EINT1_CMPMEN_SW_SFT 11
1205#define ACCDET_EINT1_CMPMEN_SW_MASK 0x1
1206#define ACCDET_EINT1_CMPMEN_SW_MASK_SFT (0x1 << 11)
1207#define ACCDET_EINT1_CTURBO_SW_ADDR \
1208 MT6359_ACCDET_CON23
1209#define ACCDET_EINT1_CTURBO_SW_SFT 12
1210#define ACCDET_EINT1_CTURBO_SW_MASK 0x1
1211#define ACCDET_EINT1_CTURBO_SW_MASK_SFT (0x1 << 12)
1212#define ACCDET_B_SW_ADDR \
1213 MT6359_ACCDET_CON24
1214#define ACCDET_B_SW_SFT 0
1215#define ACCDET_B_SW_MASK 0x1
1216#define ACCDET_B_SW_MASK_SFT (0x1 << 0)
1217#define ACCDET_A_SW_ADDR \
1218 MT6359_ACCDET_CON24
1219#define ACCDET_A_SW_SFT 1
1220#define ACCDET_A_SW_MASK 0x1
1221#define ACCDET_A_SW_MASK_SFT (0x1 << 1)
1222#define ACCDET_EINT0_CMPOUT_SW_ADDR \
1223 MT6359_ACCDET_CON24
1224#define ACCDET_EINT0_CMPOUT_SW_SFT 2
1225#define ACCDET_EINT0_CMPOUT_SW_MASK 0x1
1226#define ACCDET_EINT0_CMPOUT_SW_MASK_SFT (0x1 << 2)
1227#define ACCDET_EINT0_CMPMOUT_SW_ADDR \
1228 MT6359_ACCDET_CON24
1229#define ACCDET_EINT0_CMPMOUT_SW_SFT 3
1230#define ACCDET_EINT0_CMPMOUT_SW_MASK 0x1
1231#define ACCDET_EINT0_CMPMOUT_SW_MASK_SFT (0x1 << 3)
1232#define ACCDET_EINT0_INVOUT_SW_ADDR \
1233 MT6359_ACCDET_CON24
1234#define ACCDET_EINT0_INVOUT_SW_SFT 4
1235#define ACCDET_EINT0_INVOUT_SW_MASK 0x1
1236#define ACCDET_EINT0_INVOUT_SW_MASK_SFT (0x1 << 4)
1237#define ACCDET_EINT1_CMPOUT_SW_ADDR \
1238 MT6359_ACCDET_CON24
1239#define ACCDET_EINT1_CMPOUT_SW_SFT 5
1240#define ACCDET_EINT1_CMPOUT_SW_MASK 0x1
1241#define ACCDET_EINT1_CMPOUT_SW_MASK_SFT (0x1 << 5)
1242#define ACCDET_EINT1_CMPMOUT_SW_ADDR \
1243 MT6359_ACCDET_CON24
1244#define ACCDET_EINT1_CMPMOUT_SW_SFT 6
1245#define ACCDET_EINT1_CMPMOUT_SW_MASK 0x1
1246#define ACCDET_EINT1_CMPMOUT_SW_MASK_SFT (0x1 << 6)
1247#define ACCDET_EINT1_INVOUT_SW_ADDR \
1248 MT6359_ACCDET_CON24
1249#define ACCDET_EINT1_INVOUT_SW_SFT 7
1250#define ACCDET_EINT1_INVOUT_SW_MASK 0x1
1251#define ACCDET_EINT1_INVOUT_SW_MASK_SFT (0x1 << 7)
1252#define AD_AUDACCDETCMPOB_ADDR \
1253 MT6359_ACCDET_CON25
1254#define AD_AUDACCDETCMPOB_SFT 0
1255#define AD_AUDACCDETCMPOB_MASK 0x1
1256#define AD_AUDACCDETCMPOB_MASK_SFT (0x1 << 0)
1257#define AD_AUDACCDETCMPOA_ADDR \
1258 MT6359_ACCDET_CON25
1259#define AD_AUDACCDETCMPOA_SFT 1
1260#define AD_AUDACCDETCMPOA_MASK 0x1
1261#define AD_AUDACCDETCMPOA_MASK_SFT (0x1 << 1)
1262#define ACCDET_CUR_IN_ADDR \
1263 MT6359_ACCDET_CON25
1264#define ACCDET_CUR_IN_SFT 2
1265#define ACCDET_CUR_IN_MASK 0x3
1266#define ACCDET_CUR_IN_MASK_SFT (0x3 << 2)
1267#define ACCDET_SAM_IN_ADDR \
1268 MT6359_ACCDET_CON25
1269#define ACCDET_SAM_IN_SFT 4
1270#define ACCDET_SAM_IN_MASK 0x3
1271#define ACCDET_SAM_IN_MASK_SFT (0x3 << 4)
1272#define ACCDET_MEM_IN_ADDR \
1273 MT6359_ACCDET_CON25
1274#define ACCDET_MEM_IN_SFT 6
1275#define ACCDET_MEM_IN_MASK 0x3
1276#define ACCDET_MEM_IN_MASK_SFT (0x3 << 6)
1277#define ACCDET_STATE_ADDR \
1278 MT6359_ACCDET_CON25
1279#define ACCDET_STATE_SFT 8
1280#define ACCDET_STATE_MASK 0x7
1281#define ACCDET_STATE_MASK_SFT (0x7 << 8)
1282#define DA_AUDACCDETMBIASCLK_ADDR \
1283 MT6359_ACCDET_CON25
1284#define DA_AUDACCDETMBIASCLK_SFT 12
1285#define DA_AUDACCDETMBIASCLK_MASK 0x1
1286#define DA_AUDACCDETMBIASCLK_MASK_SFT (0x1 << 12)
1287#define DA_AUDACCDETVTHCLK_ADDR \
1288 MT6359_ACCDET_CON25
1289#define DA_AUDACCDETVTHCLK_SFT 13
1290#define DA_AUDACCDETVTHCLK_MASK 0x1
1291#define DA_AUDACCDETVTHCLK_MASK_SFT (0x1 << 13)
1292#define DA_AUDACCDETCMPCLK_ADDR \
1293 MT6359_ACCDET_CON25
1294#define DA_AUDACCDETCMPCLK_SFT 14
1295#define DA_AUDACCDETCMPCLK_MASK 0x1
1296#define DA_AUDACCDETCMPCLK_MASK_SFT (0x1 << 14)
1297#define DA_AUDACCDETAUXADCSWCTRL_ADDR \
1298 MT6359_ACCDET_CON25
1299#define DA_AUDACCDETAUXADCSWCTRL_SFT 15
1300#define DA_AUDACCDETAUXADCSWCTRL_MASK 0x1
1301#define DA_AUDACCDETAUXADCSWCTRL_MASK_SFT (0x1 << 15)
1302#define AD_EINT0CMPMOUT_ADDR \
1303 MT6359_ACCDET_CON26
1304#define AD_EINT0CMPMOUT_SFT 0
1305#define AD_EINT0CMPMOUT_MASK 0x1
1306#define AD_EINT0CMPMOUT_MASK_SFT (0x1 << 0)
1307#define AD_EINT0CMPOUT_ADDR \
1308 MT6359_ACCDET_CON26
1309#define AD_EINT0CMPOUT_SFT 1
1310#define AD_EINT0CMPOUT_MASK 0x1
1311#define AD_EINT0CMPOUT_MASK_SFT (0x1 << 1)
1312#define ACCDET_EINT0_CUR_IN_ADDR \
1313 MT6359_ACCDET_CON26
1314#define ACCDET_EINT0_CUR_IN_SFT 2
1315#define ACCDET_EINT0_CUR_IN_MASK 0x3
1316#define ACCDET_EINT0_CUR_IN_MASK_SFT (0x3 << 2)
1317#define ACCDET_EINT0_SAM_IN_ADDR \
1318 MT6359_ACCDET_CON26
1319#define ACCDET_EINT0_SAM_IN_SFT 4
1320#define ACCDET_EINT0_SAM_IN_MASK 0x3
1321#define ACCDET_EINT0_SAM_IN_MASK_SFT (0x3 << 4)
1322#define ACCDET_EINT0_MEM_IN_ADDR \
1323 MT6359_ACCDET_CON26
1324#define ACCDET_EINT0_MEM_IN_SFT 6
1325#define ACCDET_EINT0_MEM_IN_MASK 0x3
1326#define ACCDET_EINT0_MEM_IN_MASK_SFT (0x3 << 6)
1327#define ACCDET_EINT0_STATE_ADDR \
1328 MT6359_ACCDET_CON26
1329#define ACCDET_EINT0_STATE_SFT 8
1330#define ACCDET_EINT0_STATE_MASK 0x7
1331#define ACCDET_EINT0_STATE_MASK_SFT (0x7 << 8)
1332#define DA_EINT0CMPEN_ADDR \
1333 MT6359_ACCDET_CON26
1334#define DA_EINT0CMPEN_SFT 13
1335#define DA_EINT0CMPEN_MASK 0x1
1336#define DA_EINT0CMPEN_MASK_SFT (0x1 << 13)
1337#define DA_EINT0CMPMEN_ADDR \
1338 MT6359_ACCDET_CON26
1339#define DA_EINT0CMPMEN_SFT 14
1340#define DA_EINT0CMPMEN_MASK 0x1
1341#define DA_EINT0CMPMEN_MASK_SFT (0x1 << 14)
1342#define DA_EINT0CTURBO_ADDR \
1343 MT6359_ACCDET_CON26
1344#define DA_EINT0CTURBO_SFT 15
1345#define DA_EINT0CTURBO_MASK 0x1
1346#define DA_EINT0CTURBO_MASK_SFT (0x1 << 15)
1347#define AD_EINT1CMPMOUT_ADDR \
1348 MT6359_ACCDET_CON27
1349#define AD_EINT1CMPMOUT_SFT 0
1350#define AD_EINT1CMPMOUT_MASK 0x1
1351#define AD_EINT1CMPMOUT_MASK_SFT (0x1 << 0)
1352#define AD_EINT1CMPOUT_ADDR \
1353 MT6359_ACCDET_CON27
1354#define AD_EINT1CMPOUT_SFT 1
1355#define AD_EINT1CMPOUT_MASK 0x1
1356#define AD_EINT1CMPOUT_MASK_SFT (0x1 << 1)
1357#define ACCDET_EINT1_CUR_IN_ADDR \
1358 MT6359_ACCDET_CON27
1359#define ACCDET_EINT1_CUR_IN_SFT 2
1360#define ACCDET_EINT1_CUR_IN_MASK 0x3
1361#define ACCDET_EINT1_CUR_IN_MASK_SFT (0x3 << 2)
1362#define ACCDET_EINT1_SAM_IN_ADDR \
1363 MT6359_ACCDET_CON27
1364#define ACCDET_EINT1_SAM_IN_SFT 4
1365#define ACCDET_EINT1_SAM_IN_MASK 0x3
1366#define ACCDET_EINT1_SAM_IN_MASK_SFT (0x3 << 4)
1367#define ACCDET_EINT1_MEM_IN_ADDR \
1368 MT6359_ACCDET_CON27
1369#define ACCDET_EINT1_MEM_IN_SFT 6
1370#define ACCDET_EINT1_MEM_IN_MASK 0x3
1371#define ACCDET_EINT1_MEM_IN_MASK_SFT (0x3 << 6)
1372#define ACCDET_EINT1_STATE_ADDR \
1373 MT6359_ACCDET_CON27
1374#define ACCDET_EINT1_STATE_SFT 8
1375#define ACCDET_EINT1_STATE_MASK 0x7
1376#define ACCDET_EINT1_STATE_MASK_SFT (0x7 << 8)
1377#define DA_EINT1CMPEN_ADDR \
1378 MT6359_ACCDET_CON27
1379#define DA_EINT1CMPEN_SFT 13
1380#define DA_EINT1CMPEN_MASK 0x1
1381#define DA_EINT1CMPEN_MASK_SFT (0x1 << 13)
1382#define DA_EINT1CMPMEN_ADDR \
1383 MT6359_ACCDET_CON27
1384#define DA_EINT1CMPMEN_SFT 14
1385#define DA_EINT1CMPMEN_MASK 0x1
1386#define DA_EINT1CMPMEN_MASK_SFT (0x1 << 14)
1387#define DA_EINT1CTURBO_ADDR \
1388 MT6359_ACCDET_CON27
1389#define DA_EINT1CTURBO_SFT 15
1390#define DA_EINT1CTURBO_MASK 0x1
1391#define DA_EINT1CTURBO_MASK_SFT (0x1 << 15)
1392#define AD_EINT0INVOUT_ADDR \
1393 MT6359_ACCDET_CON28
1394#define AD_EINT0INVOUT_SFT 0
1395#define AD_EINT0INVOUT_MASK 0x1
1396#define AD_EINT0INVOUT_MASK_SFT (0x1 << 0)
1397#define ACCDET_EINT0_INVERTER_CUR_IN_ADDR \
1398 MT6359_ACCDET_CON28
1399#define ACCDET_EINT0_INVERTER_CUR_IN_SFT 1
1400#define ACCDET_EINT0_INVERTER_CUR_IN_MASK 0x1
1401#define ACCDET_EINT0_INVERTER_CUR_IN_MASK_SFT (0x1 << 1)
1402#define ACCDET_EINT0_INVERTER_SAM_IN_ADDR \
1403 MT6359_ACCDET_CON28
1404#define ACCDET_EINT0_INVERTER_SAM_IN_SFT 2
1405#define ACCDET_EINT0_INVERTER_SAM_IN_MASK 0x1
1406#define ACCDET_EINT0_INVERTER_SAM_IN_MASK_SFT (0x1 << 2)
1407#define ACCDET_EINT0_INVERTER_MEM_IN_ADDR \
1408 MT6359_ACCDET_CON28
1409#define ACCDET_EINT0_INVERTER_MEM_IN_SFT 3
1410#define ACCDET_EINT0_INVERTER_MEM_IN_MASK 0x1
1411#define ACCDET_EINT0_INVERTER_MEM_IN_MASK_SFT (0x1 << 3)
1412#define ACCDET_EINT0_INVERTER_STATE_ADDR \
1413 MT6359_ACCDET_CON28
1414#define ACCDET_EINT0_INVERTER_STATE_SFT 8
1415#define ACCDET_EINT0_INVERTER_STATE_MASK 0x7
1416#define ACCDET_EINT0_INVERTER_STATE_MASK_SFT (0x7 << 8)
1417#define DA_EINT0EN_ADDR \
1418 MT6359_ACCDET_CON28
1419#define DA_EINT0EN_SFT 12
1420#define DA_EINT0EN_MASK 0x1
1421#define DA_EINT0EN_MASK_SFT (0x1 << 12)
1422#define DA_EINT0INVEN_ADDR \
1423 MT6359_ACCDET_CON28
1424#define DA_EINT0INVEN_SFT 13
1425#define DA_EINT0INVEN_MASK 0x1
1426#define DA_EINT0INVEN_MASK_SFT (0x1 << 13)
1427#define DA_EINT0CEN_ADDR \
1428 MT6359_ACCDET_CON28
1429#define DA_EINT0CEN_SFT 14
1430#define DA_EINT0CEN_MASK 0x1
1431#define DA_EINT0CEN_MASK_SFT (0x1 << 14)
1432#define AD_EINT1INVOUT_ADDR \
1433 MT6359_ACCDET_CON29
1434#define AD_EINT1INVOUT_SFT 0
1435#define AD_EINT1INVOUT_MASK 0x1
1436#define AD_EINT1INVOUT_MASK_SFT (0x1 << 0)
1437#define ACCDET_EINT1_INVERTER_CUR_IN_ADDR \
1438 MT6359_ACCDET_CON29
1439#define ACCDET_EINT1_INVERTER_CUR_IN_SFT 1
1440#define ACCDET_EINT1_INVERTER_CUR_IN_MASK 0x1
1441#define ACCDET_EINT1_INVERTER_CUR_IN_MASK_SFT (0x1 << 1)
1442#define ACCDET_EINT1_INVERTER_SAM_IN_ADDR \
1443 MT6359_ACCDET_CON29
1444#define ACCDET_EINT1_INVERTER_SAM_IN_SFT 2
1445#define ACCDET_EINT1_INVERTER_SAM_IN_MASK 0x1
1446#define ACCDET_EINT1_INVERTER_SAM_IN_MASK_SFT (0x1 << 2)
1447#define ACCDET_EINT1_INVERTER_MEM_IN_ADDR \
1448 MT6359_ACCDET_CON29
1449#define ACCDET_EINT1_INVERTER_MEM_IN_SFT 3
1450#define ACCDET_EINT1_INVERTER_MEM_IN_MASK 0x1
1451#define ACCDET_EINT1_INVERTER_MEM_IN_MASK_SFT (0x1 << 3)
1452#define ACCDET_EINT1_INVERTER_STATE_ADDR \
1453 MT6359_ACCDET_CON29
1454#define ACCDET_EINT1_INVERTER_STATE_SFT 8
1455#define ACCDET_EINT1_INVERTER_STATE_MASK 0x7
1456#define ACCDET_EINT1_INVERTER_STATE_MASK_SFT (0x7 << 8)
1457#define DA_EINT1EN_ADDR \
1458 MT6359_ACCDET_CON29
1459#define DA_EINT1EN_SFT 12
1460#define DA_EINT1EN_MASK 0x1
1461#define DA_EINT1EN_MASK_SFT (0x1 << 12)
1462#define DA_EINT1INVEN_ADDR \
1463 MT6359_ACCDET_CON29
1464#define DA_EINT1INVEN_SFT 13
1465#define DA_EINT1INVEN_MASK 0x1
1466#define DA_EINT1INVEN_MASK_SFT (0x1 << 13)
1467#define DA_EINT1CEN_ADDR \
1468 MT6359_ACCDET_CON29
1469#define DA_EINT1CEN_SFT 14
1470#define DA_EINT1CEN_MASK 0x1
1471#define DA_EINT1CEN_MASK_SFT (0x1 << 14)
1472#define ACCDET_EN_ADDR \
1473 MT6359_ACCDET_CON30
1474#define ACCDET_EN_SFT 0
1475#define ACCDET_EN_MASK 0x1
1476#define ACCDET_EN_MASK_SFT (0x1 << 0)
1477#define ACCDET_EINT0_EN_ADDR \
1478 MT6359_ACCDET_CON30
1479#define ACCDET_EINT0_EN_SFT 1
1480#define ACCDET_EINT0_EN_MASK 0x1
1481#define ACCDET_EINT0_EN_MASK_SFT (0x1 << 1)
1482#define ACCDET_EINT1_EN_ADDR \
1483 MT6359_ACCDET_CON30
1484#define ACCDET_EINT1_EN_SFT 2
1485#define ACCDET_EINT1_EN_MASK 0x1
1486#define ACCDET_EINT1_EN_MASK_SFT (0x1 << 2)
1487#define ACCDET_EINT0_M_EN_ADDR \
1488 MT6359_ACCDET_CON30
1489#define ACCDET_EINT0_M_EN_SFT 3
1490#define ACCDET_EINT0_M_EN_MASK 0x1
1491#define ACCDET_EINT0_M_EN_MASK_SFT (0x1 << 3)
1492#define ACCDET_EINT0_DETECT_MOISTURE_ADDR \
1493 MT6359_ACCDET_CON30
1494#define ACCDET_EINT0_DETECT_MOISTURE_SFT 4
1495#define ACCDET_EINT0_DETECT_MOISTURE_MASK 0x1
1496#define ACCDET_EINT0_DETECT_MOISTURE_MASK_SFT (0x1 << 4)
1497#define ACCDET_EINT0_PLUG_IN_ADDR \
1498 MT6359_ACCDET_CON30
1499#define ACCDET_EINT0_PLUG_IN_SFT 5
1500#define ACCDET_EINT0_PLUG_IN_MASK 0x1
1501#define ACCDET_EINT0_PLUG_IN_MASK_SFT (0x1 << 5)
1502#define ACCDET_EINT0_M_PLUG_IN_ADDR \
1503 MT6359_ACCDET_CON30
1504#define ACCDET_EINT0_M_PLUG_IN_SFT 6
1505#define ACCDET_EINT0_M_PLUG_IN_MASK 0x1
1506#define ACCDET_EINT0_M_PLUG_IN_MASK_SFT (0x1 << 6)
1507#define ACCDET_EINT1_M_EN_ADDR \
1508 MT6359_ACCDET_CON30
1509#define ACCDET_EINT1_M_EN_SFT 7
1510#define ACCDET_EINT1_M_EN_MASK 0x1
1511#define ACCDET_EINT1_M_EN_MASK_SFT (0x1 << 7)
1512#define ACCDET_EINT1_DETECT_MOISTURE_ADDR \
1513 MT6359_ACCDET_CON30
1514#define ACCDET_EINT1_DETECT_MOISTURE_SFT 8
1515#define ACCDET_EINT1_DETECT_MOISTURE_MASK 0x1
1516#define ACCDET_EINT1_DETECT_MOISTURE_MASK_SFT (0x1 << 8)
1517#define ACCDET_EINT1_PLUG_IN_ADDR \
1518 MT6359_ACCDET_CON30
1519#define ACCDET_EINT1_PLUG_IN_SFT 9
1520#define ACCDET_EINT1_PLUG_IN_MASK 0x1
1521#define ACCDET_EINT1_PLUG_IN_MASK_SFT (0x1 << 9)
1522#define ACCDET_EINT1_M_PLUG_IN_ADDR \
1523 MT6359_ACCDET_CON30
1524#define ACCDET_EINT1_M_PLUG_IN_SFT 10
1525#define ACCDET_EINT1_M_PLUG_IN_MASK 0x1
1526#define ACCDET_EINT1_M_PLUG_IN_MASK_SFT (0x1 << 10)
1527#define ACCDET_CUR_DEB_ADDR \
1528 MT6359_ACCDET_CON31
1529#define ACCDET_CUR_DEB_SFT 0
1530#define ACCDET_CUR_DEB_MASK 0xFFFF
1531#define ACCDET_CUR_DEB_MASK_SFT (0xFFFF << 0)
1532#define ACCDET_EINT0_CUR_DEB_ADDR \
1533 MT6359_ACCDET_CON32
1534#define ACCDET_EINT0_CUR_DEB_SFT 0
1535#define ACCDET_EINT0_CUR_DEB_MASK 0x7FFF
1536#define ACCDET_EINT0_CUR_DEB_MASK_SFT (0x7FFF << 0)
1537#define ACCDET_EINT1_CUR_DEB_ADDR \
1538 MT6359_ACCDET_CON33
1539#define ACCDET_EINT1_CUR_DEB_SFT 0
1540#define ACCDET_EINT1_CUR_DEB_MASK 0x7FFF
1541#define ACCDET_EINT1_CUR_DEB_MASK_SFT (0x7FFF << 0)
1542#define ACCDET_EINT0_INVERTER_CUR_DEB_ADDR \
1543 MT6359_ACCDET_CON34
1544#define ACCDET_EINT0_INVERTER_CUR_DEB_SFT 0
1545#define ACCDET_EINT0_INVERTER_CUR_DEB_MASK 0x7FFF
1546#define ACCDET_EINT0_INVERTER_CUR_DEB_MASK_SFT (0x7FFF << 0)
1547#define ACCDET_EINT1_INVERTER_CUR_DEB_ADDR \
1548 MT6359_ACCDET_CON35
1549#define ACCDET_EINT1_INVERTER_CUR_DEB_SFT 0
1550#define ACCDET_EINT1_INVERTER_CUR_DEB_MASK 0x7FFF
1551#define ACCDET_EINT1_INVERTER_CUR_DEB_MASK_SFT (0x7FFF << 0)
1552#define AD_AUDACCDETCMPOB_MON_ADDR \
1553 MT6359_ACCDET_CON36
1554#define AD_AUDACCDETCMPOB_MON_SFT 0
1555#define AD_AUDACCDETCMPOB_MON_MASK 0x1
1556#define AD_AUDACCDETCMPOB_MON_MASK_SFT (0x1 << 0)
1557#define AD_AUDACCDETCMPOA_MON_ADDR \
1558 MT6359_ACCDET_CON36
1559#define AD_AUDACCDETCMPOA_MON_SFT 1
1560#define AD_AUDACCDETCMPOA_MON_MASK 0x1
1561#define AD_AUDACCDETCMPOA_MON_MASK_SFT (0x1 << 1)
1562#define AD_EINT0CMPMOUT_MON_ADDR \
1563 MT6359_ACCDET_CON36
1564#define AD_EINT0CMPMOUT_MON_SFT 2
1565#define AD_EINT0CMPMOUT_MON_MASK 0x1
1566#define AD_EINT0CMPMOUT_MON_MASK_SFT (0x1 << 2)
1567#define AD_EINT0CMPOUT_MON_ADDR \
1568 MT6359_ACCDET_CON36
1569#define AD_EINT0CMPOUT_MON_SFT 3
1570#define AD_EINT0CMPOUT_MON_MASK 0x1
1571#define AD_EINT0CMPOUT_MON_MASK_SFT (0x1 << 3)
1572#define AD_EINT0INVOUT_MON_ADDR \
1573 MT6359_ACCDET_CON36
1574#define AD_EINT0INVOUT_MON_SFT 4
1575#define AD_EINT0INVOUT_MON_MASK 0x1
1576#define AD_EINT0INVOUT_MON_MASK_SFT (0x1 << 4)
1577#define AD_EINT1CMPMOUT_MON_ADDR \
1578 MT6359_ACCDET_CON36
1579#define AD_EINT1CMPMOUT_MON_SFT 5
1580#define AD_EINT1CMPMOUT_MON_MASK 0x1
1581#define AD_EINT1CMPMOUT_MON_MASK_SFT (0x1 << 5)
1582#define AD_EINT1CMPOUT_MON_ADDR \
1583 MT6359_ACCDET_CON36
1584#define AD_EINT1CMPOUT_MON_SFT 6
1585#define AD_EINT1CMPOUT_MON_MASK 0x1
1586#define AD_EINT1CMPOUT_MON_MASK_SFT (0x1 << 6)
1587#define AD_EINT1INVOUT_MON_ADDR \
1588 MT6359_ACCDET_CON36
1589#define AD_EINT1INVOUT_MON_SFT 7
1590#define AD_EINT1INVOUT_MON_MASK 0x1
1591#define AD_EINT1INVOUT_MON_MASK_SFT (0x1 << 7)
1592#define DA_AUDACCDETCMPCLK_MON_ADDR \
1593 MT6359_ACCDET_CON37
1594#define DA_AUDACCDETCMPCLK_MON_SFT 0
1595#define DA_AUDACCDETCMPCLK_MON_MASK 0x1
1596#define DA_AUDACCDETCMPCLK_MON_MASK_SFT (0x1 << 0)
1597#define DA_AUDACCDETVTHCLK_MON_ADDR \
1598 MT6359_ACCDET_CON37
1599#define DA_AUDACCDETVTHCLK_MON_SFT 1
1600#define DA_AUDACCDETVTHCLK_MON_MASK 0x1
1601#define DA_AUDACCDETVTHCLK_MON_MASK_SFT (0x1 << 1)
1602#define DA_AUDACCDETMBIASCLK_MON_ADDR \
1603 MT6359_ACCDET_CON37
1604#define DA_AUDACCDETMBIASCLK_MON_SFT 2
1605#define DA_AUDACCDETMBIASCLK_MON_MASK 0x1
1606#define DA_AUDACCDETMBIASCLK_MON_MASK_SFT (0x1 << 2)
1607#define DA_AUDACCDETAUXADCSWCTRL_MON_ADDR \
1608 MT6359_ACCDET_CON37
1609#define DA_AUDACCDETAUXADCSWCTRL_MON_SFT 3
1610#define DA_AUDACCDETAUXADCSWCTRL_MON_MASK 0x1
1611#define DA_AUDACCDETAUXADCSWCTRL_MON_MASK_SFT (0x1 << 3)
1612#define DA_EINT0CTURBO_MON_ADDR \
1613 MT6359_ACCDET_CON38
1614#define DA_EINT0CTURBO_MON_SFT 0
1615#define DA_EINT0CTURBO_MON_MASK 0x1
1616#define DA_EINT0CTURBO_MON_MASK_SFT (0x1 << 0)
1617#define DA_EINT0CMPMEN_MON_ADDR \
1618 MT6359_ACCDET_CON38
1619#define DA_EINT0CMPMEN_MON_SFT 1
1620#define DA_EINT0CMPMEN_MON_MASK 0x1
1621#define DA_EINT0CMPMEN_MON_MASK_SFT (0x1 << 1)
1622#define DA_EINT0CMPEN_MON_ADDR \
1623 MT6359_ACCDET_CON38
1624#define DA_EINT0CMPEN_MON_SFT 2
1625#define DA_EINT0CMPEN_MON_MASK 0x1
1626#define DA_EINT0CMPEN_MON_MASK_SFT (0x1 << 2)
1627#define DA_EINT0INVEN_MON_ADDR \
1628 MT6359_ACCDET_CON38
1629#define DA_EINT0INVEN_MON_SFT 3
1630#define DA_EINT0INVEN_MON_MASK 0x1
1631#define DA_EINT0INVEN_MON_MASK_SFT (0x1 << 3)
1632#define DA_EINT0CEN_MON_ADDR \
1633 MT6359_ACCDET_CON38
1634#define DA_EINT0CEN_MON_SFT 4
1635#define DA_EINT0CEN_MON_MASK 0x1
1636#define DA_EINT0CEN_MON_MASK_SFT (0x1 << 4)
1637#define DA_EINT0EN_MON_ADDR \
1638 MT6359_ACCDET_CON38
1639#define DA_EINT0EN_MON_SFT 5
1640#define DA_EINT0EN_MON_MASK 0x1
1641#define DA_EINT0EN_MON_MASK_SFT (0x1 << 5)
1642#define DA_EINT1CTURBO_MON_ADDR \
1643 MT6359_ACCDET_CON38
1644#define DA_EINT1CTURBO_MON_SFT 8
1645#define DA_EINT1CTURBO_MON_MASK 0x1
1646#define DA_EINT1CTURBO_MON_MASK_SFT (0x1 << 8)
1647#define DA_EINT1CMPMEN_MON_ADDR \
1648 MT6359_ACCDET_CON38
1649#define DA_EINT1CMPMEN_MON_SFT 9
1650#define DA_EINT1CMPMEN_MON_MASK 0x1
1651#define DA_EINT1CMPMEN_MON_MASK_SFT (0x1 << 9)
1652#define DA_EINT1CMPEN_MON_ADDR \
1653 MT6359_ACCDET_CON38
1654#define DA_EINT1CMPEN_MON_SFT 10
1655#define DA_EINT1CMPEN_MON_MASK 0x1
1656#define DA_EINT1CMPEN_MON_MASK_SFT (0x1 << 10)
1657#define DA_EINT1INVEN_MON_ADDR \
1658 MT6359_ACCDET_CON38
1659#define DA_EINT1INVEN_MON_SFT 11
1660#define DA_EINT1INVEN_MON_MASK 0x1
1661#define DA_EINT1INVEN_MON_MASK_SFT (0x1 << 11)
1662#define DA_EINT1CEN_MON_ADDR \
1663 MT6359_ACCDET_CON38
1664#define DA_EINT1CEN_MON_SFT 12
1665#define DA_EINT1CEN_MON_MASK 0x1
1666#define DA_EINT1CEN_MON_MASK_SFT (0x1 << 12)
1667#define DA_EINT1EN_MON_ADDR \
1668 MT6359_ACCDET_CON38
1669#define DA_EINT1EN_MON_SFT 13
1670#define DA_EINT1EN_MON_MASK 0x1
1671#define DA_EINT1EN_MON_MASK_SFT (0x1 << 13)
1672#define ACCDET_EINT0_M_PLUG_IN_COUNT_ADDR \
1673 MT6359_ACCDET_CON39
1674#define ACCDET_EINT0_M_PLUG_IN_COUNT_SFT 0
1675#define ACCDET_EINT0_M_PLUG_IN_COUNT_MASK 0x7
1676#define ACCDET_EINT0_M_PLUG_IN_COUNT_MASK_SFT (0x7 << 0)
1677#define ACCDET_EINT1_M_PLUG_IN_COUNT_ADDR \
1678 MT6359_ACCDET_CON39
1679#define ACCDET_EINT1_M_PLUG_IN_COUNT_SFT 4
1680#define ACCDET_EINT1_M_PLUG_IN_COUNT_MASK 0x7
1681#define ACCDET_EINT1_M_PLUG_IN_COUNT_MASK_SFT (0x7 << 4)
1682#define ACCDET_MON_FLAG_EN_ADDR \
1683 MT6359_ACCDET_CON40
1684#define ACCDET_MON_FLAG_EN_SFT 0
1685#define ACCDET_MON_FLAG_EN_MASK 0x1
1686#define ACCDET_MON_FLAG_EN_MASK_SFT (0x1 << 0)
1687#define ACCDET_MON_FLAG_SEL_ADDR \
1688 MT6359_ACCDET_CON40
1689#define ACCDET_MON_FLAG_SEL_SFT 4
1690#define ACCDET_MON_FLAG_SEL_MASK 0xF
1691#define ACCDET_MON_FLAG_SEL_MASK_SFT (0xF << 4)
1692
1693#define RG_AUDPWDBMICBIAS0_ADDR \
1694 MT6359_AUDENC_ANA_CON15
1695#define RG_AUDPWDBMICBIAS0_SFT 0
1696#define RG_AUDPWDBMICBIAS0_MASK 0x1
1697#define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)
1698#define RG_AUDPREAMPLON_ADDR \
1699 MT6359_AUDENC_ANA_CON0
1700#define RG_AUDPREAMPLON_SFT 0
1701#define RG_AUDPREAMPLON_MASK 0x1
1702#define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)
1703#define RG_CLKSQ_EN_ADDR \
1704 MT6359_AUDENC_ANA_CON23
1705#define RG_CLKSQ_EN_SFT 0
1706#define RG_CLKSQ_EN_MASK 0x1
1707#define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)
1708#define RG_RTC32K_CK_PDN_ADDR \
1709 MT6359_TOP_CKPDN_CON0
1710#define RG_RTC32K_CK_PDN_SFT 15
1711#define RG_RTC32K_CK_PDN_MASK 0x1
1712#define RG_RTC32K_CK_PDN_MASK_SFT (0x1 << 15)
1713#define RG_HPLOUTPUTSTBENH_VAUDP32_ADDR \
1714 MT6359_AUDDEC_ANA_CON2
1715#define RG_HPLOUTPUTSTBENH_VAUDP32_SFT 0
1716#define RG_HPLOUTPUTSTBENH_VAUDP32_MASK 0x7
1717#define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 0)
1718#define AUXADC_RQST_CH5_ADDR \
1719 MT6359_AUXADC_RQST0
1720#define AUXADC_RQST_CH5_SFT 5
1721#define AUXADC_RQST_CH5_MASK 0x1
1722#define AUXADC_RQST_CH5_MASK_SFT (0x1 << 5)
1723#define RG_LDO_VUSB_HW0_OP_EN_ADDR \
1724 MT6359_LDO_VUSB_OP_EN
1725#define RG_LDO_VUSB_HW0_OP_EN_SFT 0
1726#define RG_LDO_VUSB_HW0_OP_EN_MASK 0x1
1727#define RG_LDO_VUSB_HW0_OP_EN_MASK_SFT (0x1 << 0)
1728#define RG_HPROUTPUTSTBENH_VAUDP32_ADDR \
1729 MT6359_AUDDEC_ANA_CON2
1730#define RG_HPROUTPUTSTBENH_VAUDP32_SFT 4
1731#define RG_HPROUTPUTSTBENH_VAUDP32_MASK 0x7
1732#define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 4)
1733#define RG_NCP_PDDIS_EN_ADDR \
1734 MT6359_AFE_NCP_CFG2
1735#define RG_NCP_PDDIS_EN_SFT 0
1736#define RG_NCP_PDDIS_EN_MASK 0x1
1737#define RG_NCP_PDDIS_EN_MASK_SFT (0x1 << 0)
1738#define RG_SCK32K_CK_PDN_ADDR \
1739 MT6359_TOP_CKPDN_CON0
1740#define RG_SCK32K_CK_PDN_SFT 0
1741#define RG_SCK32K_CK_PDN_MASK 0x1
1742#define RG_SCK32K_CK_PDN_MASK_SFT (0x1 << 0)
83/* AUDENC_ANA_CON18: */
1743/* AUDENC_ANA_CON18: */
84#define RG_ACCDET_MODE_ANA11_MODE1 (0x000f)
85#define RG_ACCDET_MODE_ANA11_MODE2 (0x008f)
86#define RG_ACCDET_MODE_ANA11_MODE6 (0x008f)
1744#define RG_ACCDET_MODE_ANA11_MODE1 (0x000F)
1745#define RG_ACCDET_MODE_ANA11_MODE2 (0x008F)
1746#define RG_ACCDET_MODE_ANA11_MODE6 (0x008F)
87
88/* AUXADC_ADC5: Auxadc CH5 read data */
89#define AUXADC_DATA_RDY_CH5 BIT(15)
90#define AUXADC_DATA_PROCEED_CH5 BIT(15)
1747
1748/* AUXADC_ADC5: Auxadc CH5 read data */
1749#define AUXADC_DATA_RDY_CH5 BIT(15)
1750#define AUXADC_DATA_PROCEED_CH5 BIT(15)
91#define AUXADC_DATA_MASK (0x0fff)
1751#define AUXADC_DATA_MASK (0x0FFF)
92
93/* AUXADC_RQST0_SET: Auxadc CH5 request, relevant 0x07EC */
94#define AUXADC_RQST_CH5_SET BIT(5)
95/* AUXADC_RQST0_CLR: Auxadc CH5 request, relevant 0x07EC */
96#define AUXADC_RQST_CH5_CLR BIT(5)
97
1752
1753/* AUXADC_RQST0_SET: Auxadc CH5 request, relevant 0x07EC */
1754#define AUXADC_RQST_CH5_SET BIT(5)
1755/* AUXADC_RQST0_CLR: Auxadc CH5 request, relevant 0x07EC */
1756#define AUXADC_RQST_CH5_CLR BIT(5)
1757
98#define ACCDET_CALI_MASK0 (0xff)
99#define ACCDET_CALI_MASK1 (0xff << 8)
100#define ACCDET_CALI_MASK2 (0xff)
101#define ACCDET_CALI_MASK3 (0xff << 8)
102#define ACCDET_CALI_MASK4 (0xff)
1758#define ACCDET_CALI_MASK0 (0xFF)
1759#define ACCDET_CALI_MASK1 (0xFF << 8)
1760#define ACCDET_CALI_MASK2 (0xFF)
1761#define ACCDET_CALI_MASK3 (0xFF << 8)
1762#define ACCDET_CALI_MASK4 (0xFF)
103
1763
104#define ACCDET_EINT1_IRQ_CLR_B11 BIT(PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT)
105#define ACCDET_EINT0_IRQ_CLR_B10 BIT(PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT)
106#define ACCDET_EINT_IRQ_CLR_B10_11 (0x03 << \
107 PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT)
108#define ACCDET_IRQ_CLR_B8 BIT(PMIC_ACCDET_IRQ_CLR_SHIFT)
1764#define ACCDET_EINT_IRQ_B2_B3 (0x03 << ACCDET_EINT0_IRQ_SFT)
109
1765
110#define ACCDET_EINT1_IRQ_B3 BIT(PMIC_ACCDET_EINT1_IRQ_SHIFT)
111#define ACCDET_EINT0_IRQ_B2 BIT(PMIC_ACCDET_EINT0_IRQ_SHIFT)
112#define ACCDET_EINT_IRQ_B2_B3 (0x03 << PMIC_ACCDET_EINT0_IRQ_SHIFT)
113#define ACCDET_IRQ_B0 BIT(PMIC_ACCDET_IRQ_SHIFT)
114
115/* ACCDET_CON25: RO, accdet FSM state,etc.*/
1766/* ACCDET_CON25: RO, accdet FSM state,etc.*/
116#define ACCDET_STATE_MEM_IN_OFFSET (PMIC_ACCDET_MEM_IN_SHIFT)
117#define ACCDET_STATE_AB_MASK (0x03)
118#define ACCDET_STATE_AB_00 (0x00)
119#define ACCDET_STATE_AB_01 (0x01)
120#define ACCDET_STATE_AB_10 (0x02)
121#define ACCDET_STATE_AB_11 (0x03)
1767#define ACCDET_STATE_MEM_IN_OFFSET (ACCDET_MEM_IN_SFT)
1768#define ACCDET_STATE_AB_MASK (0x03)
1769#define ACCDET_STATE_AB_00 (0x00)
1770#define ACCDET_STATE_AB_01 (0x01)
1771#define ACCDET_STATE_AB_10 (0x02)
1772#define ACCDET_STATE_AB_11 (0x03)
122
123/* ACCDET_CON19 */
1773
1774/* ACCDET_CON19 */
124#define ACCDET_EINT0_STABLE_VAL ((1 << PMIC_ACCDET_DA_STABLE_SHIFT) | \
125 (1 << PMIC_ACCDET_EINT0_EN_STABLE_SHIFT) | \
126 (1 << PMIC_ACCDET_EINT0_CMPEN_STABLE_SHIFT) | \
127 (1 << PMIC_ACCDET_EINT0_CEN_STABLE_SHIFT))
1775#define ACCDET_EINT0_STABLE_VAL ((ACCDET_DA_STABLE_MASK_SFT) | \
1776 (ACCDET_EINT0_EN_STABLE_MASK_SFT) | \
1777 (ACCDET_EINT0_CMPEN_STABLE_MASK_SFT) | \
1778 (ACCDET_EINT0_CEN_STABLE_MASK_SFT))
128
1779
129#define ACCDET_EINT1_STABLE_VAL ((1 << PMIC_ACCDET_DA_STABLE_SHIFT) | \
130 (1 << PMIC_ACCDET_EINT1_EN_STABLE_SHIFT) | \
131 (1 << PMIC_ACCDET_EINT1_CMPEN_STABLE_SHIFT) | \
132 (1 << PMIC_ACCDET_EINT1_CEN_STABLE_SHIFT))
133
1780#define ACCDET_EINT1_STABLE_VAL ((ACCDET_DA_STABLE_MASK_SFT) | \
1781 (ACCDET_EINT1_EN_STABLE_MASK_SFT) | \
1782 (ACCDET_EINT1_CMPEN_STABLE_MASK_SFT) | \
1783 (ACCDET_EINT1_CEN_STABLE_MASK_SFT))
134/* The following are used for mt6359.c */
135/* MT6359_DCXO_CW12 */
136#define RG_XO_AUDIO_EN_M_SFT 13
137
138/* AUD_TOP_CKPDN_CON0 */
139#define RG_VOW13M_CK_PDN_SFT 13
140#define RG_VOW13M_CK_PDN_MASK 0x1
141#define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)

--- 2498 unchanged lines hidden --- 		1784/* The following are used for mt6359.c */
1785/* MT6359_DCXO_CW12 */
1786#define RG_XO_AUDIO_EN_M_SFT 13
1787
1788/* AUD_TOP_CKPDN_CON0 */
1789#define RG_VOW13M_CK_PDN_SFT 13
1790#define RG_VOW13M_CK_PDN_MASK 0x1
1791#define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)

--- 2498 unchanged lines hidden ---