mt6359.c (01be83eea08d6d9f9209843e2e084505fba4053f) mt6359.c (682c5a72a2bb0745da73211bed5f47ccccd84025)
1// SPDX-License-Identifier: GPL-2.0
2//
3// mt6359.c -- mt6359 ALSA SoC audio codec driver
4//
5// Copyright (c) 2020 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/delay.h>

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63 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
64
65 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0,
66 0x7 << 13, 0x0);
67 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR1,
68 0x3 << 0, 0x0);
69}
70
1// SPDX-License-Identifier: GPL-2.0
2//
3// mt6359.c -- mt6359 ALSA SoC audio codec driver
4//
5// Copyright (c) 2020 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/delay.h>

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63 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
64
65 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0,
66 0x7 << 13, 0x0);
67 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR1,
68 0x3 << 0, 0x0);
69}
70
71/* use only when doing mtkaif calibraiton at the boot time */
72static void mt6359_set_dcxo(struct mt6359_priv *priv, bool enable)
73{
74 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
75 0x1 << RG_XO_AUDIO_EN_M_SFT,
76 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
77}
78
79/* use only when doing mtkaif calibraiton at the boot time */
80static void mt6359_set_clksq(struct mt6359_priv *priv, bool enable)
81{
82 /* Enable/disable CLKSQ 26MHz */
83 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
84 RG_CLKSQ_EN_MASK_SFT,
85 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
86}
87
88/* use only when doing mtkaif calibraiton at the boot time */
89static void mt6359_set_aud_global_bias(struct mt6359_priv *priv, bool enable)
90{
91 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
92 RG_AUDGLB_PWRDN_VA32_MASK_SFT,
93 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA32_SFT);
94}
95
96/* use only when doing mtkaif calibraiton at the boot time */
97static void mt6359_set_topck(struct mt6359_priv *priv, bool enable)
98{
99 regmap_update_bits(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0,
100 0x0066, enable ? 0x0 : 0x66);
101}
102
71static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable)
72{
73 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
74 RG_RSTB_DECODER_VA32_MASK_SFT,
75 (enable ? 1 : 0) << RG_RSTB_DECODER_VA32_SFT);
76}
77
78static void mt6359_mtkaif_tx_enable(struct mt6359_priv *priv)

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117
118static void mt6359_mtkaif_tx_disable(struct mt6359_priv *priv)
119{
120 /* disable aud_pad TX fifos */
121 regmap_update_bits(priv->regmap, MT6359_AFE_AUD_PAD_TOP,
122 0xff00, 0x3000);
123}
124
103static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable)
104{
105 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
106 RG_RSTB_DECODER_VA32_MASK_SFT,
107 (enable ? 1 : 0) << RG_RSTB_DECODER_VA32_SFT);
108}
109
110static void mt6359_mtkaif_tx_enable(struct mt6359_priv *priv)

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149
150static void mt6359_mtkaif_tx_disable(struct mt6359_priv *priv)
151{
152 /* disable aud_pad TX fifos */
153 regmap_update_bits(priv->regmap, MT6359_AFE_AUD_PAD_TOP,
154 0xff00, 0x3000);
155}
156
157void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
158 int mtkaif_protocol)
159{
160 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
161
162 priv->mtkaif_protocol = mtkaif_protocol;
163}
164EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_protocol);
165
166void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
167{
168 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
169
170 mt6359_set_playback_gpio(priv);
171 mt6359_set_capture_gpio(priv);
172 mt6359_mtkaif_tx_enable(priv);
173
174 mt6359_set_dcxo(priv, true);
175 mt6359_set_aud_global_bias(priv, true);
176 mt6359_set_clksq(priv, true);
177 mt6359_set_topck(priv, true);
178
179 /* set dat_miso_loopback on */
180 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
181 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
182 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
183 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
184 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
185 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
186 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
187 RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
188 1 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);
189}
190EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_enable);
191
192void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
193{
194 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
195
196 /* set dat_miso_loopback off */
197 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
198 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
199 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
200 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
201 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
202 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
203 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
204 RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT,
205 0 << RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT);
206
207 mt6359_set_topck(priv, false);
208 mt6359_set_clksq(priv, false);
209 mt6359_set_aud_global_bias(priv, false);
210 mt6359_set_dcxo(priv, false);
211
212 mt6359_mtkaif_tx_disable(priv);
213 mt6359_reset_playback_gpio(priv);
214 mt6359_reset_capture_gpio(priv);
215}
216EXPORT_SYMBOL_GPL(mt6359_mtkaif_calibration_disable);
217
218void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
219 int phase_1, int phase_2, int phase_3)
220{
221 struct mt6359_priv *priv = snd_soc_component_get_drvdata(cmpnt);
222
223 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
224 RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
225 phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
226 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
227 RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
228 phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
229 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
230 RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT,
231 phase_3 << RG_AUD_PAD_TOP_PHASE_MODE3_SFT);
232}
233EXPORT_SYMBOL_GPL(mt6359_set_mtkaif_calibration_phase);
234
125static void zcd_disable(struct mt6359_priv *priv)
126{
127 regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000);
128}
129
130static void hp_main_output_ramp(struct mt6359_priv *priv, bool up)
131{
132 int i = 0, stage = 0;

--- 2626 unchanged lines hidden --- 		235static void zcd_disable(struct mt6359_priv *priv)
236{
237 regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000);
238}
239
240static void hp_main_output_ramp(struct mt6359_priv *priv, bool up)
241{
242 int i = 0, stage = 0;

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