max98390.c (87a0b2fafc09766d8c55461a18345a1cfb10a7fe) max98390.c (c536d745adbc83abb782077a212a8cbdd7300b54)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * max98390.c -- MAX98390 ALSA Soc Audio driver
4 *
5 * Copyright (C) 2020 Maxim Integrated Products
6 *
7 */
8

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169 struct max98390_priv *max98390 =
170 snd_soc_component_get_drvdata(component);
171 unsigned int mode;
172 unsigned int format;
173 unsigned int invert = 0;
174
175 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
176
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * max98390.c -- MAX98390 ALSA Soc Audio driver
4 *
5 * Copyright (C) 2020 Maxim Integrated Products
6 *
7 */
8

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169 struct max98390_priv *max98390 =
170 snd_soc_component_get_drvdata(component);
171 unsigned int mode;
172 unsigned int format;
173 unsigned int invert = 0;
174
175 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
176
177 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
178 case SND_SOC_DAIFMT_CBS_CFS:
177 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
178 case SND_SOC_DAIFMT_CBC_CFC:
179 mode = MAX98390_PCM_MASTER_MODE_SLAVE;
180 break;
179 mode = MAX98390_PCM_MASTER_MODE_SLAVE;
180 break;
181 case SND_SOC_DAIFMT_CBM_CFM:
182 max98390->master = true;
181 case SND_SOC_DAIFMT_CBP_CFP:
182 max98390->provider = true;
183 mode = MAX98390_PCM_MASTER_MODE_MASTER;
184 break;
185 default:
186 dev_err(component->dev, "DAI clock mode unsupported\n");
187 return -EINVAL;
188 }
189
190 regmap_update_bits(max98390->regmap,

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260 9600000, 11289600, 12000000, 12288000,
261 13000000, 19200000,
262 };
263 /* BCLK/LRCLK ratio calculation */
264 int blr_clk_ratio = params_channels(params)
265 * snd_pcm_format_width(params_format(params));
266 int value;
267
183 mode = MAX98390_PCM_MASTER_MODE_MASTER;
184 break;
185 default:
186 dev_err(component->dev, "DAI clock mode unsupported\n");
187 return -EINVAL;
188 }
189
190 regmap_update_bits(max98390->regmap,

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260 9600000, 11289600, 12000000, 12288000,
261 13000000, 19200000,
262 };
263 /* BCLK/LRCLK ratio calculation */
264 int blr_clk_ratio = params_channels(params)
265 * snd_pcm_format_width(params_format(params));
266 int value;
267
268 if (max98390->master) {
268 if (max98390->provider) {
269 int i;
270 /* match rate to closest value */
271 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
272 if (rate_table[i] >= max98390->sysclk)
273 break;
274 }
275 if (i == ARRAY_SIZE(rate_table)) {
276 dev_err(component->dev, "failed to find proper clock rate.\n");

--- 856 unchanged lines hidden --- 		269 int i;
270 /* match rate to closest value */
271 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
272 if (rate_table[i] >= max98390->sysclk)
273 break;
274 }
275 if (i == ARRAY_SIZE(rate_table)) {
276 dev_err(component->dev, "failed to find proper clock rate.\n");

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