max98090.c (74c12ee02af109adcde36ec184fa59c0afb0edaa) max98090.c (4b8a1ca4628343829f373bf0d4e087fe50c451e5)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
4 *
5 * Copyright 2011-2012 Maxim Integrated Products
6 */
7
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
4 *
5 * Copyright 2011-2012 Maxim Integrated Products
6 */
7
8#include <linux/acpi.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/i2c.h>
12#include <linux/module.h>
8#include <linux/delay.h>
9#include <linux/i2c.h>
10#include <linux/module.h>
13#include <linux/mutex.h>
14#include <linux/of.h>
15#include <linux/pm.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <linux/slab.h>
11#include <linux/of.h>
12#include <linux/pm.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15#include <linux/slab.h>
16#include <linux/acpi.h>
17#include <linux/clk.h>
19#include <sound/jack.h>
18#include <sound/jack.h>
20#include <sound/max98090.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/soc.h>
24#include <sound/tlv.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/soc.h>
22#include <sound/tlv.h>
23#include <sound/max98090.h>
25#include "max98090.h"
26
24#include "max98090.h"
25
27static void max98090_shdn_save_locked(struct max98090_priv *max98090)
28{
29 int shdn = 0;
30
31 /* saved_shdn, saved_count, SHDN are protected by card->dapm_mutex */
32 regmap_read(max98090->regmap, M98090_REG_DEVICE_SHUTDOWN, &shdn);
33 max98090->saved_shdn |= shdn;
34 ++max98090->saved_count;
35
36 if (shdn)
37 regmap_write(max98090->regmap, M98090_REG_DEVICE_SHUTDOWN, 0x0);
38}
39
40static void max98090_shdn_restore_locked(struct max98090_priv *max98090)
41{
42 /* saved_shdn, saved_count, SHDN are protected by card->dapm_mutex */
43 if (--max98090->saved_count == 0) {
44 if (max98090->saved_shdn) {
45 regmap_write(max98090->regmap,
46 M98090_REG_DEVICE_SHUTDOWN,
47 M98090_SHDNN_MASK);
48 max98090->saved_shdn = 0;
49 }
50 }
51}
52
53static void max98090_shdn_save(struct max98090_priv *max98090)
54{
55 mutex_lock_nested(&max98090->component->card->dapm_mutex,
56 SND_SOC_DAPM_CLASS_RUNTIME);
57 max98090_shdn_save_locked(max98090);
58}
59
60static void max98090_shdn_restore(struct max98090_priv *max98090)
61{
62 max98090_shdn_restore_locked(max98090);
63 mutex_unlock(&max98090->component->card->dapm_mutex);
64}
65
66static int max98090_put_volsw(struct snd_kcontrol *kcontrol,
67 struct snd_ctl_elem_value *ucontrol)
68{
69 struct snd_soc_component *component =
70 snd_soc_kcontrol_component(kcontrol);
71 struct max98090_priv *max98090 =
72 snd_soc_component_get_drvdata(component);
73 int ret;
74
75 max98090_shdn_save(max98090);
76 ret = snd_soc_put_volsw(kcontrol, ucontrol);
77 max98090_shdn_restore(max98090);
78
79 return ret;
80}
81
82static int max98090_dapm_put_enum_double(struct snd_kcontrol *kcontrol,
83 struct snd_ctl_elem_value *ucontrol)
84{
85 struct snd_soc_component *component =
86 snd_soc_dapm_kcontrol_component(kcontrol);
87 struct max98090_priv *max98090 =
88 snd_soc_component_get_drvdata(component);
89 int ret;
90
91 max98090_shdn_save(max98090);
92 ret = snd_soc_dapm_put_enum_double_locked(kcontrol, ucontrol);
93 max98090_shdn_restore(max98090);
94
95 return ret;
96}
97
98static int max98090_put_enum_double(struct snd_kcontrol *kcontrol,
99 struct snd_ctl_elem_value *ucontrol)
100{
101 struct snd_soc_component *component =
102 snd_soc_kcontrol_component(kcontrol);
103 struct max98090_priv *max98090 =
104 snd_soc_component_get_drvdata(component);
105 int ret;
106
107 max98090_shdn_save(max98090);
108 ret = snd_soc_put_enum_double(kcontrol, ucontrol);
109 max98090_shdn_restore(max98090);
110
111 return ret;
112}
113
114static int max98090_bytes_put(struct snd_kcontrol *kcontrol,
115 struct snd_ctl_elem_value *ucontrol)
116{
117 struct snd_soc_component *component =
118 snd_soc_kcontrol_component(kcontrol);
119 struct max98090_priv *max98090 =
120 snd_soc_component_get_drvdata(component);
121 int ret;
122
123 max98090_shdn_save(max98090);
124 ret = snd_soc_bytes_put(kcontrol, ucontrol);
125 max98090_shdn_restore(max98090);
126
127 return ret;
128}
129
130static int max98090_dapm_event(struct snd_soc_dapm_widget *w,
131 struct snd_kcontrol *kcontrol, int event)
132{
133 struct snd_soc_component *component =
134 snd_soc_dapm_to_component(w->dapm);
135 struct max98090_priv *max98090 =
136 snd_soc_component_get_drvdata(component);
137
138 switch (event) {
139 case SND_SOC_DAPM_PRE_PMU:
140 case SND_SOC_DAPM_PRE_PMD:
141 max98090_shdn_save_locked(max98090);
142 break;
143 case SND_SOC_DAPM_POST_PMU:
144 case SND_SOC_DAPM_POST_PMD:
145 max98090_shdn_restore_locked(max98090);
146 break;
147 }
148
149 return 0;
150}
151
152/* Allows for sparsely populated register maps */
153static const struct reg_default max98090_reg[] = {
154 { 0x00, 0x00 }, /* 00 Software Reset */
155 { 0x03, 0x04 }, /* 03 Interrupt Masks */
156 { 0x04, 0x00 }, /* 04 System Clock Quick */
157 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
158 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
159 { 0x07, 0x00 }, /* 07 DAC Path Quick */

--- 467 unchanged lines hidden (view full) ---

627 max98090_pwr_perf_text);
628
629static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
630 M98090_REG_ADC_CONTROL,
631 M98090_ADCHP_SHIFT,
632 max98090_pwr_perf_text);
633
634static const struct snd_kcontrol_new max98090_snd_controls[] = {
26/* Allows for sparsely populated register maps */
27static const struct reg_default max98090_reg[] = {
28 { 0x00, 0x00 }, /* 00 Software Reset */
29 { 0x03, 0x04 }, /* 03 Interrupt Masks */
30 { 0x04, 0x00 }, /* 04 System Clock Quick */
31 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
32 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
33 { 0x07, 0x00 }, /* 07 DAC Path Quick */

--- 467 unchanged lines hidden (view full) ---

501 max98090_pwr_perf_text);
502
503static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
504 M98090_REG_ADC_CONTROL,
505 M98090_ADCHP_SHIFT,
506 max98090_pwr_perf_text);
507
508static const struct snd_kcontrol_new max98090_snd_controls[] = {
635 SOC_ENUM_EXT("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum,
636 snd_soc_get_enum_double, max98090_put_enum_double),
509 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
637
510
638 SOC_SINGLE_EXT("DMIC MIC Comp Filter Config",
639 M98090_REG_DIGITAL_MIC_CONFIG,
640 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0,
641 snd_soc_get_volsw, max98090_put_volsw),
511 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
512 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
642
643 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
644 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
645 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
646 max98090_put_enab_tlv, max98090_micboost_tlv),
647
648 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
649 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,

--- 38 unchanged lines hidden (view full) ---

688
689 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
690 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
691 max98090_av_tlv),
692 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
693 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
694 max98090_av_tlv),
695
513
514 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
515 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
516 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
517 max98090_put_enab_tlv, max98090_micboost_tlv),
518
519 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
520 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,

--- 38 unchanged lines hidden (view full) ---

559
560 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
561 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
562 max98090_av_tlv),
563 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
564 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
565 max98090_av_tlv),
566
696 SOC_ENUM_EXT("ADC Oversampling Rate", max98090_osr128_enum,
697 snd_soc_get_enum_double, max98090_put_enum_double),
698 SOC_SINGLE_EXT("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
699 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0,
700 snd_soc_get_volsw, max98090_put_volsw),
701 SOC_ENUM_EXT("ADC High Performance Mode", max98090_adchp_enum,
702 snd_soc_get_enum_double, max98090_put_enum_double),
567 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
568 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
569 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
570 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
703
571
704 SOC_SINGLE_EXT("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
705 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0,
706 snd_soc_get_volsw, max98090_put_volsw),
707 SOC_SINGLE_EXT("SDIN Mode", M98090_REG_IO_CONFIGURATION,
708 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0,
709 snd_soc_get_volsw, max98090_put_volsw),
710 SOC_SINGLE_EXT("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
711 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0,
712 snd_soc_get_volsw, max98090_put_volsw),
713 SOC_SINGLE_EXT("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
714 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1,
715 snd_soc_get_volsw, max98090_put_volsw),
716 SOC_ENUM_EXT("Filter Mode", max98090_mode_enum,
717 snd_soc_get_enum_double, max98090_put_enum_double),
718 SOC_SINGLE_EXT("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
719 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0,
720 snd_soc_get_volsw, max98090_put_volsw),
721 SOC_SINGLE_EXT("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
722 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0,
723 snd_soc_get_volsw, max98090_put_volsw),
572 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
573 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
574 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
575 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
576 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
577 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
578 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
579 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
580 SOC_ENUM("Filter Mode", max98090_mode_enum),
581 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
582 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
583 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
584 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
724 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
725 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
726 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
727 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
728 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
729 max98090_put_enab_tlv, max98090_sdg_tlv),
730 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
731 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
732 max98090_dvg_tlv),
733 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
734 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
735 max98090_dv_tlv),
585 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
586 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
587 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
588 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
589 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
590 max98090_put_enab_tlv, max98090_sdg_tlv),
591 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
592 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
593 max98090_dvg_tlv),
594 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
595 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
596 max98090_dv_tlv),
736 SND_SOC_BYTES_E("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105,
737 snd_soc_bytes_get, max98090_bytes_put),
738 SOC_SINGLE_EXT("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
739 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0,
740 snd_soc_get_volsw, max98090_put_volsw),
741 SOC_SINGLE_EXT("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
742 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0,
743 snd_soc_get_volsw, max98090_put_volsw),
744 SOC_SINGLE_EXT("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
745 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0,
746 snd_soc_get_volsw, max98090_put_volsw),
597 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
598 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
599 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
600 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
601 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
602 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
603 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
747 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
748 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
749 1),
750 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
751 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
752 max98090_dv_tlv),
753
604 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
605 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
606 1),
607 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
608 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
609 max98090_dv_tlv),
610
754 SOC_SINGLE_EXT("ALC Enable", M98090_REG_DRC_TIMING,
755 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0,
756 snd_soc_get_volsw, max98090_put_volsw),
757 SOC_ENUM_EXT("ALC Attack Time", max98090_drcatk_enum,
758 snd_soc_get_enum_double, max98090_put_enum_double),
759 SOC_ENUM_EXT("ALC Release Time", max98090_drcrls_enum,
760 snd_soc_get_enum_double, max98090_put_enum_double),
611 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
612 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
613 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
614 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
761 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
762 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
763 max98090_alcmakeup_tlv),
615 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
616 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
617 max98090_alcmakeup_tlv),
764 SOC_ENUM_EXT("ALC Compression Ratio", max98090_alccmp_enum,
765 snd_soc_get_enum_double, max98090_put_enum_double),
766 SOC_ENUM_EXT("ALC Expansion Ratio", max98090_drcexp_enum,
767 snd_soc_get_enum_double, max98090_put_enum_double),
768 SOC_SINGLE_EXT_TLV("ALC Compression Threshold Volume",
618 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
619 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
620 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
769 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
621 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
770 M98090_DRCTHC_NUM - 1, 1,
771 snd_soc_get_volsw, max98090_put_volsw, max98090_alccomp_tlv),
772 SOC_SINGLE_EXT_TLV("ALC Expansion Threshold Volume",
622 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
623 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
773 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
624 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
774 M98090_DRCTHE_NUM - 1, 1,
775 snd_soc_get_volsw, max98090_put_volsw, max98090_drcexp_tlv),
625 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
776
626
777 SOC_ENUM_EXT("DAC HP Playback Performance Mode",
778 max98090_dac_perfmode_enum,
779 snd_soc_get_enum_double, max98090_put_enum_double),
780 SOC_ENUM_EXT("DAC High Performance Mode", max98090_dachp_enum,
781 snd_soc_get_enum_double, max98090_put_enum_double),
627 SOC_ENUM("DAC HP Playback Performance Mode",
628 max98090_dac_perfmode_enum),
629 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
782
783 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
784 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
785 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
786 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
787 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
788 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
789

--- 41 unchanged lines hidden (view full) ---

831
832 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
833 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
834 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
835 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
836 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
837 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
838
630
631 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
632 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
633 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
634 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
635 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
636 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
637

--- 41 unchanged lines hidden (view full) ---

679
680 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
681 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
682 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
683 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
684 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
685 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
686
839 SND_SOC_BYTES_E("Biquad Coefficients",
840 M98090_REG_RECORD_BIQUAD_BASE, 15,
841 snd_soc_bytes_get, max98090_bytes_put),
842 SOC_SINGLE_EXT("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
843 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0,
844 snd_soc_get_volsw, max98090_put_volsw),
687 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
688 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
689 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
845};
846
847static const struct snd_kcontrol_new max98091_snd_controls[] = {
848
849 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
850 M98090_DMIC34_ZEROPAD_SHIFT,
851 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
852
690};
691
692static const struct snd_kcontrol_new max98091_snd_controls[] = {
693
694 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
695 M98090_DMIC34_ZEROPAD_SHIFT,
696 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
697
853 SOC_ENUM_EXT("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum,
854 snd_soc_get_enum_double, max98090_put_enum_double),
855 SOC_SINGLE_EXT("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
698 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
699 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
856 M98090_FLT_DMIC34HPF_SHIFT,
700 M98090_FLT_DMIC34HPF_SHIFT,
857 M98090_FLT_DMIC34HPF_NUM - 1, 0,
858 snd_soc_get_volsw, max98090_put_volsw),
701 M98090_FLT_DMIC34HPF_NUM - 1, 0),
859
860 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
861 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
862 max98090_avg_tlv),
863 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
864 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
865 max98090_avg_tlv),
866
867 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
868 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
869 max98090_av_tlv),
870 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
871 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
872 max98090_av_tlv),
873
874 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
875 M98090_REG_DMIC34_BIQUAD_BASE, 15),
702
703 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
704 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
705 max98090_avg_tlv),
706 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
707 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
708 max98090_avg_tlv),
709
710 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
711 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
712 max98090_av_tlv),
713 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
714 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
715 max98090_av_tlv),
716
717 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
718 M98090_REG_DMIC34_BIQUAD_BASE, 15),
876 SOC_SINGLE_EXT("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
877 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0,
878 snd_soc_get_volsw, max98090_put_volsw),
719 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
720 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
879
880 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
881 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
882 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
883};
884
885static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
886 struct snd_kcontrol *kcontrol, int event)

--- 37 unchanged lines hidden (view full) ---

924 val << M98090_MIC_PA1EN_SHIFT);
925 else
926 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK,
927 val << M98090_MIC_PA2EN_SHIFT);
928
929 return 0;
930}
931
721
722 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
723 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
724 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
725};
726
727static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
728 struct snd_kcontrol *kcontrol, int event)

--- 37 unchanged lines hidden (view full) ---

766 val << M98090_MIC_PA1EN_SHIFT);
767 else
768 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK,
769 val << M98090_MIC_PA2EN_SHIFT);
770
771 return 0;
772}
773
774static int max98090_shdn_event(struct snd_soc_dapm_widget *w,
775 struct snd_kcontrol *kcontrol, int event)
776{
777 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
778 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
779
780 if (event & SND_SOC_DAPM_POST_PMU)
781 max98090->shdn_pending = true;
782
783 return 0;
784
785}
786
932static const char *mic1_mux_text[] = { "IN12", "IN56" };
933
934static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
935 M98090_REG_INPUT_MODE,
936 M98090_EXTMIC1_SHIFT,
937 mic1_mux_text);
938
939static const struct snd_kcontrol_new max98090_mic1_mux =

--- 84 unchanged lines hidden (view full) ---

1024 lten_mux_text);
1025
1026static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
1027 M98090_REG_IO_CONFIGURATION,
1028 M98090_LTEN_SHIFT,
1029 lten_mux_text);
1030
1031static const struct snd_kcontrol_new max98090_ltenl_mux =
787static const char *mic1_mux_text[] = { "IN12", "IN56" };
788
789static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
790 M98090_REG_INPUT_MODE,
791 M98090_EXTMIC1_SHIFT,
792 mic1_mux_text);
793
794static const struct snd_kcontrol_new max98090_mic1_mux =

--- 84 unchanged lines hidden (view full) ---

879 lten_mux_text);
880
881static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
882 M98090_REG_IO_CONFIGURATION,
883 M98090_LTEN_SHIFT,
884 lten_mux_text);
885
886static const struct snd_kcontrol_new max98090_ltenl_mux =
1032 SOC_DAPM_ENUM_EXT("LTENL Mux", ltenl_mux_enum,
1033 snd_soc_dapm_get_enum_double,
1034 max98090_dapm_put_enum_double);
887 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
1035
1036static const struct snd_kcontrol_new max98090_ltenr_mux =
888
889static const struct snd_kcontrol_new max98090_ltenr_mux =
1037 SOC_DAPM_ENUM_EXT("LTENR Mux", ltenr_mux_enum,
1038 snd_soc_dapm_get_enum_double,
1039 max98090_dapm_put_enum_double);
890 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
1040
1041static const char *lben_mux_text[] = { "Normal", "Loopback" };
1042
1043static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
1044 M98090_REG_IO_CONFIGURATION,
1045 M98090_LBEN_SHIFT,
1046 lben_mux_text);
1047
1048static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
1049 M98090_REG_IO_CONFIGURATION,
1050 M98090_LBEN_SHIFT,
1051 lben_mux_text);
1052
1053static const struct snd_kcontrol_new max98090_lbenl_mux =
891
892static const char *lben_mux_text[] = { "Normal", "Loopback" };
893
894static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
895 M98090_REG_IO_CONFIGURATION,
896 M98090_LBEN_SHIFT,
897 lben_mux_text);
898
899static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
900 M98090_REG_IO_CONFIGURATION,
901 M98090_LBEN_SHIFT,
902 lben_mux_text);
903
904static const struct snd_kcontrol_new max98090_lbenl_mux =
1054 SOC_DAPM_ENUM_EXT("LBENL Mux", lbenl_mux_enum,
1055 snd_soc_dapm_get_enum_double,
1056 max98090_dapm_put_enum_double);
905 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
1057
1058static const struct snd_kcontrol_new max98090_lbenr_mux =
906
907static const struct snd_kcontrol_new max98090_lbenr_mux =
1059 SOC_DAPM_ENUM_EXT("LBENR Mux", lbenr_mux_enum,
1060 snd_soc_dapm_get_enum_double,
1061 max98090_dapm_put_enum_double);
908 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
1062
1063static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
1064
1065static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
1066
1067static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
1068 M98090_REG_ADC_SIDETONE,
1069 M98090_DSTSL_SHIFT,

--- 150 unchanged lines hidden (view full) ---

1220 SND_SOC_DAPM_INPUT("IN4"),
1221 SND_SOC_DAPM_INPUT("IN5"),
1222 SND_SOC_DAPM_INPUT("IN6"),
1223 SND_SOC_DAPM_INPUT("IN12"),
1224 SND_SOC_DAPM_INPUT("IN34"),
1225 SND_SOC_DAPM_INPUT("IN56"),
1226
1227 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
909
910static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
911
912static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
913
914static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
915 M98090_REG_ADC_SIDETONE,
916 M98090_DSTSL_SHIFT,

--- 150 unchanged lines hidden (view full) ---

1067 SND_SOC_DAPM_INPUT("IN4"),
1068 SND_SOC_DAPM_INPUT("IN5"),
1069 SND_SOC_DAPM_INPUT("IN6"),
1070 SND_SOC_DAPM_INPUT("IN12"),
1071 SND_SOC_DAPM_INPUT("IN34"),
1072 SND_SOC_DAPM_INPUT("IN56"),
1073
1074 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1228 M98090_MBEN_SHIFT, 0, max98090_dapm_event,
1229 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1075 M98090_MBEN_SHIFT, 0, NULL, 0),
1230 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1231 M98090_SHDNN_SHIFT, 0, NULL, 0),
1232 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1076 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1077 M98090_SHDNN_SHIFT, 0, NULL, 0),
1078 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1233 M98090_SDIEN_SHIFT, 0, max98090_dapm_event,
1234 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1079 M98090_SDIEN_SHIFT, 0, NULL, 0),
1235 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1080 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1236 M98090_SDOEN_SHIFT, 0, max98090_dapm_event,
1237 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1081 M98090_SDOEN_SHIFT, 0, NULL, 0),
1238 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1082 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1239 M98090_DIGMICL_SHIFT, 0, max98090_dapm_event,
1240 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1083 M98090_DIGMICL_SHIFT, 0, max98090_shdn_event,
1084 SND_SOC_DAPM_POST_PMU),
1241 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1085 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1242 M98090_DIGMICR_SHIFT, 0, max98090_dapm_event,
1243 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1086 M98090_DIGMICR_SHIFT, 0, max98090_shdn_event,
1087 SND_SOC_DAPM_POST_PMU),
1244 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1088 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1245 M98090_AHPF_SHIFT, 0, max98090_dapm_event,
1246 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1089 M98090_AHPF_SHIFT, 0, NULL, 0),
1247
1248/*
1249 * Note: Sysclk and misc power supplies are taken care of by SHDN
1250 */
1251
1252 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1253 0, 0, &max98090_mic1_mux),
1254

--- 13 unchanged lines hidden (view full) ---

1268 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1269 &max98090_linea_mixer_controls[0],
1270 ARRAY_SIZE(max98090_linea_mixer_controls)),
1271
1272 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1273 &max98090_lineb_mixer_controls[0],
1274 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1275
1090
1091/*
1092 * Note: Sysclk and misc power supplies are taken care of by SHDN
1093 */
1094
1095 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1096 0, 0, &max98090_mic1_mux),
1097

--- 13 unchanged lines hidden (view full) ---

1111 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1112 &max98090_linea_mixer_controls[0],
1113 ARRAY_SIZE(max98090_linea_mixer_controls)),
1114
1115 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1116 &max98090_lineb_mixer_controls[0],
1117 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1118
1276 SND_SOC_DAPM_PGA_E("LINEA Input", M98090_REG_INPUT_ENABLE,
1277 M98090_LINEAEN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1278 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1279 SND_SOC_DAPM_PGA_E("LINEB Input", M98090_REG_INPUT_ENABLE,
1280 M98090_LINEBEN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1281 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1119 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1120 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1121 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1122 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1282
1283 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1284 &max98090_left_adc_mixer_controls[0],
1285 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1286
1287 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1288 &max98090_right_adc_mixer_controls[0],
1289 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1290
1291 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1123
1124 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1125 &max98090_left_adc_mixer_controls[0],
1126 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1127
1128 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1129 &max98090_right_adc_mixer_controls[0],
1130 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1131
1132 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1292 M98090_ADLEN_SHIFT, 0, max98090_dapm_event,
1293 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1133 M98090_ADLEN_SHIFT, 0, max98090_shdn_event,
1134 SND_SOC_DAPM_POST_PMU),
1294 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1135 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1295 M98090_ADREN_SHIFT, 0, max98090_dapm_event,
1296 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1136 M98090_ADREN_SHIFT, 0, max98090_shdn_event,
1137 SND_SOC_DAPM_POST_PMU),
1297
1298 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1299 SND_SOC_NOPM, 0, 0),
1300 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1301 SND_SOC_NOPM, 0, 0),
1302
1303 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1304 0, 0, &max98090_lbenl_mux),

--- 11 unchanged lines hidden (view full) ---

1316 0, 0, &max98090_stenl_mux),
1317
1318 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1319 0, 0, &max98090_stenr_mux),
1320
1321 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1322 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1323
1138
1139 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1140 SND_SOC_NOPM, 0, 0),
1141 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1142 SND_SOC_NOPM, 0, 0),
1143
1144 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1145 0, 0, &max98090_lbenl_mux),

--- 11 unchanged lines hidden (view full) ---

1157 0, 0, &max98090_stenl_mux),
1158
1159 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1160 0, 0, &max98090_stenr_mux),
1161
1162 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1163 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1164
1324 SND_SOC_DAPM_DAC_E("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1325 M98090_DALEN_SHIFT, 0, max98090_dapm_event,
1326 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1327 SND_SOC_DAPM_DAC_E("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1328 M98090_DAREN_SHIFT, 0, max98090_dapm_event,
1329 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1165 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1166 M98090_DALEN_SHIFT, 0),
1167 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1168 M98090_DAREN_SHIFT, 0),
1330
1331 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1332 &max98090_left_hp_mixer_controls[0],
1333 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1334
1335 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1336 &max98090_right_hp_mixer_controls[0],
1337 ARRAY_SIZE(max98090_right_hp_mixer_controls)),

--- 18 unchanged lines hidden (view full) ---

1356 &max98090_linmod_mux),
1357
1358 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0,
1359 &max98090_mixhplsel_mux),
1360
1361 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0,
1362 &max98090_mixhprsel_mux),
1363
1169
1170 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1171 &max98090_left_hp_mixer_controls[0],
1172 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1173
1174 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1175 &max98090_right_hp_mixer_controls[0],
1176 ARRAY_SIZE(max98090_right_hp_mixer_controls)),

--- 18 unchanged lines hidden (view full) ---

1195 &max98090_linmod_mux),
1196
1197 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0,
1198 &max98090_mixhplsel_mux),
1199
1200 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0,
1201 &max98090_mixhprsel_mux),
1202
1364 SND_SOC_DAPM_PGA_E("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1365 M98090_HPLEN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1366 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1367 SND_SOC_DAPM_PGA_E("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1368 M98090_HPREN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1369 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1203 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1204 M98090_HPLEN_SHIFT, 0, NULL, 0),
1205 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1206 M98090_HPREN_SHIFT, 0, NULL, 0),
1370
1207
1371 SND_SOC_DAPM_PGA_E("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1372 M98090_SPLEN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1373 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1374 SND_SOC_DAPM_PGA_E("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1375 M98090_SPREN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1376 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1208 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1209 M98090_SPLEN_SHIFT, 0, NULL, 0),
1210 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1211 M98090_SPREN_SHIFT, 0, NULL, 0),
1377
1212
1378 SND_SOC_DAPM_PGA_E("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1379 M98090_RCVLEN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1380 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1381 SND_SOC_DAPM_PGA_E("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1382 M98090_RCVREN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1383 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1213 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1214 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1215 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1216 M98090_RCVREN_SHIFT, 0, NULL, 0),
1384
1385 SND_SOC_DAPM_OUTPUT("HPL"),
1386 SND_SOC_DAPM_OUTPUT("HPR"),
1387 SND_SOC_DAPM_OUTPUT("SPKL"),
1388 SND_SOC_DAPM_OUTPUT("SPKR"),
1389 SND_SOC_DAPM_OUTPUT("RCVL"),
1390 SND_SOC_DAPM_OUTPUT("RCVR"),
1391};
1392
1393static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1394 SND_SOC_DAPM_INPUT("DMIC3"),
1395 SND_SOC_DAPM_INPUT("DMIC4"),
1396
1397 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1217
1218 SND_SOC_DAPM_OUTPUT("HPL"),
1219 SND_SOC_DAPM_OUTPUT("HPR"),
1220 SND_SOC_DAPM_OUTPUT("SPKL"),
1221 SND_SOC_DAPM_OUTPUT("SPKR"),
1222 SND_SOC_DAPM_OUTPUT("RCVL"),
1223 SND_SOC_DAPM_OUTPUT("RCVR"),
1224};
1225
1226static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1227 SND_SOC_DAPM_INPUT("DMIC3"),
1228 SND_SOC_DAPM_INPUT("DMIC4"),
1229
1230 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1398 M98090_DIGMIC3_SHIFT, 0, max98090_dapm_event,
1399 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1231 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1400 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1232 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1401 M98090_DIGMIC4_SHIFT, 0, max98090_dapm_event,
1402 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1233 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1403};
1404
1405static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1406 {"MIC1 Input", NULL, "MIC1"},
1407 {"MIC2 Input", NULL, "MIC2"},
1408
1409 {"DMICL", NULL, "DMICL_ENA"},
1410 {"DMICL", NULL, "DMICR_ENA"},

--- 254 unchanged lines hidden (view full) ---

1665 }
1666
1667 /* Skip configuration when operating as slave */
1668 if (!(snd_soc_component_read32(component, M98090_REG_MASTER_MODE) &
1669 M98090_MAS_MASK)) {
1670 return;
1671 }
1672
1234};
1235
1236static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1237 {"MIC1 Input", NULL, "MIC1"},
1238 {"MIC2 Input", NULL, "MIC2"},
1239
1240 {"DMICL", NULL, "DMICL_ENA"},
1241 {"DMICL", NULL, "DMICR_ENA"},

--- 254 unchanged lines hidden (view full) ---

1496 }
1497
1498 /* Skip configuration when operating as slave */
1499 if (!(snd_soc_component_read32(component, M98090_REG_MASTER_MODE) &
1500 M98090_MAS_MASK)) {
1501 return;
1502 }
1503
1673 /*
1674 * Master mode: no need to save and restore SHDN for the following
1675 * sensitive registers.
1676 */
1677
1678 /* Check for supported PCLK to LRCLK ratios */
1679 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1680 if ((pclk_rates[i] == max98090->sysclk) &&
1681 (lrclk_rates[i] == max98090->lrclk)) {
1682 dev_dbg(component->dev,
1683 "Found supported PCLK to LRCLK rates 0x%x\n",
1684 i + 0x8);
1685

--- 70 unchanged lines hidden (view full) ---

1756
1757 if (fmt != cdata->fmt) {
1758 cdata->fmt = fmt;
1759
1760 regval = 0;
1761 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1762 case SND_SOC_DAIFMT_CBS_CFS:
1763 /* Set to slave mode PLL - MAS mode off */
1504 /* Check for supported PCLK to LRCLK ratios */
1505 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1506 if ((pclk_rates[i] == max98090->sysclk) &&
1507 (lrclk_rates[i] == max98090->lrclk)) {
1508 dev_dbg(component->dev,
1509 "Found supported PCLK to LRCLK rates 0x%x\n",
1510 i + 0x8);
1511

--- 70 unchanged lines hidden (view full) ---

1582
1583 if (fmt != cdata->fmt) {
1584 cdata->fmt = fmt;
1585
1586 regval = 0;
1587 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1588 case SND_SOC_DAIFMT_CBS_CFS:
1589 /* Set to slave mode PLL - MAS mode off */
1764 max98090_shdn_save(max98090);
1765 snd_soc_component_write(component,
1766 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1767 snd_soc_component_write(component,
1768 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1769 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1770 M98090_USE_M1_MASK, 0);
1590 snd_soc_component_write(component,
1591 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1592 snd_soc_component_write(component,
1593 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1594 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1595 M98090_USE_M1_MASK, 0);
1771 max98090_shdn_restore(max98090);
1772 max98090->master = false;
1773 break;
1774 case SND_SOC_DAIFMT_CBM_CFM:
1775 /* Set to master mode */
1776 if (max98090->tdm_slots == 4) {
1777 /* TDM */
1778 regval |= M98090_MAS_MASK |
1779 M98090_BSEL_64;

--- 9 unchanged lines hidden (view full) ---

1789 max98090->master = true;
1790 break;
1791 case SND_SOC_DAIFMT_CBS_CFM:
1792 case SND_SOC_DAIFMT_CBM_CFS:
1793 default:
1794 dev_err(component->dev, "DAI clock mode unsupported");
1795 return -EINVAL;
1796 }
1596 max98090->master = false;
1597 break;
1598 case SND_SOC_DAIFMT_CBM_CFM:
1599 /* Set to master mode */
1600 if (max98090->tdm_slots == 4) {
1601 /* TDM */
1602 regval |= M98090_MAS_MASK |
1603 M98090_BSEL_64;

--- 9 unchanged lines hidden (view full) ---

1613 max98090->master = true;
1614 break;
1615 case SND_SOC_DAIFMT_CBS_CFM:
1616 case SND_SOC_DAIFMT_CBM_CFS:
1617 default:
1618 dev_err(component->dev, "DAI clock mode unsupported");
1619 return -EINVAL;
1620 }
1797 max98090_shdn_save(max98090);
1798 snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval);
1621 snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval);
1799 max98090_shdn_restore(max98090);
1800
1801 regval = 0;
1802 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1803 case SND_SOC_DAIFMT_I2S:
1804 regval |= M98090_DLY_MASK;
1805 break;
1806 case SND_SOC_DAIFMT_LEFT_J:
1807 break;

--- 28 unchanged lines hidden (view full) ---

1836 * This accommodates an inverted logic in the MAX98090 chip
1837 * for Bit Clock Invert (BCI). The inverted logic is only
1838 * seen for the case of TDM mode. The remaining cases have
1839 * normal logic.
1840 */
1841 if (max98090->tdm_slots > 1)
1842 regval ^= M98090_BCI_MASK;
1843
1622
1623 regval = 0;
1624 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1625 case SND_SOC_DAIFMT_I2S:
1626 regval |= M98090_DLY_MASK;
1627 break;
1628 case SND_SOC_DAIFMT_LEFT_J:
1629 break;

--- 28 unchanged lines hidden (view full) ---

1658 * This accommodates an inverted logic in the MAX98090 chip
1659 * for Bit Clock Invert (BCI). The inverted logic is only
1660 * seen for the case of TDM mode. The remaining cases have
1661 * normal logic.
1662 */
1663 if (max98090->tdm_slots > 1)
1664 regval ^= M98090_BCI_MASK;
1665
1844 max98090_shdn_save(max98090);
1845 snd_soc_component_write(component,
1846 M98090_REG_INTERFACE_FORMAT, regval);
1666 snd_soc_component_write(component,
1667 M98090_REG_INTERFACE_FORMAT, regval);
1847 max98090_shdn_restore(max98090);
1848 }
1849
1850 return 0;
1851}
1852
1853static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1854 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1855{
1856 struct snd_soc_component *component = codec_dai->component;
1857 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1858 struct max98090_cdata *cdata;
1668 }
1669
1670 return 0;
1671}
1672
1673static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1674 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1675{
1676 struct snd_soc_component *component = codec_dai->component;
1677 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1678 struct max98090_cdata *cdata;
1859
1860 cdata = &max98090->dai[0];
1861
1862 if (slots < 0 || slots > 4)
1863 return -EINVAL;
1864
1865 max98090->tdm_slots = slots;
1866 max98090->tdm_width = slot_width;
1867
1868 if (max98090->tdm_slots > 1) {
1679 cdata = &max98090->dai[0];
1680
1681 if (slots < 0 || slots > 4)
1682 return -EINVAL;
1683
1684 max98090->tdm_slots = slots;
1685 max98090->tdm_width = slot_width;
1686
1687 if (max98090->tdm_slots > 1) {
1869 max98090_shdn_save(max98090);
1870 /* SLOTL SLOTR SLOTDLY */
1871 snd_soc_component_write(component, M98090_REG_TDM_FORMAT,
1872 0 << M98090_TDM_SLOTL_SHIFT |
1873 1 << M98090_TDM_SLOTR_SHIFT |
1874 0 << M98090_TDM_SLOTDLY_SHIFT);
1875
1876 /* FSW TDM */
1877 snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL,
1878 M98090_TDM_MASK,
1879 M98090_TDM_MASK);
1688 /* SLOTL SLOTR SLOTDLY */
1689 snd_soc_component_write(component, M98090_REG_TDM_FORMAT,
1690 0 << M98090_TDM_SLOTL_SHIFT |
1691 1 << M98090_TDM_SLOTR_SHIFT |
1692 0 << M98090_TDM_SLOTDLY_SHIFT);
1693
1694 /* FSW TDM */
1695 snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL,
1696 M98090_TDM_MASK,
1697 M98090_TDM_MASK);
1880 max98090_shdn_restore(max98090);
1881 }
1882
1883 /*
1884 * Normally advisable to set TDM first, but this permits either order
1885 */
1886 cdata->fmt = 0;
1887 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1888

--- 183 unchanged lines hidden (view full) ---

2072 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
2073 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
2074 break;
2075 }
2076
2077 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
2078 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
2079
1698 }
1699
1700 /*
1701 * Normally advisable to set TDM first, but this permits either order
1702 */
1703 cdata->fmt = 0;
1704 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1705

--- 183 unchanged lines hidden (view full) ---

1889 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1890 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
1891 break;
1892 }
1893
1894 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
1895 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
1896
2080 max98090_shdn_save(max98090);
2081 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
2082 M98090_MICCLK_MASK,
2083 micclk_index << M98090_MICCLK_SHIFT);
2084
2085 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
2086 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
2087 dmic_comp << M98090_DMIC_COMP_SHIFT |
2088 dmic_freq << M98090_DMIC_FREQ_SHIFT);
1897 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
1898 M98090_MICCLK_MASK,
1899 micclk_index << M98090_MICCLK_SHIFT);
1900
1901 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
1902 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
1903 dmic_comp << M98090_DMIC_COMP_SHIFT |
1904 dmic_freq << M98090_DMIC_FREQ_SHIFT);
2089 max98090_shdn_restore(max98090);
2090
2091 return 0;
2092}
2093
2094static int max98090_dai_startup(struct snd_pcm_substream *substream,
2095 struct snd_soc_dai *dai)
2096{
2097 struct snd_soc_component *component = dai->component;

--- 20 unchanged lines hidden (view full) ---

2118 max98090->bclk = snd_soc_params_to_bclk(params);
2119 if (params_channels(params) == 1)
2120 max98090->bclk *= 2;
2121
2122 max98090->lrclk = params_rate(params);
2123
2124 switch (params_width(params)) {
2125 case 16:
1905
1906 return 0;
1907}
1908
1909static int max98090_dai_startup(struct snd_pcm_substream *substream,
1910 struct snd_soc_dai *dai)
1911{
1912 struct snd_soc_component *component = dai->component;

--- 20 unchanged lines hidden (view full) ---

1933 max98090->bclk = snd_soc_params_to_bclk(params);
1934 if (params_channels(params) == 1)
1935 max98090->bclk *= 2;
1936
1937 max98090->lrclk = params_rate(params);
1938
1939 switch (params_width(params)) {
1940 case 16:
2126 max98090_shdn_save(max98090);
2127 snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT,
2128 M98090_WS_MASK, 0);
1941 snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT,
1942 M98090_WS_MASK, 0);
2129 max98090_shdn_restore(max98090);
2130 break;
2131 default:
2132 return -EINVAL;
2133 }
2134
2135 if (max98090->master)
2136 max98090_configure_bclk(component);
2137
2138 cdata->rate = max98090->lrclk;
2139
1943 break;
1944 default:
1945 return -EINVAL;
1946 }
1947
1948 if (max98090->master)
1949 max98090_configure_bclk(component);
1950
1951 cdata->rate = max98090->lrclk;
1952
2140 max98090_shdn_save(max98090);
2141 /* Update filter mode */
2142 if (max98090->lrclk < 24000)
2143 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
2144 M98090_MODE_MASK, 0);
2145 else
2146 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
2147 M98090_MODE_MASK, M98090_MODE_MASK);
2148
2149 /* Update sample rate mode */
2150 if (max98090->lrclk < 50000)
2151 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
2152 M98090_DHF_MASK, 0);
2153 else
2154 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
2155 M98090_DHF_MASK, M98090_DHF_MASK);
1953 /* Update filter mode */
1954 if (max98090->lrclk < 24000)
1955 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1956 M98090_MODE_MASK, 0);
1957 else
1958 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1959 M98090_MODE_MASK, M98090_MODE_MASK);
1960
1961 /* Update sample rate mode */
1962 if (max98090->lrclk < 50000)
1963 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1964 M98090_DHF_MASK, 0);
1965 else
1966 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
1967 M98090_DHF_MASK, M98090_DHF_MASK);
2156 max98090_shdn_restore(max98090);
2157
2158 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
2159 max98090->lrclk);
2160
2161 return 0;
2162}
2163
2164/*

--- 14 unchanged lines hidden (view full) ---

2179 clk_set_rate(max98090->mclk, freq);
2180 }
2181
2182 /* Setup clocks for slave mode, and using the PLL
2183 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
2184 * 0x02 (when master clk is 20MHz to 40MHz)..
2185 * 0x03 (when master clk is 40MHz to 60MHz)..
2186 */
1968
1969 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
1970 max98090->lrclk);
1971
1972 return 0;
1973}
1974
1975/*

--- 14 unchanged lines hidden (view full) ---

1990 clk_set_rate(max98090->mclk, freq);
1991 }
1992
1993 /* Setup clocks for slave mode, and using the PLL
1994 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1995 * 0x02 (when master clk is 20MHz to 40MHz)..
1996 * 0x03 (when master clk is 40MHz to 60MHz)..
1997 */
2187 max98090_shdn_save(max98090);
2188 if ((freq >= 10000000) && (freq <= 20000000)) {
2189 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2190 M98090_PSCLK_DIV1);
2191 max98090->pclk = freq;
2192 } else if ((freq > 20000000) && (freq <= 40000000)) {
2193 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2194 M98090_PSCLK_DIV2);
2195 max98090->pclk = freq >> 1;
2196 } else if ((freq > 40000000) && (freq <= 60000000)) {
2197 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2198 M98090_PSCLK_DIV4);
2199 max98090->pclk = freq >> 2;
2200 } else {
2201 dev_err(component->dev, "Invalid master clock frequency\n");
1998 if ((freq >= 10000000) && (freq <= 20000000)) {
1999 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2000 M98090_PSCLK_DIV1);
2001 max98090->pclk = freq;
2002 } else if ((freq > 20000000) && (freq <= 40000000)) {
2003 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2004 M98090_PSCLK_DIV2);
2005 max98090->pclk = freq >> 1;
2006 } else if ((freq > 40000000) && (freq <= 60000000)) {
2007 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2008 M98090_PSCLK_DIV4);
2009 max98090->pclk = freq >> 2;
2010 } else {
2011 dev_err(component->dev, "Invalid master clock frequency\n");
2202 max98090_shdn_restore(max98090);
2203 return -EINVAL;
2204 }
2012 return -EINVAL;
2013 }
2205 max98090_shdn_restore(max98090);
2206
2207 max98090->sysclk = freq;
2208
2209 return 0;
2210}
2211
2212static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2213{

--- 95 unchanged lines hidden (view full) ---

2309 /*
2310 * As the datasheet suggested, the maximum PLL lock time should be
2311 * 7 msec. The workaround resets the codec softly by toggling SHDN
2312 * off and on if PLL failed to lock for 10 msec. Notably, there is
2313 * no suggested hold time for SHDN off.
2314 */
2315
2316 /* Toggle shutdown OFF then ON */
2014
2015 max98090->sysclk = freq;
2016
2017 return 0;
2018}
2019
2020static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2021{

--- 95 unchanged lines hidden (view full) ---

2117 /*
2118 * As the datasheet suggested, the maximum PLL lock time should be
2119 * 7 msec. The workaround resets the codec softly by toggling SHDN
2120 * off and on if PLL failed to lock for 10 msec. Notably, there is
2121 * no suggested hold time for SHDN off.
2122 */
2123
2124 /* Toggle shutdown OFF then ON */
2317 mutex_lock(&component->card->dapm_mutex);
2318 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2319 M98090_SHDNN_MASK, 0);
2320 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2321 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2125 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2126 M98090_SHDNN_MASK, 0);
2127 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2128 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2322 mutex_unlock(&component->card->dapm_mutex);
2323
2324 for (i = 0; i < 10; ++i) {
2325 /* Give PLL time to lock */
2326 usleep_range(1000, 1200);
2327
2328 /* Check lock status */
2329 pll = snd_soc_component_read32(
2330 component, M98090_REG_DEVICE_STATUS);

--- 306 unchanged lines hidden (view full) ---

2637
2638 /*
2639 * Clear any old interrupts.
2640 * An old interrupt ocurring prior to installing the ISR
2641 * can keep a new interrupt from generating a trigger.
2642 */
2643 snd_soc_component_read32(component, M98090_REG_DEVICE_STATUS);
2644
2129
2130 for (i = 0; i < 10; ++i) {
2131 /* Give PLL time to lock */
2132 usleep_range(1000, 1200);
2133
2134 /* Check lock status */
2135 pll = snd_soc_component_read32(
2136 component, M98090_REG_DEVICE_STATUS);

--- 306 unchanged lines hidden (view full) ---

2443
2444 /*
2445 * Clear any old interrupts.
2446 * An old interrupt ocurring prior to installing the ISR
2447 * can keep a new interrupt from generating a trigger.
2448 */
2449 snd_soc_component_read32(component, M98090_REG_DEVICE_STATUS);
2450
2645 /*
2646 * SHDN should be 0 at the point, no need to save/restore for the
2647 * following registers.
2648 *
2649 * High Performance is default
2650 */
2451 /* High Performance is default */
2651 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2652 M98090_DACHP_MASK,
2653 1 << M98090_DACHP_SHIFT);
2654 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2655 M98090_PERFMODE_MASK,
2656 0 << M98090_PERFMODE_SHIFT);
2657 snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL,
2658 M98090_ADCHP_MASK,
2659 1 << M98090_ADCHP_SHIFT);
2660
2452 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2453 M98090_DACHP_MASK,
2454 1 << M98090_DACHP_SHIFT);
2455 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2456 M98090_PERFMODE_MASK,
2457 0 << M98090_PERFMODE_SHIFT);
2458 snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL,
2459 M98090_ADCHP_MASK,
2460 1 << M98090_ADCHP_SHIFT);
2461
2661 /*
2662 * SHDN should be 0 at the point, no need to save/restore for the
2663 * following registers.
2664 *
2665 * Turn on VCM bandgap reference
2666 */
2462 /* Turn on VCM bandgap reference */
2667 snd_soc_component_write(component, M98090_REG_BIAS_CONTROL,
2668 M98090_VCM_MODE_MASK);
2669
2670 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias);
2671 if (err) {
2672 micbias = M98090_MBVSEL_2V8;
2673 dev_info(component->dev, "use default 2.8v micbias\n");
2674 } else if (micbias > M98090_MBVSEL_2V8) {

--- 15 unchanged lines hidden (view full) ---

2690 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2691
2692 cancel_delayed_work_sync(&max98090->jack_work);
2693 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2694 cancel_work_sync(&max98090->pll_det_disable_work);
2695 max98090->component = NULL;
2696}
2697
2463 snd_soc_component_write(component, M98090_REG_BIAS_CONTROL,
2464 M98090_VCM_MODE_MASK);
2465
2466 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias);
2467 if (err) {
2468 micbias = M98090_MBVSEL_2V8;
2469 dev_info(component->dev, "use default 2.8v micbias\n");
2470 } else if (micbias > M98090_MBVSEL_2V8) {

--- 15 unchanged lines hidden (view full) ---

2486 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2487
2488 cancel_delayed_work_sync(&max98090->jack_work);
2489 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2490 cancel_work_sync(&max98090->pll_det_disable_work);
2491 max98090->component = NULL;
2492}
2493
2494static void max98090_seq_notifier(struct snd_soc_component *component,
2495 enum snd_soc_dapm_type event, int subseq)
2496{
2497 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2498
2499 if (max98090->shdn_pending) {
2500 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2501 M98090_SHDNN_MASK, 0);
2502 msleep(40);
2503 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2504 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2505 max98090->shdn_pending = false;
2506 }
2507}
2508
2698static const struct snd_soc_component_driver soc_component_dev_max98090 = {
2699 .probe = max98090_probe,
2700 .remove = max98090_remove,
2509static const struct snd_soc_component_driver soc_component_dev_max98090 = {
2510 .probe = max98090_probe,
2511 .remove = max98090_remove,
2512 .seq_notifier = max98090_seq_notifier,
2701 .set_bias_level = max98090_set_bias_level,
2702 .idle_bias_on = 1,
2703 .use_pmdown_time = 1,
2704 .endianness = 1,
2705 .non_legacy_dai_naming = 1,
2706};
2707
2708static const struct regmap_config max98090_regmap = {

--- 181 unchanged lines hidden --- 		2513 .set_bias_level = max98090_set_bias_level,
2514 .idle_bias_on = 1,
2515 .use_pmdown_time = 1,
2516 .endianness = 1,
2517 .non_legacy_dai_naming = 1,
2518};
2519
2520static const struct regmap_config max98090_regmap = {

--- 181 unchanged lines hidden ---