es8326.c (14a0a1ec3335ac3945a96437c35465e4a9616b88) es8326.c (a3aa9255d6ccb1bff13c7c98e5d3bf10ba67f92e)
1// SPDX-License-Identifier: GPL-2.0-only
2//
3// es8326.c -- es8326 ALSA SoC audio driver
4// Copyright Everest Semiconductor Co., Ltd
5//
6// Authors: David Yang <yangxiaohua@everest-semi.com>
7//
8

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518 struct snd_soc_component *component = dai->component;
519 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
520 unsigned int offset_l, offset_r;
521
522 if (mute) {
523 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
524 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE,
525 ES8326_MUTE_MASK, ES8326_MUTE);
1// SPDX-License-Identifier: GPL-2.0-only
2//
3// es8326.c -- es8326 ALSA SoC audio driver
4// Copyright Everest Semiconductor Co., Ltd
5//
6// Authors: David Yang <yangxiaohua@everest-semi.com>
7//
8

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518 struct snd_soc_component *component = dai->component;
519 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(component);
520 unsigned int offset_l, offset_r;
521
522 if (mute) {
523 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
524 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE,
525 ES8326_MUTE_MASK, ES8326_MUTE);
526 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xf0);
526 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF,
527 0x30, 0x00);
527 } else {
528 if (!es8326->calibrated) {
529 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_FORCE_CAL);
530 msleep(30);
531 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
532 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l);
533 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r);
534 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c);
535 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l);
536 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r);
537 es8326->calibrated = true;
538 }
528 } else {
529 if (!es8326->calibrated) {
530 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_FORCE_CAL);
531 msleep(30);
532 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_OFF);
533 regmap_read(es8326->regmap, ES8326_HPL_OFFSET_INI, &offset_l);
534 regmap_read(es8326->regmap, ES8326_HPR_OFFSET_INI, &offset_r);
535 regmap_write(es8326->regmap, ES8326_HP_OFFSET_CAL, 0x8c);
536 regmap_write(es8326->regmap, ES8326_HPL_OFFSET_INI, offset_l);
537 regmap_write(es8326->regmap, ES8326_HPR_OFFSET_INI, offset_r);
538 es8326->calibrated = true;
539 }
540 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x01);
541 usleep_range(1000, 5000);
542 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x00);
543 usleep_range(1000, 5000);
544 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x30, 0x20);
545 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x30, 0x30);
539 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1);
546 regmap_write(es8326->regmap, ES8326_HP_DRIVER, 0xa1);
540 regmap_write(es8326->regmap, ES8326_HP_VOL, 0x91);
541 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_ON);
542 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE,
543 ES8326_MUTE_MASK, ~(ES8326_MUTE));
544 }
545 return 0;
546}
547
548static int es8326_set_bias_level(struct snd_soc_component *codec,
549 enum snd_soc_bias_level level)
550{
551 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec);
552 int ret;
553
554 switch (level) {
555 case SND_SOC_BIAS_ON:
556 ret = clk_prepare_enable(es8326->mclk);
557 if (ret)
558 return ret;
559
547 regmap_write(es8326->regmap, ES8326_HP_CAL, ES8326_HP_ON);
548 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE,
549 ES8326_MUTE_MASK, ~(ES8326_MUTE));
550 }
551 return 0;
552}
553
554static int es8326_set_bias_level(struct snd_soc_component *codec,
555 enum snd_soc_bias_level level)
556{
557 struct es8326_priv *es8326 = snd_soc_component_get_drvdata(codec);
558 int ret;
559
560 switch (level) {
561 case SND_SOC_BIAS_ON:
562 ret = clk_prepare_enable(es8326->mclk);
563 if (ret)
564 return ret;
565
560 regmap_update_bits(es8326->regmap, ES8326_DAC_DSM, 0x01, 0x00);
566 regmap_update_bits(es8326->regmap, ES8326_RESET, 0x02, 0x02);
567 usleep_range(5000, 10000);
561 regmap_write(es8326->regmap, ES8326_INTOUT_IO, es8326->interrupt_clk);
562 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO,
563 (ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT));
568 regmap_write(es8326->regmap, ES8326_INTOUT_IO, es8326->interrupt_clk);
569 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO,
570 (ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT));
564 regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x0E);
565 regmap_write(es8326->regmap, ES8326_PGA_PDN, 0x40);
566 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00);
567 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x20);
571 regmap_write(es8326->regmap, ES8326_PGA_PDN, 0x40);
572 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00);
573 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x20);
568
569 regmap_update_bits(es8326->regmap, ES8326_RESET,
570 ES8326_CSM_ON, ES8326_CSM_ON);
574 regmap_update_bits(es8326->regmap, ES8326_RESET, 0x02, 0x00);
571 break;
572 case SND_SOC_BIAS_PREPARE:
573 break;
574 case SND_SOC_BIAS_STANDBY:
575 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b);
575 break;
576 case SND_SOC_BIAS_PREPARE:
577 break;
578 case SND_SOC_BIAS_STANDBY:
579 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x3b);
576 regmap_write(es8326->regmap, ES8326_VMIDSEL, 0x00);
577 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x00);
578 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, ES8326_IO_INPUT);
579 break;
580 case SND_SOC_BIAS_OFF:
581 clk_disable_unprepare(es8326->mclk);
582 break;
583 }
584

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772 es8326->jack_remove_retry = 0;
773 if (es8326->hp == 0) {
774 dev_dbg(comp->dev, "First insert, start OMTP/CTIA type check\n");
775 /*
776 * set auto-check mode, then restart jack_detect_work after 400ms.
777 * Don't report jack status.
778 */
779 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01);
580 regmap_update_bits(es8326->regmap, ES8326_CLK_CTL, 0x20, 0x00);
581 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO, ES8326_IO_INPUT);
582 break;
583 case SND_SOC_BIAS_OFF:
584 clk_disable_unprepare(es8326->mclk);
585 break;
586 }
587

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775 es8326->jack_remove_retry = 0;
776 if (es8326->hp == 0) {
777 dev_dbg(comp->dev, "First insert, start OMTP/CTIA type check\n");
778 /*
779 * set auto-check mode, then restart jack_detect_work after 400ms.
780 * Don't report jack status.
781 */
782 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x01);
783 es8326_enable_micbias(es8326->component);
780 usleep_range(50000, 70000);
781 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00);
782 regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x1f);
783 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x0f, 0x08);
784 queue_delayed_work(system_wq, &es8326->jack_detect_work,
785 msecs_to_jiffies(400));
786 es8326->hp = 1;
787 goto exit;

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815 }
816exit:
817 mutex_unlock(&es8326->lock);
818}
819
820static irqreturn_t es8326_irq(int irq, void *dev_id)
821{
822 struct es8326_priv *es8326 = dev_id;
784 usleep_range(50000, 70000);
785 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00);
786 regmap_write(es8326->regmap, ES8326_SYS_BIAS, 0x1f);
787 regmap_update_bits(es8326->regmap, ES8326_HP_DRIVER_REF, 0x0f, 0x08);
788 queue_delayed_work(system_wq, &es8326->jack_detect_work,
789 msecs_to_jiffies(400));
790 es8326->hp = 1;
791 goto exit;

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819 }
820exit:
821 mutex_unlock(&es8326->lock);
822}
823
824static irqreturn_t es8326_irq(int irq, void *dev_id)
825{
826 struct es8326_priv *es8326 = dev_id;
823 struct snd_soc_component *comp = es8326->component;
824
825 if (!es8326->jack)
826 goto out;
827
827
828 if (!es8326->jack)
829 goto out;
830
828 es8326_enable_micbias(comp);
829
830 if (es8326->jack->status & SND_JACK_HEADSET)
831 queue_delayed_work(system_wq, &es8326->jack_detect_work,
832 msecs_to_jiffies(10));
833 else
834 queue_delayed_work(system_wq, &es8326->jack_detect_work,
835 msecs_to_jiffies(300));
836
837out:

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938
939 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7F);
940 /* select vdda as micbias source */
941 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x23);
942 /* set dac dsmclip = 1 */
943 regmap_write(es8326->regmap, ES8326_DAC_DSM, 0x08);
944 regmap_write(es8326->regmap, ES8326_DAC_VPPSCALE, 0x15);
945
831 if (es8326->jack->status & SND_JACK_HEADSET)
832 queue_delayed_work(system_wq, &es8326->jack_detect_work,
833 msecs_to_jiffies(10));
834 else
835 queue_delayed_work(system_wq, &es8326->jack_detect_work,
836 msecs_to_jiffies(300));
837
838out:

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939
940 regmap_write(es8326->regmap, ES8326_ANA_VSEL, 0x7F);
941 /* select vdda as micbias source */
942 regmap_write(es8326->regmap, ES8326_VMIDLOW, 0x23);
943 /* set dac dsmclip = 1 */
944 regmap_write(es8326->regmap, ES8326_DAC_DSM, 0x08);
945 regmap_write(es8326->regmap, ES8326_DAC_VPPSCALE, 0x15);
946
947 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x80 |
948 ((es8326->version == ES8326_VERSION_B) ?
949 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol) :
950 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol | 0x04)));
951 usleep_range(5000, 10000);
952 es8326_enable_micbias(es8326->component);
953 usleep_range(50000, 70000);
954 regmap_update_bits(es8326->regmap, ES8326_HPDET_TYPE, 0x03, 0x00);
946 regmap_write(es8326->regmap, ES8326_INT_SOURCE,
947 (ES8326_INT_SRC_PIN9 | ES8326_INT_SRC_BUTTON));
948 regmap_write(es8326->regmap, ES8326_INTOUT_IO,
949 es8326->interrupt_clk);
950 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO,
951 (ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT));
952 regmap_write(es8326->regmap, ES8326_SDINOUT23_IO, ES8326_IO_INPUT);
953
954 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00);
955 regmap_write(es8326->regmap, ES8326_RESET, ES8326_CSM_ON);
956 regmap_update_bits(es8326->regmap, ES8326_PGAGAIN, ES8326_MIC_SEL_MASK,
957 ES8326_MIC1_SEL);
958
959 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, ES8326_MUTE_MASK,
960 ES8326_MUTE);
961
955 regmap_write(es8326->regmap, ES8326_INT_SOURCE,
956 (ES8326_INT_SRC_PIN9 | ES8326_INT_SRC_BUTTON));
957 regmap_write(es8326->regmap, ES8326_INTOUT_IO,
958 es8326->interrupt_clk);
959 regmap_write(es8326->regmap, ES8326_SDINOUT1_IO,
960 (ES8326_IO_DMIC_CLK << ES8326_SDINOUT1_SHIFT));
961 regmap_write(es8326->regmap, ES8326_SDINOUT23_IO, ES8326_IO_INPUT);
962
963 regmap_write(es8326->regmap, ES8326_ANA_PDN, 0x00);
964 regmap_write(es8326->regmap, ES8326_RESET, ES8326_CSM_ON);
965 regmap_update_bits(es8326->regmap, ES8326_PGAGAIN, ES8326_MIC_SEL_MASK,
966 ES8326_MIC1_SEL);
967
968 regmap_update_bits(es8326->regmap, ES8326_DAC_MUTE, ES8326_MUTE_MASK,
969 ES8326_MUTE);
970
962 regmap_write(es8326->regmap, ES8326_HPDET_TYPE, 0x80 |
963 ((es8326->version == ES8326_VERSION_B) ?
964 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol) :
965 (ES8326_HP_DET_SRC_PIN9 | es8326->jack_pol | 0x04)));
966 regmap_write(es8326->regmap, ES8326_HP_VOL, 0x11);
967
968 es8326->jack_remove_retry = 0;
969 es8326->hp = 0;
970 return 0;
971}
972
973static int es8326_suspend(struct snd_soc_component *component)
974{

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972 es8326->jack_remove_retry = 0;
973 es8326->hp = 0;
974 return 0;
975}
976
977static int es8326_suspend(struct snd_soc_component *component)
978{

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