da7219.c (9938b04472d5c59f8bd8152a548533a8599596a2) da7219.c (63a450aa4d08ccf4f53e9fa59144e746e2288319)
1/*
2 * da7219.c - DA7219 ALSA SoC Codec Driver
3 *
4 * Copyright (c) 2015 Dialog Semiconductor
5 *
6 * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

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1074 u32 freq_ref;
1075 u64 frac_div;
1076
1077 /* Verify 2MHz - 54MHz MCLK provided, and set input divider */
1078 if (da7219->mclk_rate < 2000000) {
1079 dev_err(codec->dev, "PLL input clock %d below valid range\n",
1080 da7219->mclk_rate);
1081 return -EINVAL;
1/*
2 * da7219.c - DA7219 ALSA SoC Codec Driver
3 *
4 * Copyright (c) 2015 Dialog Semiconductor
5 *
6 * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it

--- 1065 unchanged lines hidden (view full) ---

1074 u32 freq_ref;
1075 u64 frac_div;
1076
1077 /* Verify 2MHz - 54MHz MCLK provided, and set input divider */
1078 if (da7219->mclk_rate < 2000000) {
1079 dev_err(codec->dev, "PLL input clock %d below valid range\n",
1080 da7219->mclk_rate);
1081 return -EINVAL;
1082 } else if (da7219->mclk_rate <= 5000000) {
1083 indiv_bits = DA7219_PLL_INDIV_2_5_MHZ;
1084 indiv = DA7219_PLL_INDIV_2_5_MHZ_VAL;
1085 } else if (da7219->mclk_rate <= 10000000) {
1086 indiv_bits = DA7219_PLL_INDIV_5_10_MHZ;
1087 indiv = DA7219_PLL_INDIV_5_10_MHZ_VAL;
1088 } else if (da7219->mclk_rate <= 20000000) {
1089 indiv_bits = DA7219_PLL_INDIV_10_20_MHZ;
1090 indiv = DA7219_PLL_INDIV_10_20_MHZ_VAL;
1091 } else if (da7219->mclk_rate <= 40000000) {
1092 indiv_bits = DA7219_PLL_INDIV_20_40_MHZ;
1093 indiv = DA7219_PLL_INDIV_20_40_MHZ_VAL;
1082 } else if (da7219->mclk_rate <= 4500000) {
1083 indiv_bits = DA7219_PLL_INDIV_2_TO_4_5_MHZ;
1084 indiv = DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL;
1085 } else if (da7219->mclk_rate <= 9000000) {
1086 indiv_bits = DA7219_PLL_INDIV_4_5_TO_9_MHZ;
1087 indiv = DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL;
1088 } else if (da7219->mclk_rate <= 18000000) {
1089 indiv_bits = DA7219_PLL_INDIV_9_TO_18_MHZ;
1090 indiv = DA7219_PLL_INDIV_9_TO_18_MHZ_VAL;
1091 } else if (da7219->mclk_rate <= 36000000) {
1092 indiv_bits = DA7219_PLL_INDIV_18_TO_36_MHZ;
1093 indiv = DA7219_PLL_INDIV_18_TO_36_MHZ_VAL;
1094 } else if (da7219->mclk_rate <= 54000000) {
1094 } else if (da7219->mclk_rate <= 54000000) {
1095 indiv_bits = DA7219_PLL_INDIV_40_54_MHZ;
1096 indiv = DA7219_PLL_INDIV_40_54_MHZ_VAL;
1095 indiv_bits = DA7219_PLL_INDIV_36_TO_54_MHZ;
1096 indiv = DA7219_PLL_INDIV_36_TO_54_MHZ_VAL;
1097 } else {
1098 dev_err(codec->dev, "PLL input clock %d above valid range\n",
1099 da7219->mclk_rate);
1100 return -EINVAL;
1101 }
1102 freq_ref = (da7219->mclk_rate / indiv);
1103 pll_ctrl = indiv_bits;
1104

--- 864 unchanged lines hidden --- 		1097 } else {
1098 dev_err(codec->dev, "PLL input clock %d above valid range\n",
1099 da7219->mclk_rate);
1100 return -EINVAL;
1101 }
1102 freq_ref = (da7219->mclk_rate / indiv);
1103 pll_ctrl = indiv_bits;
1104

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