cs42l42.c (4ae1d8f911d6fc20baefd5eb061bf6964fa22a32) cs42l42.c (fdbd256175a1e11c1ba827112d56b9a3952e1219)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * cs42l42.c -- CS42L42 ALSA SoC audio driver
4 *
5 * Copyright 2016 Cirrus Logic, Inc.
6 *
7 * Author: James Schulman <james.schulman@cirrus.com>
8 * Author: Brian Austin <brian.austin@cirrus.com>

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673 CS42L42_FSYNC_PULSE_WIDTH_MASK,
674 CS42L42_FRAC0_VAL(fsync - 1) <<
675 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
676 snd_soc_component_update_bits(component,
677 CS42L42_FSYNC_PW_UPPER,
678 CS42L42_FSYNC_PULSE_WIDTH_MASK,
679 CS42L42_FRAC1_VAL(fsync - 1) <<
680 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * cs42l42.c -- CS42L42 ALSA SoC audio driver
4 *
5 * Copyright 2016 Cirrus Logic, Inc.
6 *
7 * Author: James Schulman <james.schulman@cirrus.com>
8 * Author: Brian Austin <brian.austin@cirrus.com>

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673 CS42L42_FSYNC_PULSE_WIDTH_MASK,
674 CS42L42_FRAC0_VAL(fsync - 1) <<
675 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
676 snd_soc_component_update_bits(component,
677 CS42L42_FSYNC_PW_UPPER,
678 CS42L42_FSYNC_PULSE_WIDTH_MASK,
679 CS42L42_FRAC1_VAL(fsync - 1) <<
680 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
681 /* Set the sample rates (96k or lower) */
682 snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
683 CS42L42_FS_EN_MASK,
684 (CS42L42_FS_EN_IASRC_96K |
685 CS42L42_FS_EN_OASRC_96K) <<
686 CS42L42_FS_EN_SHIFT);
687 /* Set the input/output internal MCLK clock ~12 MHz */
688 snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
689 CS42L42_CLK_IASRC_SEL_MASK,
690 CS42L42_CLK_IASRC_SEL_12 <<
691 CS42L42_CLK_IASRC_SEL_SHIFT);
692 snd_soc_component_update_bits(component,
693 CS42L42_OUT_ASRC_CLK,
694 CS42L42_CLK_OASRC_SEL_MASK,
695 CS42L42_CLK_OASRC_SEL_12 <<
696 CS42L42_CLK_OASRC_SEL_SHIFT);
697 if (pll_ratio_table[i].mclk_src_sel == 0) {
698 /* Pass the clock straight through */
699 snd_soc_component_update_bits(component,
700 CS42L42_PLL_CTL1,
701 CS42L42_PLL_START_MASK, 0);
702 } else {
703 /* Configure PLL per table 4-5 */
704 snd_soc_component_update_bits(component,

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751 }
752 return 0;
753 }
754 }
755
756 return -EINVAL;
757}
758
681 if (pll_ratio_table[i].mclk_src_sel == 0) {
682 /* Pass the clock straight through */
683 snd_soc_component_update_bits(component,
684 CS42L42_PLL_CTL1,
685 CS42L42_PLL_START_MASK, 0);
686 } else {
687 /* Configure PLL per table 4-5 */
688 snd_soc_component_update_bits(component,

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735 }
736 return 0;
737 }
738 }
739
740 return -EINVAL;
741}
742
743static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
744{
745 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
746 unsigned int fs;
747
748 /* Don't reconfigure if there is an audio stream running */
749 if (cs42l42->stream_use)
750 return;
751
752 /* SRC MCLK must be as close as possible to 125 * sample rate */
753 if (sample_rate <= 48000)
754 fs = CS42L42_CLK_IASRC_SEL_6;
755 else
756 fs = CS42L42_CLK_IASRC_SEL_12;
757
758 /* Set the sample rates (96k or lower) */
759 snd_soc_component_update_bits(component,
760 CS42L42_FS_RATE_EN,
761 CS42L42_FS_EN_MASK,
762 (CS42L42_FS_EN_IASRC_96K |
763 CS42L42_FS_EN_OASRC_96K) <<
764 CS42L42_FS_EN_SHIFT);
765
766 snd_soc_component_update_bits(component,
767 CS42L42_IN_ASRC_CLK,
768 CS42L42_CLK_IASRC_SEL_MASK,
769 fs << CS42L42_CLK_IASRC_SEL_SHIFT);
770 snd_soc_component_update_bits(component,
771 CS42L42_OUT_ASRC_CLK,
772 CS42L42_CLK_OASRC_SEL_MASK,
773 fs << CS42L42_CLK_OASRC_SEL_SHIFT);
774}
775
759static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
760{
761 struct snd_soc_component *component = codec_dai->component;
762 u32 asp_cfg_val = 0;
763
764 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
765 case SND_SOC_DAIFMT_CBS_CFM:
766 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<

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841 struct snd_pcm_hw_params *params,
842 struct snd_soc_dai *dai)
843{
844 struct snd_soc_component *component = dai->component;
845 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
846 unsigned int channels = params_channels(params);
847 unsigned int width = (params_width(params) / 8) - 1;
848 unsigned int val = 0;
776static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
777{
778 struct snd_soc_component *component = codec_dai->component;
779 u32 asp_cfg_val = 0;
780
781 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
782 case SND_SOC_DAIFMT_CBS_CFM:
783 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<

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858 struct snd_pcm_hw_params *params,
859 struct snd_soc_dai *dai)
860{
861 struct snd_soc_component *component = dai->component;
862 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
863 unsigned int channels = params_channels(params);
864 unsigned int width = (params_width(params) / 8) - 1;
865 unsigned int val = 0;
866 int ret;
849
850 cs42l42->srate = params_rate(params);
851 cs42l42->bclk = snd_soc_params_to_bclk(params);
852
853 /* I2S frame always has 2 channels even for mono audio */
854 if (channels == 1)
855 cs42l42->bclk *= 2;
856

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894 CS42L42_ASP_RX0_CH_EN_MASK,
895 BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
896 BIT(CS42L42_ASP_RX0_CH2_SHIFT));
897 break;
898 default:
899 break;
900 }
901
867
868 cs42l42->srate = params_rate(params);
869 cs42l42->bclk = snd_soc_params_to_bclk(params);
870
871 /* I2S frame always has 2 channels even for mono audio */
872 if (channels == 1)
873 cs42l42->bclk *= 2;
874

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912 CS42L42_ASP_RX0_CH_EN_MASK,
913 BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
914 BIT(CS42L42_ASP_RX0_CH2_SHIFT));
915 break;
916 default:
917 break;
918 }
919
902 return cs42l42_pll_config(component);
920 ret = cs42l42_pll_config(component);
921 if (ret)
922 return ret;
923
924 cs42l42_src_config(component, params_rate(params));
925
926 return 0;
903}
904
905static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
906 int clk_id, unsigned int freq, int dir)
907{
908 struct snd_soc_component *component = dai->component;
909 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
910 int i;

--- 1223 unchanged lines hidden --- 		927}
928
929static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
930 int clk_id, unsigned int freq, int dir)
931{
932 struct snd_soc_component *component = dai->component;
933 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
934 int i;

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