| cs35l45.h (74b14e2850a34740c121cf2758d4181063d4c77c) | cs35l45.h (6c07be8fe92c6b0c24ee1c599601dce3506b83c7) |
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| 1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* 3 * cs35l45.h - CS35L45 ALSA SoC audio driver 4 * 5 * Copyright 2019-2022 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * --- 16 unchanged lines hidden (view full) --- 25#define CS35L45_GLOBAL_ENABLES 0x00002014 26#define CS35L45_BLOCK_ENABLES 0x00002018 27#define CS35L45_BLOCK_ENABLES2 0x0000201C 28#define CS35L45_ERROR_RELEASE 0x00002034 29#define CS35L45_SYNC_GPIO1 0x00002430 30#define CS35L45_INTB_GPIO2_MCLK_REF 0x00002434 31#define CS35L45_GPIO3 0x00002438 32#define CS35L45_PWRMGT_CTL 0x00002900 | 1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* 3 * cs35l45.h - CS35L45 ALSA SoC audio driver 4 * 5 * Copyright 2019-2022 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * --- 16 unchanged lines hidden (view full) --- 25#define CS35L45_GLOBAL_ENABLES 0x00002014 26#define CS35L45_BLOCK_ENABLES 0x00002018 27#define CS35L45_BLOCK_ENABLES2 0x0000201C 28#define CS35L45_ERROR_RELEASE 0x00002034 29#define CS35L45_SYNC_GPIO1 0x00002430 30#define CS35L45_INTB_GPIO2_MCLK_REF 0x00002434 31#define CS35L45_GPIO3 0x00002438 32#define CS35L45_PWRMGT_CTL 0x00002900 |
| 33#define CS35L45_WAKESRC_CTL 0x00002904 34#define CS35L45_WKI2C_CTL 0x00002908 35#define CS35L45_PWRMGT_STS 0x0000290C |
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| 33#define CS35L45_REFCLK_INPUT 0x00002C04 34#define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C 35#define CS35L45_BOOST_CCM_CFG 0x00003808 36#define CS35L45_BOOST_DCM_CFG 0x0000380C 37#define CS35L45_BOOST_OV_CFG 0x0000382C 38#define CS35L45_ASP_ENABLES1 0x00004800 39#define CS35L45_ASP_CONTROL1 0x00004804 40#define CS35L45_ASP_CONTROL2 0x00004808 --- 302 unchanged lines hidden (view full) --- 343#define CS35L45_PCM_SRC_INTERPOLATOR 0x40 344#define CS35L45_PCM_SRC_IL_TARGET 0x48 345 346#define CS35L45_RESET_HOLD_US 2000 347#define CS35L45_RESET_US 2000 348#define CS35L45_POST_GLOBAL_EN_US 5000 349#define CS35L45_PRE_GLOBAL_DIS_US 3000 350 | 36#define CS35L45_REFCLK_INPUT 0x00002C04 37#define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C 38#define CS35L45_BOOST_CCM_CFG 0x00003808 39#define CS35L45_BOOST_DCM_CFG 0x0000380C 40#define CS35L45_BOOST_OV_CFG 0x0000382C 41#define CS35L45_ASP_ENABLES1 0x00004800 42#define CS35L45_ASP_CONTROL1 0x00004804 43#define CS35L45_ASP_CONTROL2 0x00004808 --- 302 unchanged lines hidden (view full) --- 346#define CS35L45_PCM_SRC_INTERPOLATOR 0x40 347#define CS35L45_PCM_SRC_IL_TARGET 0x48 348 349#define CS35L45_RESET_HOLD_US 2000 350#define CS35L45_RESET_US 2000 351#define CS35L45_POST_GLOBAL_EN_US 5000 352#define CS35L45_PRE_GLOBAL_DIS_US 3000 353 |
| 354/* WAKESRC_CTL */ 355#define CS35L45_WKSRC_SYNC_GPIO1 BIT(0) 356#define CS35L45_WKSRC_INT_GPIO2 BIT(1) 357#define CS35L45_WKSRC_GPIO3 BIT(2) 358#define CS35L45_WKSRC_SPI BIT(3) 359#define CS35L45_WKSRC_I2C BIT(4) 360#define CS35L45_UPDT_WKCTL_SHIFT 15 361#define CS35L45_UPDT_WKCTL_MASK BIT(15) 362#define CS35L45_WKSRC_EN_SHIFT 8 363#define CS35L45_WKSRC_EN_MASK GENMASK(12, 8) 364#define CS35L45_WKSRC_POL_SHIFT 0 365#define CS35L45_WKSRC_POL_MASK GENMASK(3, 0) 366 367/* WAKEI2C_CTL */ 368#define CS35L45_UPDT_WKI2C_SHIFT 15 369#define CS35L45_UPDT_WKI2C_MASK BIT(15) 370#define CS35L45_WKI2C_ADDR_SHIFT 0 371#define CS35L45_WKI2C_ADDR_MASK GENMASK(6, 0) 372 |
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| 351#define CS35L45_SPI_MAX_FREQ 4000000 352 353enum cs35l45_cspl_mboxstate { 354 CSPL_MBOX_STS_RUNNING = 0, 355 CSPL_MBOX_STS_PAUSED = 1, 356 CSPL_MBOX_STS_RDY_FOR_REINIT = 2, 357 CSPL_MBOX_STS_HIBERNATE = 3, 358}; --- 5 unchanged lines hidden (view full) --- 364 CSPL_MBOX_CMD_REINIT = 3, 365 CSPL_MBOX_CMD_STOP_PRE_REINIT = 4, 366 CSPL_MBOX_CMD_HIBERNATE = 5, 367 CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6, 368 CSPL_MBOX_CMD_UNKNOWN_CMD = -1, 369 CSPL_MBOX_CMD_INVALID_SEQUENCE = -2, 370}; 371 | 373#define CS35L45_SPI_MAX_FREQ 4000000 374 375enum cs35l45_cspl_mboxstate { 376 CSPL_MBOX_STS_RUNNING = 0, 377 CSPL_MBOX_STS_PAUSED = 1, 378 CSPL_MBOX_STS_RDY_FOR_REINIT = 2, 379 CSPL_MBOX_STS_HIBERNATE = 3, 380}; --- 5 unchanged lines hidden (view full) --- 386 CSPL_MBOX_CMD_REINIT = 3, 387 CSPL_MBOX_CMD_STOP_PRE_REINIT = 4, 388 CSPL_MBOX_CMD_HIBERNATE = 5, 389 CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6, 390 CSPL_MBOX_CMD_UNKNOWN_CMD = -1, 391 CSPL_MBOX_CMD_INVALID_SEQUENCE = -2, 392}; 393 |
| 394enum control_bus_type { 395 CONTROL_BUS_I2C = 0, 396 CONTROL_BUS_SPI = 1, 397}; 398 |
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| 372#define CS35L45_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 373 SNDRV_PCM_FMTBIT_S24_3LE| \ 374 SNDRV_PCM_FMTBIT_S24_LE) 375 376#define CS35L45_RATES (SNDRV_PCM_RATE_44100 | \ 377 SNDRV_PCM_RATE_48000 | \ 378 SNDRV_PCM_RATE_88200 | \ 379 SNDRV_PCM_RATE_96000) --- 54 unchanged lines hidden (view full) --- 434 struct regulator *vdd_batt; 435 struct regulator *vdd_a; 436 bool initialized; 437 bool sysclk_set; 438 u8 slot_width; 439 u8 slot_count; 440 int irq_invert; 441 int irq; | 399#define CS35L45_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 400 SNDRV_PCM_FMTBIT_S24_3LE| \ 401 SNDRV_PCM_FMTBIT_S24_LE) 402 403#define CS35L45_RATES (SNDRV_PCM_RATE_44100 | \ 404 SNDRV_PCM_RATE_48000 | \ 405 SNDRV_PCM_RATE_88200 | \ 406 SNDRV_PCM_RATE_96000) --- 54 unchanged lines hidden (view full) --- 461 struct regulator *vdd_batt; 462 struct regulator *vdd_a; 463 bool initialized; 464 bool sysclk_set; 465 u8 slot_width; 466 u8 slot_count; 467 int irq_invert; 468 int irq; |
| 469 unsigned int i2c_addr; 470 enum control_bus_type bus_type; |
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| 442 struct regmap_irq_chip_data *irq_data; 443}; 444 445extern const struct dev_pm_ops cs35l45_pm_ops; 446extern const struct regmap_config cs35l45_i2c_regmap; 447extern const struct regmap_config cs35l45_spi_regmap; 448int cs35l45_apply_patch(struct cs35l45_private *cs35l45); 449unsigned int cs35l45_get_clk_freq_id(unsigned int freq); 450int cs35l45_probe(struct cs35l45_private *cs35l45); 451void cs35l45_remove(struct cs35l45_private *cs35l45); 452 453#endif /* CS35L45_H */ | 471 struct regmap_irq_chip_data *irq_data; 472}; 473 474extern const struct dev_pm_ops cs35l45_pm_ops; 475extern const struct regmap_config cs35l45_i2c_regmap; 476extern const struct regmap_config cs35l45_spi_regmap; 477int cs35l45_apply_patch(struct cs35l45_private *cs35l45); 478unsigned int cs35l45_get_clk_freq_id(unsigned int freq); 479int cs35l45_probe(struct cs35l45_private *cs35l45); 480void cs35l45_remove(struct cs35l45_private *cs35l45); 481 482#endif /* CS35L45_H */ |