| cs35l45.h (4f2c0a4acffbec01079c28f839422e64ddeff004) | cs35l45.h (fa8c052b4c614aa1d2d60e5c9f40e9d885bf9511) |
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| 1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* 3 * cs35l45.h - CS35L45 ALSA SoC audio driver 4 * 5 * Copyright 2019-2022 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * 9 */ 10 11#ifndef CS35L45_H 12#define CS35L45_H 13 14#include <linux/pm_runtime.h> 15#include <linux/regmap.h> 16#include <linux/regulator/consumer.h> | 1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* 3 * cs35l45.h - CS35L45 ALSA SoC audio driver 4 * 5 * Copyright 2019-2022 Cirrus Logic, Inc. 6 * 7 * Author: James Schulman <james.schulman@cirrus.com> 8 * 9 */ 10 11#ifndef CS35L45_H 12#define CS35L45_H 13 14#include <linux/pm_runtime.h> 15#include <linux/regmap.h> 16#include <linux/regulator/consumer.h> |
| 17#include <dt-bindings/sound/cs35l45.h> |
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| 17 18#define CS35L45_DEVID 0x00000000 19#define CS35L45_REVID 0x00000004 20#define CS35L45_RELID 0x0000000C 21#define CS35L45_OTPID 0x00000010 22#define CS35L45_SFT_RESET 0x00000020 23#define CS35L45_GLOBAL_ENABLES 0x00002014 24#define CS35L45_BLOCK_ENABLES 0x00002018 25#define CS35L45_BLOCK_ENABLES2 0x0000201C 26#define CS35L45_ERROR_RELEASE 0x00002034 | 18 19#define CS35L45_DEVID 0x00000000 20#define CS35L45_REVID 0x00000004 21#define CS35L45_RELID 0x0000000C 22#define CS35L45_OTPID 0x00000010 23#define CS35L45_SFT_RESET 0x00000020 24#define CS35L45_GLOBAL_ENABLES 0x00002014 25#define CS35L45_BLOCK_ENABLES 0x00002018 26#define CS35L45_BLOCK_ENABLES2 0x0000201C 27#define CS35L45_ERROR_RELEASE 0x00002034 |
| 28#define CS35L45_SYNC_GPIO1 0x00002430 29#define CS35L45_INTB_GPIO2_MCLK_REF 0x00002434 30#define CS35L45_GPIO3 0x00002438 |
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| 27#define CS35L45_REFCLK_INPUT 0x00002C04 28#define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C 29#define CS35L45_BOOST_CCM_CFG 0x00003808 30#define CS35L45_BOOST_DCM_CFG 0x0000380C 31#define CS35L45_BOOST_OV_CFG 0x0000382C 32#define CS35L45_ASP_ENABLES1 0x00004800 33#define CS35L45_ASP_CONTROL1 0x00004804 34#define CS35L45_ASP_CONTROL2 0x00004808 --- 8 unchanged lines hidden (view full) --- 43#define CS35L45_ASPTX2_INPUT 0x00004C24 44#define CS35L45_ASPTX3_INPUT 0x00004C28 45#define CS35L45_ASPTX4_INPUT 0x00004C2C 46#define CS35L45_ASPTX5_INPUT 0x00004C30 47#define CS35L45_LDPM_CONFIG 0x00006404 48#define CS35L45_AMP_PCM_CONTROL 0x00007000 49#define CS35L45_AMP_PCM_HPF_TST 0x00007004 50#define CS35L45_IRQ1_EINT_4 0x0000E01C | 31#define CS35L45_REFCLK_INPUT 0x00002C04 32#define CS35L45_GLOBAL_SAMPLE_RATE 0x00002C0C 33#define CS35L45_BOOST_CCM_CFG 0x00003808 34#define CS35L45_BOOST_DCM_CFG 0x0000380C 35#define CS35L45_BOOST_OV_CFG 0x0000382C 36#define CS35L45_ASP_ENABLES1 0x00004800 37#define CS35L45_ASP_CONTROL1 0x00004804 38#define CS35L45_ASP_CONTROL2 0x00004808 --- 8 unchanged lines hidden (view full) --- 47#define CS35L45_ASPTX2_INPUT 0x00004C24 48#define CS35L45_ASPTX3_INPUT 0x00004C28 49#define CS35L45_ASPTX4_INPUT 0x00004C2C 50#define CS35L45_ASPTX5_INPUT 0x00004C30 51#define CS35L45_LDPM_CONFIG 0x00006404 52#define CS35L45_AMP_PCM_CONTROL 0x00007000 53#define CS35L45_AMP_PCM_HPF_TST 0x00007004 54#define CS35L45_IRQ1_EINT_4 0x0000E01C |
| 51#define CS35L45_LASTREG 0x0000E01C 52 | 55#define CS35L45_GPIO_STATUS1 0x0000F000 56#define CS35L45_GPIO1_CTRL1 0x0000F008 57#define CS35L45_GPIO2_CTRL1 0x0000F00C 58#define CS35L45_GPIO3_CTRL1 0x0000F010 59#define CS35L45_LASTREG 0x0000F010 |
| 53/* SFT_RESET */ 54#define CS35L45_SOFT_RESET_TRIGGER 0x5A000000 55 56/* GLOBAL_ENABLES */ 57#define CS35L45_GLOBAL_EN_SHIFT 0 58#define CS35L45_GLOBAL_EN_MASK BIT(0) 59 60/* BLOCK_ENABLES */ --- 99 unchanged lines hidden (view full) --- 160#define CS35l45_HPF_DEFAULT 0x00000000 161#define CS35L45_HPF_44P1 0x000108BD 162#define CS35L45_HPF_88P2 0x0001045F 163 164/* IRQ1_EINT_4 */ 165#define CS35L45_OTP_BOOT_DONE_STS_MASK BIT(1) 166#define CS35L45_OTP_BUSY_MASK BIT(0) 167 | 60/* SFT_RESET */ 61#define CS35L45_SOFT_RESET_TRIGGER 0x5A000000 62 63/* GLOBAL_ENABLES */ 64#define CS35L45_GLOBAL_EN_SHIFT 0 65#define CS35L45_GLOBAL_EN_MASK BIT(0) 66 67/* BLOCK_ENABLES */ --- 99 unchanged lines hidden (view full) --- 167#define CS35l45_HPF_DEFAULT 0x00000000 168#define CS35L45_HPF_44P1 0x000108BD 169#define CS35L45_HPF_88P2 0x0001045F 170 171/* IRQ1_EINT_4 */ 172#define CS35L45_OTP_BOOT_DONE_STS_MASK BIT(1) 173#define CS35L45_OTP_BUSY_MASK BIT(0) 174 |
| 175/* GPIOX_CTRL1 */ 176#define CS35L45_GPIO_DIR_SHIFT 31 177#define CS35L45_GPIO_DIR_MASK BIT(31) 178#define CS35L45_GPIO_LVL_SHIFT 15 179#define CS35L45_GPIO_LVL_MASK BIT(15) 180#define CS35L45_GPIO_OP_CFG_SHIFT 14 181#define CS35L45_GPIO_OP_CFG_MASK BIT(14) 182#define CS35L45_GPIO_POL_SHIFT 12 183#define CS35L45_GPIO_POL_MASK BIT(12) 184 185/* SYNC_GPIO1, INTB_GPIO2_MCLK_REF, GPIO3 */ 186#define CS35L45_GPIO_CTRL_SHIFT 20 187#define CS35L45_GPIO_CTRL_MASK GENMASK(22, 20) 188#define CS35L45_GPIO_INVERT_SHIFT 19 189#define CS35L45_GPIO_INVERT_MASK BIT(19) 190 |
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| 168/* Mixer sources */ 169#define CS35L45_PCM_SRC_MASK 0x7F 170#define CS35L45_PCM_SRC_ZERO 0x00 171#define CS35L45_PCM_SRC_ASP_RX1 0x08 172#define CS35L45_PCM_SRC_ASP_RX2 0x09 173#define CS35L45_PCM_SRC_VMON 0x18 174#define CS35L45_PCM_SRC_IMON 0x19 175#define CS35L45_PCM_SRC_ERR_VOL 0x20 --- 42 unchanged lines hidden --- | 191/* Mixer sources */ 192#define CS35L45_PCM_SRC_MASK 0x7F 193#define CS35L45_PCM_SRC_ZERO 0x00 194#define CS35L45_PCM_SRC_ASP_RX1 0x08 195#define CS35L45_PCM_SRC_ASP_RX2 0x09 196#define CS35L45_PCM_SRC_VMON 0x18 197#define CS35L45_PCM_SRC_IMON 0x19 198#define CS35L45_PCM_SRC_ERR_VOL 0x20 --- 42 unchanged lines hidden --- |