cs35l45-tables.c (50501936288d6a29d7ef78f25d00e33240fad45f) cs35l45-tables.c (f9ad18b24c24b06820fcd72975f1b08b1d466168)
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
1// SPDX-License-Identifier: GPL-2.0
2//
3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
4//
5// Copyright 2019-2022 Cirrus Logic, Inc.
6//
7// Author: James Schulman <james.schulman@cirrus.com>
8
9#include <linux/module.h>

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250 .reg_stride = 4,
251 .reg_format_endian = REGMAP_ENDIAN_BIG,
252 .val_format_endian = REGMAP_ENDIAN_BIG,
253 .max_register = CS35L45_LASTREG,
254 .reg_defaults = cs35l45_defaults,
255 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
256 .volatile_reg = cs35l45_volatile_reg,
257 .readable_reg = cs35l45_readable_reg,
2//
3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
4//
5// Copyright 2019-2022 Cirrus Logic, Inc.
6//
7// Author: James Schulman <james.schulman@cirrus.com>
8
9#include <linux/module.h>

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250 .reg_stride = 4,
251 .reg_format_endian = REGMAP_ENDIAN_BIG,
252 .val_format_endian = REGMAP_ENDIAN_BIG,
253 .max_register = CS35L45_LASTREG,
254 .reg_defaults = cs35l45_defaults,
255 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
256 .volatile_reg = cs35l45_volatile_reg,
257 .readable_reg = cs35l45_readable_reg,
258 .cache_type = REGCACHE_RBTREE,
258 .cache_type = REGCACHE_MAPLE,
259};
260EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45);
261
262const struct regmap_config cs35l45_spi_regmap = {
263 .reg_bits = 32,
264 .val_bits = 32,
265 .pad_bits = 16,
266 .reg_stride = 4,
267 .reg_format_endian = REGMAP_ENDIAN_BIG,
268 .val_format_endian = REGMAP_ENDIAN_BIG,
269 .max_register = CS35L45_LASTREG,
270 .reg_defaults = cs35l45_defaults,
271 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
272 .volatile_reg = cs35l45_volatile_reg,
273 .readable_reg = cs35l45_readable_reg,
259};
260EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45);
261
262const struct regmap_config cs35l45_spi_regmap = {
263 .reg_bits = 32,
264 .val_bits = 32,
265 .pad_bits = 16,
266 .reg_stride = 4,
267 .reg_format_endian = REGMAP_ENDIAN_BIG,
268 .val_format_endian = REGMAP_ENDIAN_BIG,
269 .max_register = CS35L45_LASTREG,
270 .reg_defaults = cs35l45_defaults,
271 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
272 .volatile_reg = cs35l45_volatile_reg,
273 .readable_reg = cs35l45_readable_reg,
274 .cache_type = REGCACHE_RBTREE,
274 .cache_type = REGCACHE_MAPLE,
275};
276EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45);
277
278static const struct {
279 u8 cfg_id;
280 u32 freq;
281} cs35l45_pll_refclk_freq[] = {
282 { 0x0C, 128000 },

--- 47 unchanged lines hidden --- 		275};
276EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45);
277
278static const struct {
279 u8 cfg_id;
280 u32 freq;
281} cs35l45_pll_refclk_freq[] = {
282 { 0x0C, 128000 },

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