cs35l45-tables.c (4dac6f5abc02ffeeb10459c575aba2343363d4ee) | cs35l45-tables.c (926505cf14258376c3cd244e891c7d739a2a049a) |
---|---|
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2// 3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver 4// 5// Copyright 2019-2022 Cirrus Logic, Inc. 6// 7// Author: James Schulman <james.schulman@cirrus.com> 8 --- 24 unchanged lines hidden (view full) --- 33 { CS35L45_ERROR_RELEASE, 0x00200000 }, 34}; 35 36int cs35l45_apply_patch(struct cs35l45_private *cs35l45) 37{ 38 return regmap_register_patch(cs35l45->regmap, cs35l45_patch, 39 ARRAY_SIZE(cs35l45_patch)); 40} | 1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2// 3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver 4// 5// Copyright 2019-2022 Cirrus Logic, Inc. 6// 7// Author: James Schulman <james.schulman@cirrus.com> 8 --- 24 unchanged lines hidden (view full) --- 33 { CS35L45_ERROR_RELEASE, 0x00200000 }, 34}; 35 36int cs35l45_apply_patch(struct cs35l45_private *cs35l45) 37{ 38 return regmap_register_patch(cs35l45->regmap, cs35l45_patch, 39 ARRAY_SIZE(cs35l45_patch)); 40} |
41EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45_TABLES); | 41EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45); |
42 43static const struct reg_default cs35l45_defaults[] = { 44 { CS35L45_BLOCK_ENABLES, 0x00003323 }, 45 { CS35L45_BLOCK_ENABLES2, 0x00000010 }, 46 { CS35L45_REFCLK_INPUT, 0x00000510 }, 47 { CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 }, 48 { CS35L45_ASP_ENABLES1, 0x00000000 }, 49 { CS35L45_ASP_CONTROL1, 0x00000028 }, --- 71 unchanged lines hidden (view full) --- 121 .val_format_endian = REGMAP_ENDIAN_BIG, 122 .max_register = CS35L45_LASTREG, 123 .reg_defaults = cs35l45_defaults, 124 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 125 .volatile_reg = cs35l45_volatile_reg, 126 .readable_reg = cs35l45_readable_reg, 127 .cache_type = REGCACHE_RBTREE, 128}; | 42 43static const struct reg_default cs35l45_defaults[] = { 44 { CS35L45_BLOCK_ENABLES, 0x00003323 }, 45 { CS35L45_BLOCK_ENABLES2, 0x00000010 }, 46 { CS35L45_REFCLK_INPUT, 0x00000510 }, 47 { CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 }, 48 { CS35L45_ASP_ENABLES1, 0x00000000 }, 49 { CS35L45_ASP_CONTROL1, 0x00000028 }, --- 71 unchanged lines hidden (view full) --- 121 .val_format_endian = REGMAP_ENDIAN_BIG, 122 .max_register = CS35L45_LASTREG, 123 .reg_defaults = cs35l45_defaults, 124 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 125 .volatile_reg = cs35l45_volatile_reg, 126 .readable_reg = cs35l45_readable_reg, 127 .cache_type = REGCACHE_RBTREE, 128}; |
129EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45_TABLES); | 129EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45); |
130 131const struct regmap_config cs35l45_spi_regmap = { 132 .reg_bits = 32, 133 .val_bits = 32, 134 .pad_bits = 16, 135 .reg_stride = 4, 136 .reg_format_endian = REGMAP_ENDIAN_BIG, 137 .val_format_endian = REGMAP_ENDIAN_BIG, 138 .max_register = CS35L45_LASTREG, 139 .reg_defaults = cs35l45_defaults, 140 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 141 .volatile_reg = cs35l45_volatile_reg, 142 .readable_reg = cs35l45_readable_reg, 143 .cache_type = REGCACHE_RBTREE, 144}; | 130 131const struct regmap_config cs35l45_spi_regmap = { 132 .reg_bits = 32, 133 .val_bits = 32, 134 .pad_bits = 16, 135 .reg_stride = 4, 136 .reg_format_endian = REGMAP_ENDIAN_BIG, 137 .val_format_endian = REGMAP_ENDIAN_BIG, 138 .max_register = CS35L45_LASTREG, 139 .reg_defaults = cs35l45_defaults, 140 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults), 141 .volatile_reg = cs35l45_volatile_reg, 142 .readable_reg = cs35l45_readable_reg, 143 .cache_type = REGCACHE_RBTREE, 144}; |
145EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45_TABLES); | 145EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45); |
146 147static const struct { 148 u8 cfg_id; 149 u32 freq; 150} cs35l45_pll_refclk_freq[] = { 151 { 0x0C, 128000 }, 152 { 0x0F, 256000 }, 153 { 0x11, 384000 }, --- 36 unchanged lines hidden (view full) --- 190 191 for (i = 0; i < ARRAY_SIZE(cs35l45_pll_refclk_freq); ++i) { 192 if (cs35l45_pll_refclk_freq[i].freq == freq) 193 return cs35l45_pll_refclk_freq[i].cfg_id; 194 } 195 196 return -EINVAL; 197} | 146 147static const struct { 148 u8 cfg_id; 149 u32 freq; 150} cs35l45_pll_refclk_freq[] = { 151 { 0x0C, 128000 }, 152 { 0x0F, 256000 }, 153 { 0x11, 384000 }, --- 36 unchanged lines hidden (view full) --- 190 191 for (i = 0; i < ARRAY_SIZE(cs35l45_pll_refclk_freq); ++i) { 192 if (cs35l45_pll_refclk_freq[i].freq == freq) 193 return cs35l45_pll_refclk_freq[i].cfg_id; 194 } 195 196 return -EINVAL; 197} |
198EXPORT_SYMBOL_NS_GPL(cs35l45_get_clk_freq_id, SND_SOC_CS35L45_TABLES); | 198EXPORT_SYMBOL_NS_GPL(cs35l45_get_clk_freq_id, SND_SOC_CS35L45); |