cs35l45-tables.c (34069d12e239ae8f36dd96c378e4622fb1c42a76) cs35l45-tables.c (18050443b9fc4e809c077fbf0967349410e86117)
1// SPDX-License-Identifier: GPL-2.0
2//
3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
4//
5// Copyright 2019-2022 Cirrus Logic, Inc.
6//
7// Author: James Schulman <james.schulman@cirrus.com>
8

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86 { CS35L45_DSP1RX2_INPUT, 0x00000009 },
87 { CS35L45_DSP1RX3_INPUT, 0x00000018 },
88 { CS35L45_DSP1RX4_INPUT, 0x00000019 },
89 { CS35L45_DSP1RX5_INPUT, 0x00000020 },
90 { CS35L45_DSP1RX6_INPUT, 0x00000028 },
91 { CS35L45_DSP1RX7_INPUT, 0x0000003A },
92 { CS35L45_DSP1RX8_INPUT, 0x00000028 },
93 { CS35L45_AMP_PCM_CONTROL, 0x00100000 },
1// SPDX-License-Identifier: GPL-2.0
2//
3// cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
4//
5// Copyright 2019-2022 Cirrus Logic, Inc.
6//
7// Author: James Schulman <james.schulman@cirrus.com>
8

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86 { CS35L45_DSP1RX2_INPUT, 0x00000009 },
87 { CS35L45_DSP1RX3_INPUT, 0x00000018 },
88 { CS35L45_DSP1RX4_INPUT, 0x00000019 },
89 { CS35L45_DSP1RX5_INPUT, 0x00000020 },
90 { CS35L45_DSP1RX6_INPUT, 0x00000028 },
91 { CS35L45_DSP1RX7_INPUT, 0x0000003A },
92 { CS35L45_DSP1RX8_INPUT, 0x00000028 },
93 { CS35L45_AMP_PCM_CONTROL, 0x00100000 },
94 { CS35L45_AMP_GAIN, 0x00002300 },
94 { CS35L45_IRQ1_CFG, 0x00000000 },
95 { CS35L45_IRQ1_MASK_1, 0xBFEFFFBF },
96 { CS35L45_IRQ1_MASK_2, 0xFFFFFFFF },
97 { CS35L45_IRQ1_MASK_3, 0xFFFF87FF },
98 { CS35L45_IRQ1_MASK_4, 0xF8FFFFFF },
99 { CS35L45_IRQ1_MASK_5, 0x0EF80000 },
100 { CS35L45_IRQ1_MASK_6, 0x00000000 },
101 { CS35L45_IRQ1_MASK_7, 0xFFFFFF78 },

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151 case CS35L45_DSP1RX1_INPUT:
152 case CS35L45_DSP1RX2_INPUT:
153 case CS35L45_DSP1RX3_INPUT:
154 case CS35L45_DSP1RX4_INPUT:
155 case CS35L45_DSP1RX5_INPUT:
156 case CS35L45_DSP1RX6_INPUT:
157 case CS35L45_DSP1RX7_INPUT:
158 case CS35L45_DSP1RX8_INPUT:
95 { CS35L45_IRQ1_CFG, 0x00000000 },
96 { CS35L45_IRQ1_MASK_1, 0xBFEFFFBF },
97 { CS35L45_IRQ1_MASK_2, 0xFFFFFFFF },
98 { CS35L45_IRQ1_MASK_3, 0xFFFF87FF },
99 { CS35L45_IRQ1_MASK_4, 0xF8FFFFFF },
100 { CS35L45_IRQ1_MASK_5, 0x0EF80000 },
101 { CS35L45_IRQ1_MASK_6, 0x00000000 },
102 { CS35L45_IRQ1_MASK_7, 0xFFFFFF78 },

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152 case CS35L45_DSP1RX1_INPUT:
153 case CS35L45_DSP1RX2_INPUT:
154 case CS35L45_DSP1RX3_INPUT:
155 case CS35L45_DSP1RX4_INPUT:
156 case CS35L45_DSP1RX5_INPUT:
157 case CS35L45_DSP1RX6_INPUT:
158 case CS35L45_DSP1RX7_INPUT:
159 case CS35L45_DSP1RX8_INPUT:
160 case CS35L45_HVLV_CONFIG:
159 case CS35L45_AMP_PCM_CONTROL:
161 case CS35L45_AMP_PCM_CONTROL:
162 case CS35L45_AMP_GAIN:
160 case CS35L45_AMP_PCM_HPF_TST:
161 case CS35L45_IRQ1_CFG:
162 case CS35L45_IRQ1_STATUS:
163 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
164 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
165 case CS35L45_IRQ1_MASK_1 ... CS35L45_IRQ1_MASK_18:
166 case CS35L45_GPIO_STATUS1:
167 case CS35L45_GPIO1_CTRL1:

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250 .reg_stride = 4,
251 .reg_format_endian = REGMAP_ENDIAN_BIG,
252 .val_format_endian = REGMAP_ENDIAN_BIG,
253 .max_register = CS35L45_LASTREG,
254 .reg_defaults = cs35l45_defaults,
255 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
256 .volatile_reg = cs35l45_volatile_reg,
257 .readable_reg = cs35l45_readable_reg,
163 case CS35L45_AMP_PCM_HPF_TST:
164 case CS35L45_IRQ1_CFG:
165 case CS35L45_IRQ1_STATUS:
166 case CS35L45_IRQ1_EINT_1 ... CS35L45_IRQ1_EINT_18:
167 case CS35L45_IRQ1_STS_1 ... CS35L45_IRQ1_STS_18:
168 case CS35L45_IRQ1_MASK_1 ... CS35L45_IRQ1_MASK_18:
169 case CS35L45_GPIO_STATUS1:
170 case CS35L45_GPIO1_CTRL1:

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253 .reg_stride = 4,
254 .reg_format_endian = REGMAP_ENDIAN_BIG,
255 .val_format_endian = REGMAP_ENDIAN_BIG,
256 .max_register = CS35L45_LASTREG,
257 .reg_defaults = cs35l45_defaults,
258 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
259 .volatile_reg = cs35l45_volatile_reg,
260 .readable_reg = cs35l45_readable_reg,
258 .cache_type = REGCACHE_RBTREE,
261 .cache_type = REGCACHE_MAPLE,
259};
260EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45);
261
262const struct regmap_config cs35l45_spi_regmap = {
263 .reg_bits = 32,
264 .val_bits = 32,
265 .pad_bits = 16,
266 .reg_stride = 4,
267 .reg_format_endian = REGMAP_ENDIAN_BIG,
268 .val_format_endian = REGMAP_ENDIAN_BIG,
269 .max_register = CS35L45_LASTREG,
270 .reg_defaults = cs35l45_defaults,
271 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
272 .volatile_reg = cs35l45_volatile_reg,
273 .readable_reg = cs35l45_readable_reg,
262};
263EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45);
264
265const struct regmap_config cs35l45_spi_regmap = {
266 .reg_bits = 32,
267 .val_bits = 32,
268 .pad_bits = 16,
269 .reg_stride = 4,
270 .reg_format_endian = REGMAP_ENDIAN_BIG,
271 .val_format_endian = REGMAP_ENDIAN_BIG,
272 .max_register = CS35L45_LASTREG,
273 .reg_defaults = cs35l45_defaults,
274 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
275 .volatile_reg = cs35l45_volatile_reg,
276 .readable_reg = cs35l45_readable_reg,
274 .cache_type = REGCACHE_RBTREE,
277 .cache_type = REGCACHE_MAPLE,
275};
276EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45);
277
278static const struct {
279 u8 cfg_id;
280 u32 freq;
281} cs35l45_pll_refclk_freq[] = {
282 { 0x0C, 128000 },

--- 47 unchanged lines hidden --- 		278};
279EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45);
280
281static const struct {
282 u8 cfg_id;
283 u32 freq;
284} cs35l45_pll_refclk_freq[] = {
285 { 0x0C, 128000 },

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