amd.h (b24484c18b1089f9dd1ef7901b05a85e315e9f41) amd.h (e8a33a94078560df73761f6d6147a25bda07605c)
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>

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14#include <sound/pcm.h>
15#include <sound/soc.h>
16#include <sound/soc-acpi.h>
17#include <sound/soc-dai.h>
18
19#include "chip_offset_byte.h"
20
21#define ACP3X_DEV 3
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>

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14#include <sound/pcm.h>
15#include <sound/soc.h>
16#include <sound/soc-acpi.h>
17#include <sound/soc-dai.h>
18
19#include "chip_offset_byte.h"
20
21#define ACP3X_DEV 3
22#define ACP6X_DEV 6
22
23#define I2S_SP_INSTANCE 0x00
24#define I2S_BT_INSTANCE 0x01
25#define DMIC_INSTANCE 0x02
23
24#define I2S_SP_INSTANCE 0x00
25#define I2S_BT_INSTANCE 0x01
26#define DMIC_INSTANCE 0x02
27#define I2S_HS_INSTANCE 0x03
26
27#define MEM_WINDOW_START 0x4080000
28
29#define ACP_I2S_REG_START 0x1242400
30#define ACP_I2S_REG_END 0x1242810
31#define ACP3x_I2STDM_REG_START 0x1242400
32#define ACP3x_I2STDM_REG_END 0x1242410
33#define ACP3x_BT_TDM_REG_START 0x1242800
34#define ACP3x_BT_TDM_REG_END 0x1242810
35
36#define THRESHOLD(bit, base) ((bit) + (base))
37#define I2S_RX_THRESHOLD(base) THRESHOLD(7, base)
38#define I2S_TX_THRESHOLD(base) THRESHOLD(8, base)
39#define BT_TX_THRESHOLD(base) THRESHOLD(6, base)
40#define BT_RX_THRESHOLD(base) THRESHOLD(5, base)
28
29#define MEM_WINDOW_START 0x4080000
30
31#define ACP_I2S_REG_START 0x1242400
32#define ACP_I2S_REG_END 0x1242810
33#define ACP3x_I2STDM_REG_START 0x1242400
34#define ACP3x_I2STDM_REG_END 0x1242410
35#define ACP3x_BT_TDM_REG_START 0x1242800
36#define ACP3x_BT_TDM_REG_END 0x1242810
37
38#define THRESHOLD(bit, base) ((bit) + (base))
39#define I2S_RX_THRESHOLD(base) THRESHOLD(7, base)
40#define I2S_TX_THRESHOLD(base) THRESHOLD(8, base)
41#define BT_TX_THRESHOLD(base) THRESHOLD(6, base)
42#define BT_RX_THRESHOLD(base) THRESHOLD(5, base)
43#define HS_TX_THRESHOLD(base) THRESHOLD(4, base)
44#define HS_RX_THRESHOLD(base) THRESHOLD(3, base)
41
42#define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
43#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
44#define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
45#define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
46#define ACP_SRAM_PDM_PTE_OFFSET 0x400
45
46#define ACP_SRAM_SP_PB_PTE_OFFSET 0x0
47#define ACP_SRAM_SP_CP_PTE_OFFSET 0x100
48#define ACP_SRAM_BT_PB_PTE_OFFSET 0x200
49#define ACP_SRAM_BT_CP_PTE_OFFSET 0x300
50#define ACP_SRAM_PDM_PTE_OFFSET 0x400
51#define ACP_SRAM_HS_PB_PTE_OFFSET 0x500
52#define ACP_SRAM_HS_CP_PTE_OFFSET 0x600
47#define PAGE_SIZE_4K_ENABLE 0x2
48
49#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
50#define I2S_SP_RX_MEM_WINDOW_START 0x4020000
51#define I2S_BT_TX_MEM_WINDOW_START 0x4040000
52#define I2S_BT_RX_MEM_WINDOW_START 0x4060000
53#define PAGE_SIZE_4K_ENABLE 0x2
54
55#define I2S_SP_TX_MEM_WINDOW_START 0x4000000
56#define I2S_SP_RX_MEM_WINDOW_START 0x4020000
57#define I2S_BT_TX_MEM_WINDOW_START 0x4040000
58#define I2S_BT_RX_MEM_WINDOW_START 0x4060000
59#define I2S_HS_TX_MEM_WINDOW_START 0x40A0000
60#define I2S_HS_RX_MEM_WINDOW_START 0x40C0000
53
54#define SP_PB_FIFO_ADDR_OFFSET 0x500
55#define SP_CAPT_FIFO_ADDR_OFFSET 0x700
56#define BT_PB_FIFO_ADDR_OFFSET 0x900
57#define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
61
62#define SP_PB_FIFO_ADDR_OFFSET 0x500
63#define SP_CAPT_FIFO_ADDR_OFFSET 0x700
64#define BT_PB_FIFO_ADDR_OFFSET 0x900
65#define BT_CAPT_FIFO_ADDR_OFFSET 0xB00
66#define HS_PB_FIFO_ADDR_OFFSET 0xD00
67#define HS_CAPT_FIFO_ADDR_OFFSET 0xF00
58#define PLAYBACK_MIN_NUM_PERIODS 2
59#define PLAYBACK_MAX_NUM_PERIODS 8
60#define PLAYBACK_MAX_PERIOD_SIZE 8192
61#define PLAYBACK_MIN_PERIOD_SIZE 1024
62#define CAPTURE_MIN_NUM_PERIODS 2
63#define CAPTURE_MAX_NUM_PERIODS 8
64#define CAPTURE_MAX_PERIOD_SIZE 8192
65#define CAPTURE_MIN_PERIOD_SIZE 1024
66
67#define MAX_BUFFER 65536
68#define MIN_BUFFER MAX_BUFFER
69#define FIFO_SIZE 0x100
70#define DMA_SIZE 0x40
71#define FRM_LEN 0x100
72
73#define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
74
68#define PLAYBACK_MIN_NUM_PERIODS 2
69#define PLAYBACK_MAX_NUM_PERIODS 8
70#define PLAYBACK_MAX_PERIOD_SIZE 8192
71#define PLAYBACK_MIN_PERIOD_SIZE 1024
72#define CAPTURE_MIN_NUM_PERIODS 2
73#define CAPTURE_MAX_NUM_PERIODS 8
74#define CAPTURE_MAX_PERIOD_SIZE 8192
75#define CAPTURE_MIN_PERIOD_SIZE 1024
76
77#define MAX_BUFFER 65536
78#define MIN_BUFFER MAX_BUFFER
79#define FIFO_SIZE 0x100
80#define DMA_SIZE 0x40
81#define FRM_LEN 0x100
82
83#define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x38
84
75#define ACP_MAX_STREAM 6
85#define ACP_MAX_STREAM 8
76
77struct acp_chip_info {
78 char *name; /* Platform name */
79 unsigned int acp_rev; /* ACP Revision id */
80 void __iomem *base; /* ACP memory PCI base */
81};
82
83struct acp_stream {

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90 u32 pte_offset;
91 u32 fifo_offset;
92};
93
94struct acp_resource {
95 int offset;
96 int no_of_ctrls;
97 int irqp_used;
86
87struct acp_chip_info {
88 char *name; /* Platform name */
89 unsigned int acp_rev; /* ACP Revision id */
90 void __iomem *base; /* ACP memory PCI base */
91};
92
93struct acp_stream {

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100 u32 pte_offset;
101 u32 fifo_offset;
102};
103
104struct acp_resource {
105 int offset;
106 int no_of_ctrls;
107 int irqp_used;
108 bool soc_mclk;
98 u32 irq_reg_offset;
99 u32 i2s_pin_cfg_offset;
100 int i2s_mode;
101 u64 scratch_reg_offset;
102 u64 sram_pte_offset;
103};
104
105struct acp_dev_data {

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112 struct snd_soc_dai_driver *dai_driver;
113 int num_dai;
114
115 struct acp_stream *stream[ACP_MAX_STREAM];
116
117 struct snd_soc_acpi_mach *machines;
118 struct platform_device *mach_dev;
119
109 u32 irq_reg_offset;
110 u32 i2s_pin_cfg_offset;
111 int i2s_mode;
112 u64 scratch_reg_offset;
113 u64 sram_pte_offset;
114};
115
116struct acp_dev_data {

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123 struct snd_soc_dai_driver *dai_driver;
124 int num_dai;
125
126 struct acp_stream *stream[ACP_MAX_STREAM];
127
128 struct snd_soc_acpi_mach *machines;
129 struct platform_device *mach_dev;
130
131 u32 bclk_div;
132 u32 lrclk_div;
133
120 struct acp_resource *rsrc;
121};
122
134 struct acp_resource *rsrc;
135};
136
137union acp_i2stdm_mstrclkgen {
138 struct {
139 u32 i2stdm_master_mode : 1;
140 u32 i2stdm_format_mode : 1;
141 u32 i2stdm_lrclk_div_val : 9;
142 u32 i2stdm_bclk_div_val : 11;
143 u32:10;
144 } bitfields, bits;
145 u32 u32_all;
146};
147
123extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
124extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
125
126int asoc_acp_i2s_probe(struct snd_soc_dai *dai);
127int acp_platform_register(struct device *dev);
128int acp_platform_unregister(struct device *dev);
129
130int acp_machine_select(struct acp_dev_data *adata);

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141 case I2S_BT_INSTANCE:
142 high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
143 low = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_LOW);
144 break;
145 case I2S_SP_INSTANCE:
146 high = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
147 low = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
148 break;
148extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
149extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
150
151int asoc_acp_i2s_probe(struct snd_soc_dai *dai);
152int acp_platform_register(struct device *dev);
153int acp_platform_unregister(struct device *dev);
154
155int acp_machine_select(struct acp_dev_data *adata);

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166 case I2S_BT_INSTANCE:
167 high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
168 low = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_LOW);
169 break;
170 case I2S_SP_INSTANCE:
171 high = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
172 low = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
173 break;
174 case I2S_HS_INSTANCE:
175 high = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_HIGH);
176 low = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_LOW);
177 break;
149 default:
150 dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
151 return -EINVAL;
152 }
153 } else {
154 switch (dai_id) {
155 case I2S_BT_INSTANCE:
156 high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
157 low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
158 break;
159 case I2S_SP_INSTANCE:
160 high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
161 low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
162 break;
178 default:
179 dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
180 return -EINVAL;
181 }
182 } else {
183 switch (dai_id) {
184 case I2S_BT_INSTANCE:
185 high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
186 low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
187 break;
188 case I2S_SP_INSTANCE:
189 high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
190 low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
191 break;
192 case I2S_HS_INSTANCE:
193 high = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_HIGH);
194 low = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_LOW);
195 break;
163 case DMIC_INSTANCE:
164 high = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
165 low = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
166 break;
167 default:
168 dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
169 return -EINVAL;
170 }
171 }
172 /* Get 64 bit value from two 32 bit registers */
173 byte_count = (high << 32) | low;
174
175 return byte_count;
176}
177
196 case DMIC_INSTANCE:
197 high = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
198 low = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
199 break;
200 default:
201 dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
202 return -EINVAL;
203 }
204 }
205 /* Get 64 bit value from two 32 bit registers */
206 byte_count = (high << 32) | low;
207
208 return byte_count;
209}
210
211static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id)
212{
213 union acp_i2stdm_mstrclkgen mclkgen;
214 u32 master_reg;
215
216 switch (dai_id) {
217 case I2S_SP_INSTANCE:
218 master_reg = ACP_I2STDM0_MSTRCLKGEN;
219 break;
220 case I2S_BT_INSTANCE:
221 master_reg = ACP_I2STDM1_MSTRCLKGEN;
222 break;
223 case I2S_HS_INSTANCE:
224 master_reg = ACP_I2STDM2_MSTRCLKGEN;
225 break;
226 default:
227 master_reg = ACP_I2STDM0_MSTRCLKGEN;
228 break;
229 }
230
231 mclkgen.bits.i2stdm_master_mode = 0x1;
232 mclkgen.bits.i2stdm_format_mode = 0x00;
233
234 mclkgen.bits.i2stdm_bclk_div_val = adata->bclk_div;
235 mclkgen.bits.i2stdm_lrclk_div_val = adata->lrclk_div;
236 writel(mclkgen.u32_all, adata->acp_base + master_reg);
237}
178#endif
238#endif