patch_cs8409.c (c16c8bfa09d5f318c1bd65698d058d3739970c24) patch_cs8409.c (9cd827381310e9947ea0ed7fb69b6491419549f2)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
4 *
5 * Copyright (C) 2021 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
7 */
8

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476}
477
478static void cs42l42_mute(struct sub_codec *cs42l42, int vol_type,
479 unsigned int chs, bool mute)
480{
481 if (mute) {
482 if (vol_type == CS42L42_VOL_DAC) {
483 if (chs & BIT(0))
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
4 *
5 * Copyright (C) 2021 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
7 */
8

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476}
477
478static void cs42l42_mute(struct sub_codec *cs42l42, int vol_type,
479 unsigned int chs, bool mute)
480{
481 if (mute) {
482 if (vol_type == CS42L42_VOL_DAC) {
483 if (chs & BIT(0))
484 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHA, 0x3f);
484 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, 0x3f);
485 if (chs & BIT(1))
485 if (chs & BIT(1))
486 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHB, 0x3f);
486 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, 0x3f);
487 } else if (vol_type == CS42L42_VOL_ADC) {
488 if (chs & BIT(0))
487 } else if (vol_type == CS42L42_VOL_ADC) {
488 if (chs & BIT(0))
489 cs8409_i2c_write(cs42l42, CS42L42_REG_AMIC_VOL, 0x9f);
489 cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, 0x9f);
490 }
491 } else {
492 if (vol_type == CS42L42_VOL_DAC) {
493 if (chs & BIT(0))
490 }
491 } else {
492 if (vol_type == CS42L42_VOL_DAC) {
493 if (chs & BIT(0))
494 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHA,
494 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL,
495 -(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET])
495 -(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET])
496 & CS42L42_REG_HS_VOL_MASK);
496 & CS42L42_MIXER_CH_VOL_MASK);
497 if (chs & BIT(1))
497 if (chs & BIT(1))
498 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHB,
498 cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL,
499 -(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET])
499 -(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET])
500 & CS42L42_REG_HS_VOL_MASK);
500 & CS42L42_MIXER_CH_VOL_MASK);
501 } else if (vol_type == CS42L42_VOL_ADC) {
502 if (chs & BIT(0))
501 } else if (vol_type == CS42L42_VOL_ADC) {
502 if (chs & BIT(0))
503 cs8409_i2c_write(cs42l42, CS42L42_REG_AMIC_VOL,
503 cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME,
504 cs42l42->vol[CS42L42_ADC_VOL_OFFSET]
505 & CS42L42_REG_AMIC_VOL_MASK);
506 }
507 }
508}
509
510int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
511{

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596 cs42l42 = spec->scodecs[i];
597 cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute);
598 }
599}
600
601/* Configure CS42L42 slave codec for jack autodetect */
602static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42)
603{
504 cs42l42->vol[CS42L42_ADC_VOL_OFFSET]
505 & CS42L42_REG_AMIC_VOL_MASK);
506 }
507 }
508}
509
510int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
511{

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596 cs42l42 = spec->scodecs[i];
597 cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute);
598 }
599}
600
601/* Configure CS42L42 slave codec for jack autodetect */
602static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42)
603{
604 cs8409_i2c_write(cs42l42, 0x1b70, cs42l42->hsbias_hiz);
604 cs8409_i2c_write(cs42l42, CS42L42_HSBIAS_SC_AUTOCTL, cs42l42->hsbias_hiz);
605 /* Clear WAKE# */
605 /* Clear WAKE# */
606 cs8409_i2c_write(cs42l42, 0x1b71, 0x00C1);
606 cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C1);
607 /* Wait ~2.5ms */
608 usleep_range(2500, 3000);
609 /* Set mode WAKE# output follows the combination logic directly */
607 /* Wait ~2.5ms */
608 usleep_range(2500, 3000);
609 /* Set mode WAKE# output follows the combination logic directly */
610 cs8409_i2c_write(cs42l42, 0x1b71, 0x00C0);
610 cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C0);
611 /* Clear interrupts status */
611 /* Clear interrupts status */
612 cs8409_i2c_read(cs42l42, 0x130f);
612 cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
613 /* Enable interrupt */
613 /* Enable interrupt */
614 cs8409_i2c_write(cs42l42, 0x1320, 0xF3);
614 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
615}
616
617/* Enable and run CS42L42 slave codec jack auto detect */
618static void cs42l42_run_jack_detect(struct sub_codec *cs42l42)
619{
620 /* Clear interrupts */
615}
616
617/* Enable and run CS42L42 slave codec jack auto detect */
618static void cs42l42_run_jack_detect(struct sub_codec *cs42l42)
619{
620 /* Clear interrupts */
621 cs8409_i2c_read(cs42l42, 0x1308);
622 cs8409_i2c_read(cs42l42, 0x1b77);
623 cs8409_i2c_write(cs42l42, 0x1320, 0xFF);
624 cs8409_i2c_read(cs42l42, 0x130f);
621 cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS);
622 cs8409_i2c_read(cs42l42, CS42L42_DET_STATUS1);
623 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xFF);
624 cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
625
625
626 cs8409_i2c_write(cs42l42, 0x1102, 0x87);
627 cs8409_i2c_write(cs42l42, 0x1f06, 0x86);
628 cs8409_i2c_write(cs42l42, 0x1b74, 0x07);
629 cs8409_i2c_write(cs42l42, 0x131b, 0xFD);
630 cs8409_i2c_write(cs42l42, 0x1120, 0x80);
626 cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x87);
627 cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x86);
628 cs8409_i2c_write(cs42l42, CS42L42_MISC_DET_CTL, 0x07);
629 cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFD);
630 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
631 /* Wait ~20ms*/
632 usleep_range(20000, 25000);
631 /* Wait ~20ms*/
632 usleep_range(20000, 25000);
633 cs8409_i2c_write(cs42l42, 0x111f, 0x77);
634 cs8409_i2c_write(cs42l42, 0x1120, 0xc0);
633 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 0x77);
634 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0xc0);
635}
636
637static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status)
638{
639 int status_changed = cs42l42->force_status_change;
640
641 cs42l42->force_status_change = 0;
642
643 /* TIP_SENSE INSERT/REMOVE */
644 switch (reg_ts_status) {
635}
636
637static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status)
638{
639 int status_changed = cs42l42->force_status_change;
640
641 cs42l42->force_status_change = 0;
642
643 /* TIP_SENSE INSERT/REMOVE */
644 switch (reg_ts_status) {
645 case CS42L42_JACK_INSERTED:
645 case CS42L42_TS_PLUG:
646 if (!cs42l42->hp_jack_in) {
647 if (cs42l42->no_type_dect) {
648 status_changed = 1;
649 cs42l42->hp_jack_in = 1;
650 cs42l42->mic_jack_in = 0;
651 } else {
652 cs42l42_run_jack_detect(cs42l42);
653 }
654 }
655 break;
656
646 if (!cs42l42->hp_jack_in) {
647 if (cs42l42->no_type_dect) {
648 status_changed = 1;
649 cs42l42->hp_jack_in = 1;
650 cs42l42->mic_jack_in = 0;
651 } else {
652 cs42l42_run_jack_detect(cs42l42);
653 }
654 }
655 break;
656
657 case CS42L42_JACK_REMOVED:
657 case CS42L42_TS_UNPLUG:
658 if (cs42l42->hp_jack_in || cs42l42->mic_jack_in) {
659 status_changed = 1;
660 cs42l42->hp_jack_in = 0;
661 cs42l42->mic_jack_in = 0;
662 }
663 break;
664 default:
665 /* jack in transition */
666 break;
667 }
668
669 return status_changed;
670}
671
672static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42)
673{
658 if (cs42l42->hp_jack_in || cs42l42->mic_jack_in) {
659 status_changed = 1;
660 cs42l42->hp_jack_in = 0;
661 cs42l42->mic_jack_in = 0;
662 }
663 break;
664 default:
665 /* jack in transition */
666 break;
667 }
668
669 return status_changed;
670}
671
672static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42)
673{
674 int current_plug_status;
674 int status_changed = 0;
675 int reg_cdc_status;
676 int reg_hs_status;
677 int reg_ts_status;
678 int type;
679
680 /* Read jack detect status registers */
675 int status_changed = 0;
676 int reg_cdc_status;
677 int reg_hs_status;
678 int reg_ts_status;
679 int type;
680
681 /* Read jack detect status registers */
681 reg_cdc_status = cs8409_i2c_read(cs42l42, 0x1308);
682 reg_hs_status = cs8409_i2c_read(cs42l42, 0x1124);
683 reg_ts_status = cs8409_i2c_read(cs42l42, 0x130f);
682 reg_cdc_status = cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS);
683 reg_hs_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS);
684 reg_ts_status = cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS);
684
685 /* If status values are < 0, read error has occurred. */
686 if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0)
687 return -EIO;
688
685
686 /* If status values are < 0, read error has occurred. */
687 if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0)
688 return -EIO;
689
690 current_plug_status = (reg_ts_status & (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK))
691 >> CS42L42_TS_PLUG_SHIFT;
692
689 /* HSDET_AUTO_DONE */
693 /* HSDET_AUTO_DONE */
690 if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE) {
694 if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE_MASK) {
691
692 /* Disable HSDET_AUTO_DONE */
695
696 /* Disable HSDET_AUTO_DONE */
693 cs8409_i2c_write(cs42l42, 0x131b, 0xFF);
697 cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFF);
694
698
695 type = ((reg_hs_status & CS42L42_HSTYPE_MASK) + 1);
699 type = (reg_hs_status & CS42L42_HSDET_TYPE_MASK) >> CS42L42_HSDET_TYPE_SHIFT;
696
697 if (cs42l42->no_type_dect) {
700
701 if (cs42l42->no_type_dect) {
698 status_changed = cs42l42_handle_tip_sense(cs42l42, reg_ts_status);
699 } else if (type == 4) {
700 /* Type 4 not supported */
701 status_changed = cs42l42_handle_tip_sense(cs42l42, CS42L42_JACK_REMOVED);
702 status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);
703 } else if (type == CS42L42_PLUG_INVALID) {
704 /* Type CS42L42_PLUG_INVALID not supported */
705 status_changed = cs42l42_handle_tip_sense(cs42l42, CS42L42_TS_UNPLUG);
702 } else {
703 if (!cs42l42->hp_jack_in) {
704 status_changed = 1;
705 cs42l42->hp_jack_in = 1;
706 }
706 } else {
707 if (!cs42l42->hp_jack_in) {
708 status_changed = 1;
709 cs42l42->hp_jack_in = 1;
710 }
707 /* type = 3 has no mic */
708 if ((!cs42l42->mic_jack_in) && (type != 3)) {
711 /* type = CS42L42_PLUG_HEADPHONE has no mic */
712 if ((!cs42l42->mic_jack_in) && (type != CS42L42_PLUG_HEADPHONE)) {
709 status_changed = 1;
710 cs42l42->mic_jack_in = 1;
711 }
712 }
713 /* Configure the HSDET mode. */
713 status_changed = 1;
714 cs42l42->mic_jack_in = 1;
715 }
716 }
717 /* Configure the HSDET mode. */
714 cs8409_i2c_write(cs42l42, 0x1120, 0x80);
718 cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80);
715 /* Enable the HPOUT ground clamp and configure the HP pull-down */
719 /* Enable the HPOUT ground clamp and configure the HP pull-down */
716 cs8409_i2c_write(cs42l42, 0x1F06, 0x02);
720 cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x02);
717 /* Re-Enable Tip Sense Interrupt */
721 /* Re-Enable Tip Sense Interrupt */
718 cs8409_i2c_write(cs42l42, 0x1320, 0xF3);
722 cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3);
719 } else {
723 } else {
720 status_changed = cs42l42_handle_tip_sense(cs42l42, reg_ts_status);
724 status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status);
721 }
722
723 return status_changed;
724}
725
726static void cs42l42_resume(struct sub_codec *cs42l42)
727{
728 struct hda_codec *codec = cs42l42->codec;
729 unsigned int gpio_data;
730 struct cs8409_i2c_param irq_regs[] = {
725 }
726
727 return status_changed;
728}
729
730static void cs42l42_resume(struct sub_codec *cs42l42)
731{
732 struct hda_codec *codec = cs42l42->codec;
733 unsigned int gpio_data;
734 struct cs8409_i2c_param irq_regs[] = {
731 { 0x1308, 0x00 },
732 { 0x1309, 0x00 },
733 { 0x130A, 0x00 },
734 { 0x130F, 0x00 },
735 { CS42L42_CODEC_STATUS, 0x00 },
736 { CS42L42_DET_INT_STATUS1, 0x00 },
737 { CS42L42_DET_INT_STATUS2, 0x00 },
738 { CS42L42_TSRS_PLUG_STATUS, 0x00 },
735 };
736 int fsv_old, fsv_new;
737
738 /* Bring CS42L42 out of Reset */
739 gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
740 gpio_data |= cs42l42->reset_gpio;
741 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, gpio_data);
742 usleep_range(10000, 15000);
743
744 cs42l42->suspended = 0;
745
746 /* Initialize CS42L42 companion codec */
747 cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num);
748 usleep_range(20000, 25000);
749
750 /* Clear interrupts, by reading interrupt status registers */
751 cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs));
752
739 };
740 int fsv_old, fsv_new;
741
742 /* Bring CS42L42 out of Reset */
743 gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
744 gpio_data |= cs42l42->reset_gpio;
745 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, gpio_data);
746 usleep_range(10000, 15000);
747
748 cs42l42->suspended = 0;
749
750 /* Initialize CS42L42 companion codec */
751 cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num);
752 usleep_range(20000, 25000);
753
754 /* Clear interrupts, by reading interrupt status registers */
755 cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs));
756
753 fsv_old = cs8409_i2c_read(cs42l42, 0x2001);
757 fsv_old = cs8409_i2c_read(cs42l42, CS42L42_HP_CTL);
754 if (cs42l42->full_scale_vol == CS42L42_FULL_SCALE_VOL_0DB)
755 fsv_new = fsv_old & ~CS42L42_FULL_SCALE_VOL_MASK;
756 else
757 fsv_new = fsv_old & CS42L42_FULL_SCALE_VOL_MASK;
758 if (fsv_new != fsv_old)
758 if (cs42l42->full_scale_vol == CS42L42_FULL_SCALE_VOL_0DB)
759 fsv_new = fsv_old & ~CS42L42_FULL_SCALE_VOL_MASK;
760 else
761 fsv_new = fsv_old & CS42L42_FULL_SCALE_VOL_MASK;
762 if (fsv_new != fsv_old)
759 cs8409_i2c_write(cs42l42, 0x2001, fsv_new);
763 cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv_new);
760
761 /* we have to explicitly allow unsol event handling even during the
762 * resume phase so that the jack event is processed properly
763 */
764 snd_hda_codec_allow_unsol_events(cs42l42->codec);
765
766 cs42l42_enable_jack_detect(cs42l42);
767}
768
769#ifdef CONFIG_PM
770static void cs42l42_suspend(struct sub_codec *cs42l42)
771{
772 struct hda_codec *codec = cs42l42->codec;
773 unsigned int gpio_data;
774 int reg_cdc_status = 0;
775 const struct cs8409_i2c_param cs42l42_pwr_down_seq[] = {
764
765 /* we have to explicitly allow unsol event handling even during the
766 * resume phase so that the jack event is processed properly
767 */
768 snd_hda_codec_allow_unsol_events(cs42l42->codec);
769
770 cs42l42_enable_jack_detect(cs42l42);
771}
772
773#ifdef CONFIG_PM
774static void cs42l42_suspend(struct sub_codec *cs42l42)
775{
776 struct hda_codec *codec = cs42l42->codec;
777 unsigned int gpio_data;
778 int reg_cdc_status = 0;
779 const struct cs8409_i2c_param cs42l42_pwr_down_seq[] = {
776 { 0x1F06, 0x02 },
777 { 0x1129, 0x00 },
778 { 0x2301, 0x3F },
779 { 0x2302, 0x3F },
780 { 0x2303, 0x3F },
781 { 0x2001, 0x0F },
782 { 0x2A01, 0x00 },
783 { 0x1207, 0x00 },
784 { 0x1101, 0xFE },
785 { 0x1102, 0x8C },
786 { 0x1101, 0xFF },
780 { CS42L42_DAC_CTL2, 0x02 },
781 { CS42L42_HS_CLAMP_DISABLE, 0x00 },
782 { CS42L42_MIXER_CHA_VOL, 0x3F },
783 { CS42L42_MIXER_ADC_VOL, 0x3F },
784 { CS42L42_MIXER_CHB_VOL, 0x3F },
785 { CS42L42_HP_CTL, 0x0F },
786 { CS42L42_ASP_RX_DAI0_EN, 0x00 },
787 { CS42L42_ASP_CLK_CFG, 0x00 },
788 { CS42L42_PWR_CTL1, 0xFE },
789 { CS42L42_PWR_CTL2, 0x8C },
790 { CS42L42_PWR_CTL1, 0xFF },
787 };
788
789 cs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq));
790
791 if (read_poll_timeout(cs8409_i2c_read, reg_cdc_status,
792 (reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US,
791 };
792
793 cs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq));
794
795 if (read_poll_timeout(cs8409_i2c_read, reg_cdc_status,
796 (reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US,
793 true, cs42l42, 0x1308) < 0)
797 true, cs42l42, CS42L42_CODEC_STATUS) < 0)
794 codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n");
795
796 /* Power down CS42L42 ASP/EQ/MIX/HP */
798 codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n");
799
800 /* Power down CS42L42 ASP/EQ/MIX/HP */
797 cs8409_i2c_write(cs42l42, 0x1102, 0x9C);
801 cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x9C);
798 cs42l42->suspended = 1;
799 cs42l42->last_page = 0;
800 cs42l42->hp_jack_in = 0;
801 cs42l42->mic_jack_in = 0;
802 cs42l42->force_status_change = 1;
803
804 /* Put CS42L42 into Reset */
805 gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);

--- 512 unchanged lines hidden --- 		802 cs42l42->suspended = 1;
803 cs42l42->last_page = 0;
804 cs42l42->hp_jack_in = 0;
805 cs42l42->mic_jack_in = 0;
806 cs42l42->force_status_change = 1;
807
808 /* Put CS42L42 into Reset */
809 gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);

--- 512 unchanged lines hidden ---