hpi6205.c (a1f3d4bba8ea395a39d34ade6017afee8be16031) hpi6205.c (3285ea10e9b09d68da18d2f805980246ec53523a)
1/******************************************************************************
2
3 AudioScience HPI driver
4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;

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33#include "hpimsginit.h"
34#include "hpidebug.h"
35#include "hpi6205.h"
36#include "hpidspcd.h"
37#include "hpicmn.h"
38
39/*****************************************************************************/
40/* HPI6205 specific error codes */
1/******************************************************************************
2
3 AudioScience HPI driver
4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;

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33#include "hpimsginit.h"
34#include "hpidebug.h"
35#include "hpi6205.h"
36#include "hpidspcd.h"
37#include "hpicmn.h"
38
39/*****************************************************************************/
40/* HPI6205 specific error codes */
41#define HPI6205_ERROR_BASE 1000
42/*#define HPI6205_ERROR_MEM_ALLOC 1001 */
41#define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */
42
43/* operational/messaging errors */
44#define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015
45#define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016
46
47/* initialization/bootload errors */
43#define HPI6205_ERROR_6205_NO_IRQ 1002
44#define HPI6205_ERROR_6205_INIT_FAILED 1003
48#define HPI6205_ERROR_6205_NO_IRQ 1002
49#define HPI6205_ERROR_6205_INIT_FAILED 1003
45/*#define HPI6205_ERROR_MISSING_DSPCODE 1004 */
46#define HPI6205_ERROR_UNKNOWN_PCI_DEVICE 1005
47#define HPI6205_ERROR_6205_REG 1006
48#define HPI6205_ERROR_6205_DSPPAGE 1007
50#define HPI6205_ERROR_6205_REG 1006
51#define HPI6205_ERROR_6205_DSPPAGE 1007
49#define HPI6205_ERROR_BAD_DSPINDEX 1008
50#define HPI6205_ERROR_C6713_HPIC 1009
51#define HPI6205_ERROR_C6713_HPIA 1010
52#define HPI6205_ERROR_C6713_PLL 1011
53#define HPI6205_ERROR_DSP_INTMEM 1012
54#define HPI6205_ERROR_DSP_EXTMEM 1013
55#define HPI6205_ERROR_DSP_PLD 1014
52#define HPI6205_ERROR_C6713_HPIC 1009
53#define HPI6205_ERROR_C6713_HPIA 1010
54#define HPI6205_ERROR_C6713_PLL 1011
55#define HPI6205_ERROR_DSP_INTMEM 1012
56#define HPI6205_ERROR_DSP_EXTMEM 1013
57#define HPI6205_ERROR_DSP_PLD 1014
56#define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015
57#define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016
58#define HPI6205_ERROR_6205_EEPROM 1017
59#define HPI6205_ERROR_DSP_EMIF 1018
60
58#define HPI6205_ERROR_6205_EEPROM 1017
59#define HPI6205_ERROR_DSP_EMIF 1018
60
61#define hpi6205_error(dsp_index, err) (err)
62/*****************************************************************************/
63/* for C6205 PCI i/f */
64/* Host Status Register (HSR) bitfields */
65#define C6205_HSR_INTSRC 0x01
66#define C6205_HSR_INTAVAL 0x02
67#define C6205_HSR_INTAM 0x04
68#define C6205_HSR_CFGERR 0x08
69#define C6205_HSR_EEREAD 0x10

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203 struct hpi_message *phm, struct hpi_response *phr);
204
205static void instream_start(struct hpi_adapter_obj *pao,
206 struct hpi_message *phm, struct hpi_response *phr);
207
208static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
209 u32 address);
210
61/*****************************************************************************/
62/* for C6205 PCI i/f */
63/* Host Status Register (HSR) bitfields */
64#define C6205_HSR_INTSRC 0x01
65#define C6205_HSR_INTAVAL 0x02
66#define C6205_HSR_INTAM 0x04
67#define C6205_HSR_CFGERR 0x08
68#define C6205_HSR_EEREAD 0x10

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202 struct hpi_message *phm, struct hpi_response *phr);
203
204static void instream_start(struct hpi_adapter_obj *pao,
205 struct hpi_message *phm, struct hpi_response *phr);
206
207static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
208 u32 address);
209
211static u16 boot_loader_write_mem32(struct hpi_adapter_obj *pao, int dsp_index,
212 u32 address, u32 data);
210static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
211 int dsp_index, u32 address, u32 data);
213
214static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao,
215 int dsp_index);
216
217static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
218 u32 address, u32 length);
219
220static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
221 int dsp_index);
222
223static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
224 int dsp_index);
225
226static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index);
227
228/*****************************************************************************/
229
230static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
231{
212
213static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao,
214 int dsp_index);
215
216static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
217 u32 address, u32 length);
218
219static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
220 int dsp_index);
221
222static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
223 int dsp_index);
224
225static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index);
226
227/*****************************************************************************/
228
229static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
230{
232
233 switch (phm->function) {
231 switch (phm->function) {
234 case HPI_SUBSYS_OPEN:
235 case HPI_SUBSYS_CLOSE:
236 case HPI_SUBSYS_GET_INFO:
237 case HPI_SUBSYS_DRIVER_UNLOAD:
238 case HPI_SUBSYS_DRIVER_LOAD:
239 case HPI_SUBSYS_FIND_ADAPTERS:
240 /* messages that should not get here */
241 phr->error = HPI_ERROR_UNIMPLEMENTED;
242 break;
243 case HPI_SUBSYS_CREATE_ADAPTER:
244 subsys_create_adapter(phm, phr);
245 break;
246 case HPI_SUBSYS_DELETE_ADAPTER:
247 subsys_delete_adapter(phm, phr);
248 break;
249 default:
250 phr->error = HPI_ERROR_INVALID_FUNC;
251 break;
252 }
253}
254
255static void control_message(struct hpi_adapter_obj *pao,
256 struct hpi_message *phm, struct hpi_response *phr)
257{
258
259 struct hpi_hw_obj *phw = pao->priv;
232 case HPI_SUBSYS_CREATE_ADAPTER:
233 subsys_create_adapter(phm, phr);
234 break;
235 case HPI_SUBSYS_DELETE_ADAPTER:
236 subsys_delete_adapter(phm, phr);
237 break;
238 default:
239 phr->error = HPI_ERROR_INVALID_FUNC;
240 break;
241 }
242}
243
244static void control_message(struct hpi_adapter_obj *pao,
245 struct hpi_message *phm, struct hpi_response *phr)
246{
247
248 struct hpi_hw_obj *phw = pao->priv;
249 u16 pending_cache_error = 0;
260
261 switch (phm->function) {
262 case HPI_CONTROL_GET_STATE:
263 if (pao->has_control_cache) {
250
251 switch (phm->function) {
252 case HPI_CONTROL_GET_STATE:
253 if (pao->has_control_cache) {
264 rmb(); /* make sure we see updates DM_aed from DSP */
265 if (hpi_check_control_cache(phw->p_cache, phm, phr))
254 rmb(); /* make sure we see updates DMAed from DSP */
255 if (hpi_check_control_cache(phw->p_cache, phm, phr)) {
266 break;
256 break;
257 } else if (phm->u.c.attribute == HPI_METER_PEAK) {
258 pending_cache_error =
259 HPI_ERROR_CONTROL_CACHING;
260 }
267 }
268 hw_message(pao, phm, phr);
261 }
262 hw_message(pao, phm, phr);
263 if (pending_cache_error && !phr->error)
264 phr->error = pending_cache_error;
269 break;
270 case HPI_CONTROL_GET_INFO:
271 hw_message(pao, phm, phr);
272 break;
273 case HPI_CONTROL_SET_STATE:
274 hw_message(pao, phm, phr);
275 if (pao->has_control_cache)
265 break;
266 case HPI_CONTROL_GET_INFO:
267 hw_message(pao, phm, phr);
268 break;
269 case HPI_CONTROL_SET_STATE:
270 hw_message(pao, phm, phr);
271 if (pao->has_control_cache)
276 hpi_sync_control_cache(phw->p_cache, phm, phr);
272 hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm,
273 phr);
277 break;
278 default:
279 phr->error = HPI_ERROR_INVALID_FUNC;
280 break;
281 }
282}
283
284static void adapter_message(struct hpi_adapter_obj *pao,

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293
294static void outstream_message(struct hpi_adapter_obj *pao,
295 struct hpi_message *phm, struct hpi_response *phr)
296{
297
298 if (phm->obj_index >= HPI_MAX_STREAMS) {
299 phr->error = HPI_ERROR_INVALID_STREAM;
300 HPI_DEBUG_LOG(WARNING,
274 break;
275 default:
276 phr->error = HPI_ERROR_INVALID_FUNC;
277 break;
278 }
279}
280
281static void adapter_message(struct hpi_adapter_obj *pao,

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290
291static void outstream_message(struct hpi_adapter_obj *pao,
292 struct hpi_message *phm, struct hpi_response *phr)
293{
294
295 if (phm->obj_index >= HPI_MAX_STREAMS) {
296 phr->error = HPI_ERROR_INVALID_STREAM;
297 HPI_DEBUG_LOG(WARNING,
301 "message referencing invalid stream %d "
298 "Message referencing invalid stream %d "
302 "on adapter index %d\n", phm->obj_index,
303 phm->adapter_index);
304 return;
305 }
306
307 switch (phm->function) {
308 case HPI_OSTREAM_WRITE:
309 outstream_write(pao, phm, phr);

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337
338static void instream_message(struct hpi_adapter_obj *pao,
339 struct hpi_message *phm, struct hpi_response *phr)
340{
341
342 if (phm->obj_index >= HPI_MAX_STREAMS) {
343 phr->error = HPI_ERROR_INVALID_STREAM;
344 HPI_DEBUG_LOG(WARNING,
299 "on adapter index %d\n", phm->obj_index,
300 phm->adapter_index);
301 return;
302 }
303
304 switch (phm->function) {
305 case HPI_OSTREAM_WRITE:
306 outstream_write(pao, phm, phr);

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334
335static void instream_message(struct hpi_adapter_obj *pao,
336 struct hpi_message *phm, struct hpi_response *phr)
337{
338
339 if (phm->obj_index >= HPI_MAX_STREAMS) {
340 phr->error = HPI_ERROR_INVALID_STREAM;
341 HPI_DEBUG_LOG(WARNING,
345 "message referencing invalid stream %d "
342 "Message referencing invalid stream %d "
346 "on adapter index %d\n", phm->obj_index,
347 phm->adapter_index);
348 return;
349 }
350
351 switch (phm->function) {
352 case HPI_ISTREAM_READ:
353 instream_read(pao, phm, phr);

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380void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
381{
382 struct hpi_adapter_obj *pao = NULL;
383
384 /* subsytem messages are processed by every HPI.
385 * All other messages are ignored unless the adapter index matches
386 * an adapter in the HPI
387 */
343 "on adapter index %d\n", phm->obj_index,
344 phm->adapter_index);
345 return;
346 }
347
348 switch (phm->function) {
349 case HPI_ISTREAM_READ:
350 instream_read(pao, phm, phr);

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377void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
378{
379 struct hpi_adapter_obj *pao = NULL;
380
381 /* subsytem messages are processed by every HPI.
382 * All other messages are ignored unless the adapter index matches
383 * an adapter in the HPI
384 */
388 HPI_DEBUG_LOG(DEBUG, "HPI obj=%d, func=%d\n", phm->object,
389 phm->function);
385 /* HPI_DEBUG_LOG(DEBUG, "HPI Obj=%d, Func=%d\n", phm->wObject,
386 phm->wFunction); */
390
391 /* if Dsp has crashed then do not communicate with it any more */
392 if (phm->object != HPI_OBJ_SUBSYSTEM) {
393 pao = hpi_find_adapter(phm->adapter_index);
394 if (!pao) {
395 HPI_DEBUG_LOG(DEBUG,
396 " %d,%d refused, for another HPI?\n",
397 phm->object, phm->function);

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406 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n",
407 phm->object, phm->function);
408 return;
409 }
410 }
411
412 /* Init default response */
413 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
387
388 /* if Dsp has crashed then do not communicate with it any more */
389 if (phm->object != HPI_OBJ_SUBSYSTEM) {
390 pao = hpi_find_adapter(phm->adapter_index);
391 if (!pao) {
392 HPI_DEBUG_LOG(DEBUG,
393 " %d,%d refused, for another HPI?\n",
394 phm->object, phm->function);

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403 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n",
404 phm->object, phm->function);
405 return;
406 }
407 }
408
409 /* Init default response */
410 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
414 hpi_init_response(phr, phm->object, phm->function,
415 HPI_ERROR_PROCESSING_MESSAGE);
411 phr->error = HPI_ERROR_PROCESSING_MESSAGE;
416
417 HPI_DEBUG_LOG(VERBOSE, "start of switch\n");
418 switch (phm->type) {
419 case HPI_TYPE_MESSAGE:
420 switch (phm->object) {
421 case HPI_OBJ_SUBSYSTEM:
422 subsys_message(phm, phr);
423 break;
424
425 case HPI_OBJ_ADAPTER:
412
413 HPI_DEBUG_LOG(VERBOSE, "start of switch\n");
414 switch (phm->type) {
415 case HPI_TYPE_MESSAGE:
416 switch (phm->object) {
417 case HPI_OBJ_SUBSYSTEM:
418 subsys_message(phm, phr);
419 break;
420
421 case HPI_OBJ_ADAPTER:
426 phr->size =
427 sizeof(struct hpi_response_header) +
428 sizeof(struct hpi_adapter_res);
429 adapter_message(pao, phm, phr);
430 break;
431
432 case HPI_OBJ_CONTROLEX:
433 case HPI_OBJ_CONTROL:
434 control_message(pao, phm, phr);
435 break;
436

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469 struct hpi_adapter_obj ao;
470 u32 os_error_code;
471 u16 err;
472
473 HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n");
474
475 memset(&ao, 0, sizeof(ao));
476
422 adapter_message(pao, phm, phr);
423 break;
424
425 case HPI_OBJ_CONTROLEX:
426 case HPI_OBJ_CONTROL:
427 control_message(pao, phm, phr);
428 break;
429

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462 struct hpi_adapter_obj ao;
463 u32 os_error_code;
464 u16 err;
465
466 HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n");
467
468 memset(&ao, 0, sizeof(ao));
469
477 /* this HPI only creates adapters for TI/PCI devices */
478 if (phm->u.s.resource.bus_type != HPI_BUS_PCI)
479 return;
480 if (phm->u.s.resource.r.pci->vendor_id != HPI_PCI_VENDOR_ID_TI)
481 return;
482 if (phm->u.s.resource.r.pci->device_id != HPI_PCI_DEV_ID_DSP6205)
483 return;
484
485 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
486 if (!ao.priv) {
487 HPI_DEBUG_LOG(ERROR, "cant get mem for adapter object\n");
488 phr->error = HPI_ERROR_MEMORY_ALLOC;
489 return;
490 }
491
492 ao.pci = *phm->u.s.resource.r.pci;
493 err = create_adapter_obj(&ao, &os_error_code);
470 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
471 if (!ao.priv) {
472 HPI_DEBUG_LOG(ERROR, "cant get mem for adapter object\n");
473 phr->error = HPI_ERROR_MEMORY_ALLOC;
474 return;
475 }
476
477 ao.pci = *phm->u.s.resource.r.pci;
478 err = create_adapter_obj(&ao, &os_error_code);
494 if (!err)
495 err = hpi_add_adapter(&ao);
496 if (err) {
479 if (err) {
497 phr->u.s.data = os_error_code;
498 delete_adapter_obj(&ao);
499 phr->error = err;
480 delete_adapter_obj(&ao);
481 phr->error = err;
482 phr->u.s.data = os_error_code;
500 return;
501 }
502
503 phr->u.s.aw_adapter_list[ao.index] = ao.adapter_type;
504 phr->u.s.adapter_index = ao.index;
505 phr->u.s.num_adapters++;
506 phr->error = 0;
507}
508
509/** delete an adapter - required by WDM driver */
510static void subsys_delete_adapter(struct hpi_message *phm,
511 struct hpi_response *phr)
512{
513 struct hpi_adapter_obj *pao;
514 struct hpi_hw_obj *phw;
515
483 return;
484 }
485
486 phr->u.s.aw_adapter_list[ao.index] = ao.adapter_type;
487 phr->u.s.adapter_index = ao.index;
488 phr->u.s.num_adapters++;
489 phr->error = 0;
490}
491
492/** delete an adapter - required by WDM driver */
493static void subsys_delete_adapter(struct hpi_message *phm,
494 struct hpi_response *phr)
495{
496 struct hpi_adapter_obj *pao;
497 struct hpi_hw_obj *phw;
498
516 pao = hpi_find_adapter(phm->adapter_index);
499 pao = hpi_find_adapter(phm->obj_index);
517 if (!pao) {
518 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
519 return;
520 }
521 phw = (struct hpi_hw_obj *)pao->priv;
522 /* reset adapter h/w */
523 /* Reset C6713 #1 */
524 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
525 /* reset C6205 */
526 iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR);
527
528 delete_adapter_obj(pao);
500 if (!pao) {
501 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
502 return;
503 }
504 phw = (struct hpi_hw_obj *)pao->priv;
505 /* reset adapter h/w */
506 /* Reset C6713 #1 */
507 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
508 /* reset C6205 */
509 iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR);
510
511 delete_adapter_obj(pao);
512 hpi_delete_adapter(pao);
529 phr->error = 0;
530}
531
532/** Create adapter object
533 allocate buffers, bootload DSPs, initialise control cache
534*/
535static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
536 u32 *pos_error_code)

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561 phw->prDSPP =
562 pao->pci.ap_mem_base[1] +
563 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]);
564
565 pao->has_control_cache = 0;
566
567 if (hpios_locked_mem_alloc(&phw->h_locked_mem,
568 sizeof(struct bus_master_interface),
513 phr->error = 0;
514}
515
516/** Create adapter object
517 allocate buffers, bootload DSPs, initialise control cache
518*/
519static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
520 u32 *pos_error_code)

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545 phw->prDSPP =
546 pao->pci.ap_mem_base[1] +
547 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]);
548
549 pao->has_control_cache = 0;
550
551 if (hpios_locked_mem_alloc(&phw->h_locked_mem,
552 sizeof(struct bus_master_interface),
569 pao->pci.p_os_data))
553 pao->pci.pci_dev))
570 phw->p_interface_buffer = NULL;
571 else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem,
572 (void *)&phw->p_interface_buffer))
573 phw->p_interface_buffer = NULL;
574
575 HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n",
576 phw->p_interface_buffer);
577

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586 /* no need to clean up as SubSysCreateAdapter */
587 /* calls DeleteAdapter on error. */
588 return err;
589
590 HPI_DEBUG_LOG(INFO, "load DSP code OK\n");
591
592 /* allow boot load even if mem alloc wont work */
593 if (!phw->p_interface_buffer)
554 phw->p_interface_buffer = NULL;
555 else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem,
556 (void *)&phw->p_interface_buffer))
557 phw->p_interface_buffer = NULL;
558
559 HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n",
560 phw->p_interface_buffer);
561

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570 /* no need to clean up as SubSysCreateAdapter */
571 /* calls DeleteAdapter on error. */
572 return err;
573
574 HPI_DEBUG_LOG(INFO, "load DSP code OK\n");
575
576 /* allow boot load even if mem alloc wont work */
577 if (!phw->p_interface_buffer)
594 return hpi6205_error(0, HPI_ERROR_MEMORY_ALLOC);
578 return HPI_ERROR_MEMORY_ALLOC;
595
596 interface = phw->p_interface_buffer;
597
598#ifndef HPI6205_NO_HSR_POLL
599 /* wait for first interrupt indicating the DSP init is done */
600 time_out = HPI6205_TIMEOUT * 10;
601 temp1 = 0;
602 while (((temp1 & C6205_HSR_INTSRC) == 0) && --time_out)
603 temp1 = ioread32(phw->prHSR);
604
605 if (temp1 & C6205_HSR_INTSRC)
606 HPI_DEBUG_LOG(INFO,
579
580 interface = phw->p_interface_buffer;
581
582#ifndef HPI6205_NO_HSR_POLL
583 /* wait for first interrupt indicating the DSP init is done */
584 time_out = HPI6205_TIMEOUT * 10;
585 temp1 = 0;
586 while (((temp1 & C6205_HSR_INTSRC) == 0) && --time_out)
587 temp1 = ioread32(phw->prHSR);
588
589 if (temp1 & C6205_HSR_INTSRC)
590 HPI_DEBUG_LOG(INFO,
607 "interrupt confirming DSP code running OK\n");
591 "Interrupt confirming DSP code running OK\n");
608 else {
609 HPI_DEBUG_LOG(ERROR,
592 else {
593 HPI_DEBUG_LOG(ERROR,
610 "timed out waiting for interrupt "
594 "Timed out waiting for interrupt "
611 "confirming DSP code running\n");
595 "confirming DSP code running\n");
612 return hpi6205_error(0, HPI6205_ERROR_6205_NO_IRQ);
596 return HPI6205_ERROR_6205_NO_IRQ;
613 }
614
615 /* reset the interrupt */
616 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
617#endif
618
619 /* make sure the DSP has started ok */
620 if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) {
621 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n");
597 }
598
599 /* reset the interrupt */
600 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
601#endif
602
603 /* make sure the DSP has started ok */
604 if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) {
605 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n");
622 return hpi6205_error(0, HPI6205_ERROR_6205_INIT_FAILED);
606 return HPI6205_ERROR_6205_INIT_FAILED;
623 }
624 /* Note that *pao, *phw are zeroed after allocation,
625 * so pointers and flags are NULL by default.
626 * Allocate bus mastering control cache buffer and tell the DSP about it
627 */
628 if (interface->control_cache.number_of_controls) {
607 }
608 /* Note that *pao, *phw are zeroed after allocation,
609 * so pointers and flags are NULL by default.
610 * Allocate bus mastering control cache buffer and tell the DSP about it
611 */
612 if (interface->control_cache.number_of_controls) {
629 void *p_control_cache_virtual;
613 u8 *p_control_cache_virtual;
630
631 err = hpios_locked_mem_alloc(&phw->h_control_cache,
632 interface->control_cache.size_in_bytes,
614
615 err = hpios_locked_mem_alloc(&phw->h_control_cache,
616 interface->control_cache.size_in_bytes,
633 pao->pci.p_os_data);
617 pao->pci.pci_dev);
634 if (!err)
635 err = hpios_locked_mem_get_virt_addr(&phw->
618 if (!err)
619 err = hpios_locked_mem_get_virt_addr(&phw->
636 h_control_cache, &p_control_cache_virtual);
620 h_control_cache,
621 (void *)&p_control_cache_virtual);
637 if (!err) {
638 memset(p_control_cache_virtual, 0,
639 interface->control_cache.size_in_bytes);
640
641 phw->p_cache =
642 hpi_alloc_control_cache(interface->
643 control_cache.number_of_controls,
644 interface->control_cache.size_in_bytes,
622 if (!err) {
623 memset(p_control_cache_virtual, 0,
624 interface->control_cache.size_in_bytes);
625
626 phw->p_cache =
627 hpi_alloc_control_cache(interface->
628 control_cache.number_of_controls,
629 interface->control_cache.size_in_bytes,
645 (struct hpi_control_cache_info *)
646 p_control_cache_virtual);
647 if (!phw->p_cache)
648 err = HPI_ERROR_MEMORY_ALLOC;
649 }
650 if (!err) {
651 err = hpios_locked_mem_get_phys_addr(&phw->
652 h_control_cache, &phys_addr);
653 interface->control_cache.physical_address32 =

--- 7 unchanged lines hidden (view full) ---

661 hpios_locked_mem_free(&phw->h_control_cache);
662 pao->has_control_cache = 0;
663 }
664 }
665 /* allocate bus mastering async buffer and tell the DSP about it */
666 if (interface->async_buffer.b.size) {
667 err = hpios_locked_mem_alloc(&phw->h_async_event_buffer,
668 interface->async_buffer.b.size *
630 p_control_cache_virtual);
631 if (!phw->p_cache)
632 err = HPI_ERROR_MEMORY_ALLOC;
633 }
634 if (!err) {
635 err = hpios_locked_mem_get_phys_addr(&phw->
636 h_control_cache, &phys_addr);
637 interface->control_cache.physical_address32 =

--- 7 unchanged lines hidden (view full) ---

645 hpios_locked_mem_free(&phw->h_control_cache);
646 pao->has_control_cache = 0;
647 }
648 }
649 /* allocate bus mastering async buffer and tell the DSP about it */
650 if (interface->async_buffer.b.size) {
651 err = hpios_locked_mem_alloc(&phw->h_async_event_buffer,
652 interface->async_buffer.b.size *
669 sizeof(struct hpi_async_event), pao->pci.p_os_data);
653 sizeof(struct hpi_async_event), pao->pci.pci_dev);
670 if (!err)
671 err = hpios_locked_mem_get_virt_addr
672 (&phw->h_async_event_buffer, (void *)
673 &phw->p_async_event_buffer);
674 if (!err)
675 memset((void *)phw->p_async_event_buffer, 0,
676 interface->async_buffer.b.size *
677 sizeof(struct hpi_async_event));

--- 10 unchanged lines hidden (view full) ---

688 (&phw->h_async_event_buffer);
689 phw->p_async_event_buffer = NULL;
690 }
691 }
692 }
693 send_dsp_command(phw, H620_HIF_IDLE);
694
695 {
654 if (!err)
655 err = hpios_locked_mem_get_virt_addr
656 (&phw->h_async_event_buffer, (void *)
657 &phw->p_async_event_buffer);
658 if (!err)
659 memset((void *)phw->p_async_event_buffer, 0,
660 interface->async_buffer.b.size *
661 sizeof(struct hpi_async_event));

--- 10 unchanged lines hidden (view full) ---

672 (&phw->h_async_event_buffer);
673 phw->p_async_event_buffer = NULL;
674 }
675 }
676 }
677 send_dsp_command(phw, H620_HIF_IDLE);
678
679 {
696 struct hpi_message hM;
697 struct hpi_response hR;
680 struct hpi_message hm;
681 struct hpi_response hr;
698 u32 max_streams;
699
700 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n");
682 u32 max_streams;
683
684 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n");
701 memset(&hM, 0, sizeof(hM));
702 hM.type = HPI_TYPE_MESSAGE;
703 hM.size = sizeof(hM);
704 hM.object = HPI_OBJ_ADAPTER;
705 hM.function = HPI_ADAPTER_GET_INFO;
706 hM.adapter_index = 0;
707 memset(&hR, 0, sizeof(hR));
708 hR.size = sizeof(hR);
685 memset(&hm, 0, sizeof(hm));
686 hm.type = HPI_TYPE_MESSAGE;
687 hm.size = sizeof(hm);
688 hm.object = HPI_OBJ_ADAPTER;
689 hm.function = HPI_ADAPTER_GET_INFO;
690 hm.adapter_index = 0;
691 memset(&hr, 0, sizeof(hr));
692 hr.size = sizeof(hr);
709
693
710 err = message_response_sequence(pao, &hM, &hR);
694 err = message_response_sequence(pao, &hm, &hr);
711 if (err) {
712 HPI_DEBUG_LOG(ERROR, "message transport error %d\n",
713 err);
714 return err;
715 }
695 if (err) {
696 HPI_DEBUG_LOG(ERROR, "message transport error %d\n",
697 err);
698 return err;
699 }
716 if (hR.error)
717 return hR.error;
700 if (hr.error)
701 return hr.error;
718
702
719 pao->adapter_type = hR.u.a.adapter_type;
720 pao->index = hR.u.a.adapter_index;
703 pao->adapter_type = hr.u.ax.info.adapter_type;
704 pao->index = hr.u.ax.info.adapter_index;
721
705
722 max_streams = hR.u.a.num_outstreams + hR.u.a.num_instreams;
706 max_streams =
707 hr.u.ax.info.num_outstreams +
708 hr.u.ax.info.num_instreams;
723
724 hpios_locked_mem_prepare((max_streams * 6) / 10, max_streams,
709
710 hpios_locked_mem_prepare((max_streams * 6) / 10, max_streams,
725 65536, pao->pci.p_os_data);
711 65536, pao->pci.pci_dev);
726
727 HPI_DEBUG_LOG(VERBOSE,
728 "got adapter info type %x index %d serial %d\n",
712
713 HPI_DEBUG_LOG(VERBOSE,
714 "got adapter info type %x index %d serial %d\n",
729 hR.u.a.adapter_type, hR.u.a.adapter_index,
730 hR.u.a.serial_number);
715 hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index,
716 hr.u.ax.info.serial_number);
731 }
732
733 pao->open = 0; /* upon creation the adapter is closed */
734
735 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
717 }
718
719 pao->open = 0; /* upon creation the adapter is closed */
720
721 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
736 return 0;
722
723 return hpi_add_adapter(pao);
737}
738
739/** Free memory areas allocated by adapter
740 * this routine is called from SubSysDeleteAdapter,
741 * and SubSysCreateAdapter if duplicate index
742*/
743static void delete_adapter_obj(struct hpi_adapter_obj *pao)
744{

--- 26 unchanged lines hidden (view full) ---

771
772 for (i = 0; i < HPI_MAX_STREAMS; i++)
773 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) {
774 hpios_locked_mem_free(&phw->outstream_host_buffers
775 [i]);
776 phw->outstream_host_buffer_size[i] = 0;
777 }
778
724}
725
726/** Free memory areas allocated by adapter
727 * this routine is called from SubSysDeleteAdapter,
728 * and SubSysCreateAdapter if duplicate index
729*/
730static void delete_adapter_obj(struct hpi_adapter_obj *pao)
731{

--- 26 unchanged lines hidden (view full) ---

758
759 for (i = 0; i < HPI_MAX_STREAMS; i++)
760 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) {
761 hpios_locked_mem_free(&phw->outstream_host_buffers
762 [i]);
763 phw->outstream_host_buffer_size[i] = 0;
764 }
765
779 hpios_locked_mem_unprepare(pao->pci.p_os_data);
766 hpios_locked_mem_unprepare(pao->pci.pci_dev);
780
767
781 hpi_delete_adapter(pao);
782 kfree(phw);
783}
784
785/*****************************************************************************/
786/* OutStream Host buffer functions */
787
788/** Allocate or attach buffer for busmastering
789*/

--- 29 unchanged lines hidden (view full) ---

819
820 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
821 obj_index]))
822 hpios_locked_mem_free(&phw->outstream_host_buffers
823 [phm->obj_index]);
824
825 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers
826 [phm->obj_index], phm->u.d.u.buffer.buffer_size,
768 kfree(phw);
769}
770
771/*****************************************************************************/
772/* OutStream Host buffer functions */
773
774/** Allocate or attach buffer for busmastering
775*/

--- 29 unchanged lines hidden (view full) ---

805
806 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
807 obj_index]))
808 hpios_locked_mem_free(&phw->outstream_host_buffers
809 [phm->obj_index]);
810
811 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers
812 [phm->obj_index], phm->u.d.u.buffer.buffer_size,
827 pao->pci.p_os_data);
813 pao->pci.pci_dev);
828
829 if (err) {
830 phr->error = HPI_ERROR_INVALID_DATASIZE;
831 phw->outstream_host_buffer_size[phm->obj_index] = 0;
832 return;
833 }
834
835 err = hpios_locked_mem_get_phys_addr

--- 20 unchanged lines hidden (view full) ---

856 /* GRANT phase. Set up the BBM status, tell the DSP about
857 the buffer so it can start using BBM.
858 */
859 struct hpi_hostbuffer_status *status;
860
861 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
862 buffer_size - 1)) {
863 HPI_DEBUG_LOG(ERROR,
814
815 if (err) {
816 phr->error = HPI_ERROR_INVALID_DATASIZE;
817 phw->outstream_host_buffer_size[phm->obj_index] = 0;
818 return;
819 }
820
821 err = hpios_locked_mem_get_phys_addr

--- 20 unchanged lines hidden (view full) ---

842 /* GRANT phase. Set up the BBM status, tell the DSP about
843 the buffer so it can start using BBM.
844 */
845 struct hpi_hostbuffer_status *status;
846
847 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
848 buffer_size - 1)) {
849 HPI_DEBUG_LOG(ERROR,
864 "buffer size must be 2^N not %d\n",
850 "Buffer size must be 2^N not %d\n",
865 phm->u.d.u.buffer.buffer_size);
866 phr->error = HPI_ERROR_INVALID_DATASIZE;
867 return;
868 }
869 phw->outstream_host_buffer_size[phm->obj_index] =
870 phm->u.d.u.buffer.buffer_size;
871 status = &interface->outstream_host_buffer_status[phm->
872 obj_index];

--- 88 unchanged lines hidden (view full) ---

961 /* there is no BBM buffer, write via message */
962 hw_message(pao, phm, phr);
963 return;
964 }
965
966 hpi_init_response(phr, phm->object, phm->function, 0);
967 status = &interface->outstream_host_buffer_status[phm->obj_index];
968
851 phm->u.d.u.buffer.buffer_size);
852 phr->error = HPI_ERROR_INVALID_DATASIZE;
853 return;
854 }
855 phw->outstream_host_buffer_size[phm->obj_index] =
856 phm->u.d.u.buffer.buffer_size;
857 status = &interface->outstream_host_buffer_status[phm->
858 obj_index];

--- 88 unchanged lines hidden (view full) ---

947 /* there is no BBM buffer, write via message */
948 hw_message(pao, phm, phr);
949 return;
950 }
951
952 hpi_init_response(phr, phm->object, phm->function, 0);
953 status = &interface->outstream_host_buffer_status[phm->obj_index];
954
969 if (phw->flag_outstream_just_reset[phm->obj_index]) {
970 /* First OutStremWrite() call following reset will write data to the
971 adapter's buffers, reducing delay before stream can start. The DSP
972 takes care of setting the stream data format using format information
973 embedded in phm.
974 */
975 int partial_write = 0;
976 unsigned int original_size = 0;
977
978 phw->flag_outstream_just_reset[phm->obj_index] = 0;
979
980 /* Send the first buffer to the DSP the old way. */
981 /* Limit size of first transfer - */
982 /* expect that this will not usually be triggered. */
983 if (phm->u.d.u.data.data_size > HPI6205_SIZEOF_DATA) {
984 partial_write = 1;
985 original_size = phm->u.d.u.data.data_size;
986 phm->u.d.u.data.data_size = HPI6205_SIZEOF_DATA;
987 }
988 /* write it */
989 phm->function = HPI_OSTREAM_WRITE;
990 hw_message(pao, phm, phr);
991
992 if (phr->error)
993 return;
994
995 /* update status information that the DSP would typically
996 * update (and will update next time the DSP
997 * buffer update task reads data from the host BBM buffer)
998 */
999 status->auxiliary_data_available = phm->u.d.u.data.data_size;
1000 status->host_index += phm->u.d.u.data.data_size;
1001 status->dSP_index += phm->u.d.u.data.data_size;
1002
1003 /* if we did a full write, we can return from here. */
1004 if (!partial_write)
1005 return;
1006
1007 /* tweak buffer parameters and let the rest of the */
1008 /* buffer land in internal BBM buffer */
1009 phm->u.d.u.data.data_size =
1010 original_size - HPI6205_SIZEOF_DATA;
1011 phm->u.d.u.data.pb_data += HPI6205_SIZEOF_DATA;
1012 }
1013
1014 space_available = outstream_get_space_available(status);
1015 if (space_available < phm->u.d.u.data.data_size) {
1016 phr->error = HPI_ERROR_INVALID_DATASIZE;
1017 return;
1018 }
1019
1020 /* HostBuffers is used to indicate host buffer is internally allocated.
1021 otherwise, assumed external, data written externally */

--- 20 unchanged lines hidden (view full) ---

1042
1043 memcpy(p_bbm_data +
1044 (status->host_index & (status->size_in_bytes - 1)),
1045 p_app_data, l_first_write);
1046 /* remaining data if any */
1047 memcpy(p_bbm_data, p_app_data + l_first_write,
1048 phm->u.d.u.data.data_size - l_first_write);
1049 }
955 space_available = outstream_get_space_available(status);
956 if (space_available < phm->u.d.u.data.data_size) {
957 phr->error = HPI_ERROR_INVALID_DATASIZE;
958 return;
959 }
960
961 /* HostBuffers is used to indicate host buffer is internally allocated.
962 otherwise, assumed external, data written externally */

--- 20 unchanged lines hidden (view full) ---

983
984 memcpy(p_bbm_data +
985 (status->host_index & (status->size_in_bytes - 1)),
986 p_app_data, l_first_write);
987 /* remaining data if any */
988 memcpy(p_bbm_data, p_app_data + l_first_write,
989 phm->u.d.u.data.data_size - l_first_write);
990 }
991
992 /*
993 * This version relies on the DSP code triggering an OStream buffer
994 * update immediately following a SET_FORMAT call. The host has
995 * already written data into the BBM buffer, but the DSP won't know about
996 * it until dwHostIndex is adjusted.
997 */
998 if (phw->flag_outstream_just_reset[phm->obj_index]) {
999 /* Format can only change after reset. Must tell DSP. */
1000 u16 function = phm->function;
1001 phw->flag_outstream_just_reset[phm->obj_index] = 0;
1002 phm->function = HPI_OSTREAM_SET_FORMAT;
1003 hw_message(pao, phm, phr); /* send the format to the DSP */
1004 phm->function = function;
1005 if (phr->error)
1006 return;
1007 }
1008
1050 status->host_index += phm->u.d.u.data.data_size;
1051}
1052
1053static void outstream_get_info(struct hpi_adapter_obj *pao,
1054 struct hpi_message *phm, struct hpi_response *phr)
1055{
1056 struct hpi_hw_obj *phw = pao->priv;
1057 struct bus_master_interface *interface = phw->p_interface_buffer;

--- 69 unchanged lines hidden (view full) ---

1127
1128 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1129 obj_index]))
1130 hpios_locked_mem_free(&phw->instream_host_buffers
1131 [phm->obj_index]);
1132
1133 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm->
1134 obj_index], phm->u.d.u.buffer.buffer_size,
1009 status->host_index += phm->u.d.u.data.data_size;
1010}
1011
1012static void outstream_get_info(struct hpi_adapter_obj *pao,
1013 struct hpi_message *phm, struct hpi_response *phr)
1014{
1015 struct hpi_hw_obj *phw = pao->priv;
1016 struct bus_master_interface *interface = phw->p_interface_buffer;

--- 69 unchanged lines hidden (view full) ---

1086
1087 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1088 obj_index]))
1089 hpios_locked_mem_free(&phw->instream_host_buffers
1090 [phm->obj_index]);
1091
1092 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm->
1093 obj_index], phm->u.d.u.buffer.buffer_size,
1135 pao->pci.p_os_data);
1094 pao->pci.pci_dev);
1136
1137 if (err) {
1138 phr->error = HPI_ERROR_INVALID_DATASIZE;
1139 phw->instream_host_buffer_size[phm->obj_index] = 0;
1140 return;
1141 }
1142
1143 err = hpios_locked_mem_get_phys_addr

--- 14 unchanged lines hidden (view full) ---

1158
1159 if (command == HPI_BUFFER_CMD_EXTERNAL
1160 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
1161 struct hpi_hostbuffer_status *status;
1162
1163 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
1164 buffer_size - 1)) {
1165 HPI_DEBUG_LOG(ERROR,
1095
1096 if (err) {
1097 phr->error = HPI_ERROR_INVALID_DATASIZE;
1098 phw->instream_host_buffer_size[phm->obj_index] = 0;
1099 return;
1100 }
1101
1102 err = hpios_locked_mem_get_phys_addr

--- 14 unchanged lines hidden (view full) ---

1117
1118 if (command == HPI_BUFFER_CMD_EXTERNAL
1119 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
1120 struct hpi_hostbuffer_status *status;
1121
1122 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
1123 buffer_size - 1)) {
1124 HPI_DEBUG_LOG(ERROR,
1166 "buffer size must be 2^N not %d\n",
1125 "Buffer size must be 2^N not %d\n",
1167 phm->u.d.u.buffer.buffer_size);
1168 phr->error = HPI_ERROR_INVALID_DATASIZE;
1169 return;
1170 }
1171
1172 phw->instream_host_buffer_size[phm->obj_index] =
1173 phm->u.d.u.buffer.buffer_size;
1174 status = &interface->instream_host_buffer_status[phm->

--- 164 unchanged lines hidden (view full) ---

1339#define HPI6205_MAX_FILES_TO_LOAD 2
1340
1341static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
1342 u32 *pos_error_code)
1343{
1344 struct hpi_hw_obj *phw = pao->priv;
1345 struct dsp_code dsp_code;
1346 u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD];
1126 phm->u.d.u.buffer.buffer_size);
1127 phr->error = HPI_ERROR_INVALID_DATASIZE;
1128 return;
1129 }
1130
1131 phw->instream_host_buffer_size[phm->obj_index] =
1132 phm->u.d.u.buffer.buffer_size;
1133 status = &interface->instream_host_buffer_status[phm->

--- 164 unchanged lines hidden (view full) ---

1298#define HPI6205_MAX_FILES_TO_LOAD 2
1299
1300static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
1301 u32 *pos_error_code)
1302{
1303 struct hpi_hw_obj *phw = pao->priv;
1304 struct dsp_code dsp_code;
1305 u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD];
1347 u16 firmware_id = pao->pci.subsys_device_id;
1306 u16 firmware_id = pao->pci.pci_dev->subsystem_device;
1348 u32 temp;
1349 int dsp = 0, i = 0;
1350 u16 err = 0;
1351
1352 boot_code_id[0] = HPI_ADAPTER_ASI(0x6205);
1353
1354 /* special cases where firmware_id != subsys ID */
1355 switch (firmware_id) {

--- 20 unchanged lines hidden (view full) ---

1376 temp = C6205_HDCR_WARMRESET;
1377 iowrite32(temp, phw->prHDCR);
1378 hpios_delay_micro_seconds(1000);
1379
1380 /* check that PCI i/f was configured by EEPROM */
1381 temp = ioread32(phw->prHSR);
1382 if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) !=
1383 C6205_HSR_EEREAD)
1307 u32 temp;
1308 int dsp = 0, i = 0;
1309 u16 err = 0;
1310
1311 boot_code_id[0] = HPI_ADAPTER_ASI(0x6205);
1312
1313 /* special cases where firmware_id != subsys ID */
1314 switch (firmware_id) {

--- 20 unchanged lines hidden (view full) ---

1335 temp = C6205_HDCR_WARMRESET;
1336 iowrite32(temp, phw->prHDCR);
1337 hpios_delay_micro_seconds(1000);
1338
1339 /* check that PCI i/f was configured by EEPROM */
1340 temp = ioread32(phw->prHSR);
1341 if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) !=
1342 C6205_HSR_EEREAD)
1384 return hpi6205_error(0, HPI6205_ERROR_6205_EEPROM);
1343 return HPI6205_ERROR_6205_EEPROM;
1385 temp |= 0x04;
1386 /* disable PINTA interrupt */
1387 iowrite32(temp, phw->prHSR);
1388
1389 /* check control register reports PCI boot mode */
1390 temp = ioread32(phw->prHDCR);
1391 if (!(temp & C6205_HDCR_PCIBOOT))
1344 temp |= 0x04;
1345 /* disable PINTA interrupt */
1346 iowrite32(temp, phw->prHSR);
1347
1348 /* check control register reports PCI boot mode */
1349 temp = ioread32(phw->prHDCR);
1350 if (!(temp & C6205_HDCR_PCIBOOT))
1392 return hpi6205_error(0, HPI6205_ERROR_6205_REG);
1351 return HPI6205_ERROR_6205_REG;
1393
1352
1394 /* try writing a couple of numbers to the DSP page register */
1353 /* try writing a few numbers to the DSP page register */
1395 /* and reading them back. */
1354 /* and reading them back. */
1396 temp = 1;
1355 temp = 3;
1397 iowrite32(temp, phw->prDSPP);
1398 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1356 iowrite32(temp, phw->prDSPP);
1357 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1399 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE);
1358 return HPI6205_ERROR_6205_DSPPAGE;
1400 temp = 2;
1401 iowrite32(temp, phw->prDSPP);
1402 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1359 temp = 2;
1360 iowrite32(temp, phw->prDSPP);
1361 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1403 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE);
1404 temp = 3;
1362 return HPI6205_ERROR_6205_DSPPAGE;
1363 temp = 1;
1405 iowrite32(temp, phw->prDSPP);
1406 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1364 iowrite32(temp, phw->prDSPP);
1365 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1407 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE);
1366 return HPI6205_ERROR_6205_DSPPAGE;
1408 /* reset DSP page to the correct number */
1409 temp = 0;
1410 iowrite32(temp, phw->prDSPP);
1411 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1367 /* reset DSP page to the correct number */
1368 temp = 0;
1369 iowrite32(temp, phw->prDSPP);
1370 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1412 return hpi6205_error(0, HPI6205_ERROR_6205_DSPPAGE);
1371 return HPI6205_ERROR_6205_DSPPAGE;
1413 phw->dsp_page = 0;
1414
1415 /* release 6713 from reset before 6205 is bootloaded.
1416 This ensures that the EMIF is inactive,
1417 and the 6713 HPI gets the correct bootmode etc
1418 */
1419 if (boot_code_id[1] != 0) {
1420 /* DSP 1 is a C6713 */

--- 29 unchanged lines hidden (view full) ---

1450 if (err)
1451 return err;
1452
1453 err = boot_loader_test_pld(pao, dsp);
1454 if (err)
1455 return err;
1456
1457 /* write the DSP code down into the DSPs memory */
1372 phw->dsp_page = 0;
1373
1374 /* release 6713 from reset before 6205 is bootloaded.
1375 This ensures that the EMIF is inactive,
1376 and the 6713 HPI gets the correct bootmode etc
1377 */
1378 if (boot_code_id[1] != 0) {
1379 /* DSP 1 is a C6713 */

--- 29 unchanged lines hidden (view full) ---

1409 if (err)
1410 return err;
1411
1412 err = boot_loader_test_pld(pao, dsp);
1413 if (err)
1414 return err;
1415
1416 /* write the DSP code down into the DSPs memory */
1458 dsp_code.ps_dev = pao->pci.p_os_data;
1417 dsp_code.ps_dev = pao->pci.pci_dev;
1459 err = hpi_dsp_code_open(boot_code_id[dsp], &dsp_code,
1460 pos_error_code);
1461 if (err)
1462 return err;
1463
1464 while (1) {
1465 u32 length;
1466 u32 address;

--- 12 unchanged lines hidden (view full) ---

1479 err = hpi_dsp_code_read_word(&dsp_code, &type);
1480 if (err)
1481 break;
1482 err = hpi_dsp_code_read_block(length, &dsp_code,
1483 &pcode);
1484 if (err)
1485 break;
1486 for (i = 0; i < (int)length; i++) {
1418 err = hpi_dsp_code_open(boot_code_id[dsp], &dsp_code,
1419 pos_error_code);
1420 if (err)
1421 return err;
1422
1423 while (1) {
1424 u32 length;
1425 u32 address;

--- 12 unchanged lines hidden (view full) ---

1438 err = hpi_dsp_code_read_word(&dsp_code, &type);
1439 if (err)
1440 break;
1441 err = hpi_dsp_code_read_block(length, &dsp_code,
1442 &pcode);
1443 if (err)
1444 break;
1445 for (i = 0; i < (int)length; i++) {
1487 err = boot_loader_write_mem32(pao, dsp,
1488 address, *pcode);
1489 if (err)
1490 break;
1446 boot_loader_write_mem32(pao, dsp, address,
1447 *pcode);
1491 /* dummy read every 4 words */
1492 /* for 6205 advisory 1.4.4 */
1493 if (i % 4 == 0)
1494 boot_loader_read_mem32(pao, dsp,
1495 address);
1496 pcode++;
1497 address += 4;
1498 }

--- 57 unchanged lines hidden (view full) ---

1556
1557 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem,
1558 &physicalPC_iaddress);
1559
1560 /* locate the host mailbox on the DSP. */
1561 host_mailbox_address_on_dsp = 0x80000000;
1562 while ((physicalPC_iaddress != physicalPC_iaddress_verify)
1563 && time_out--) {
1448 /* dummy read every 4 words */
1449 /* for 6205 advisory 1.4.4 */
1450 if (i % 4 == 0)
1451 boot_loader_read_mem32(pao, dsp,
1452 address);
1453 pcode++;
1454 address += 4;
1455 }

--- 57 unchanged lines hidden (view full) ---

1513
1514 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem,
1515 &physicalPC_iaddress);
1516
1517 /* locate the host mailbox on the DSP. */
1518 host_mailbox_address_on_dsp = 0x80000000;
1519 while ((physicalPC_iaddress != physicalPC_iaddress_verify)
1520 && time_out--) {
1564 err = boot_loader_write_mem32(pao, 0,
1521 boot_loader_write_mem32(pao, 0,
1565 host_mailbox_address_on_dsp,
1566 physicalPC_iaddress);
1567 physicalPC_iaddress_verify =
1568 boot_loader_read_mem32(pao, 0,
1569 host_mailbox_address_on_dsp);
1570 }
1571 }
1572 HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n");

--- 53 unchanged lines hidden (view full) ---

1626 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1627 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR);
1628 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR);
1629 data = (data << 16) | (lsb & 0xFFFF);
1630 }
1631 return data;
1632}
1633
1522 host_mailbox_address_on_dsp,
1523 physicalPC_iaddress);
1524 physicalPC_iaddress_verify =
1525 boot_loader_read_mem32(pao, 0,
1526 host_mailbox_address_on_dsp);
1527 }
1528 }
1529 HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n");

--- 53 unchanged lines hidden (view full) ---

1583 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1584 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR);
1585 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR);
1586 data = (data << 16) | (lsb & 0xFFFF);
1587 }
1588 return data;
1589}
1590
1634static u16 boot_loader_write_mem32(struct hpi_adapter_obj *pao, int dsp_index,
1635 u32 address, u32 data)
1591static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
1592 int dsp_index, u32 address, u32 data)
1636{
1637 struct hpi_hw_obj *phw = pao->priv;
1593{
1594 struct hpi_hw_obj *phw = pao->priv;
1638 u16 err = 0;
1639 __iomem u32 *p_data;
1640 /* u32 dwVerifyData=0; */
1641
1642 if (dsp_index == 0) {
1643 /* DSP 0 is always C6205 */
1644 if ((address >= 0x01800000) & (address < 0x02000000)) {
1645 /* BAR1 - DSP register access using */
1646 /* Non-prefetchable PCI access */

--- 23 unchanged lines hidden (view full) ---

1670 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1671 boot_loader_read_mem32(pao, 0, 0);
1672
1673 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data);
1674 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16);
1675
1676 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1677 boot_loader_read_mem32(pao, 0, 0);
1595 __iomem u32 *p_data;
1596 /* u32 dwVerifyData=0; */
1597
1598 if (dsp_index == 0) {
1599 /* DSP 0 is always C6205 */
1600 if ((address >= 0x01800000) & (address < 0x02000000)) {
1601 /* BAR1 - DSP register access using */
1602 /* Non-prefetchable PCI access */

--- 23 unchanged lines hidden (view full) ---

1626 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1627 boot_loader_read_mem32(pao, 0, 0);
1628
1629 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data);
1630 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16);
1631
1632 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1633 boot_loader_read_mem32(pao, 0, 0);
1678 } else
1679 err = hpi6205_error(dsp_index, HPI6205_ERROR_BAD_DSPINDEX);
1680 return err;
1634 }
1681}
1682
1683static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index)
1684{
1635}
1636
1637static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index)
1638{
1685 u16 err = 0;
1686
1687 if (dsp_index == 0) {
1688 u32 setting;
1689
1690 /* DSP 0 is always C6205 */
1691
1692 /* Set the EMIF */
1693 /* memory map of C6205 */
1694 /* 00000000-0000FFFF 16Kx32 internal program */

--- 11 unchanged lines hidden (view full) ---

1706#define MTYPE_OFS 4
1707#define RH_OFS 0
1708
1709 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */
1710 setting = 0x00000030;
1711 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting);
1712 if (setting != boot_loader_read_mem32(pao, dsp_index,
1713 0x01800008))
1639 if (dsp_index == 0) {
1640 u32 setting;
1641
1642 /* DSP 0 is always C6205 */
1643
1644 /* Set the EMIF */
1645 /* memory map of C6205 */
1646 /* 00000000-0000FFFF 16Kx32 internal program */

--- 11 unchanged lines hidden (view full) ---

1658#define MTYPE_OFS 4
1659#define RH_OFS 0
1660
1661 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */
1662 setting = 0x00000030;
1663 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting);
1664 if (setting != boot_loader_read_mem32(pao, dsp_index,
1665 0x01800008))
1714 return hpi6205_error(dsp_index,
1715 HPI6205_ERROR_DSP_EMIF);
1666 return HPI6205_ERROR_DSP_EMIF;
1716
1717 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */
1718 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1719 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */
1720 /* WST should be 71, but 63 is max possible */
1721 setting =
1722 (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) |
1723 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1724 (2L << MTYPE_OFS);
1725 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting);
1726 if (setting != boot_loader_read_mem32(pao, dsp_index,
1727 0x01800004))
1667
1668 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */
1669 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1670 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */
1671 /* WST should be 71, but 63 is max possible */
1672 setting =
1673 (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) |
1674 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1675 (2L << MTYPE_OFS);
1676 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting);
1677 if (setting != boot_loader_read_mem32(pao, dsp_index,
1678 0x01800004))
1728 return hpi6205_error(dsp_index,
1729 HPI6205_ERROR_DSP_EMIF);
1679 return HPI6205_ERROR_DSP_EMIF;
1730
1731 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */
1732 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1733 /* plenty of wait states */
1734 setting =
1735 (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) |
1736 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1737 (2L << MTYPE_OFS);
1738 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting);
1739 if (setting != boot_loader_read_mem32(pao, dsp_index,
1740 0x01800010))
1680
1681 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */
1682 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1683 /* plenty of wait states */
1684 setting =
1685 (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) |
1686 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1687 (2L << MTYPE_OFS);
1688 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting);
1689 if (setting != boot_loader_read_mem32(pao, dsp_index,
1690 0x01800010))
1741 return hpi6205_error(dsp_index,
1742 HPI6205_ERROR_DSP_EMIF);
1691 return HPI6205_ERROR_DSP_EMIF;
1743
1744 /* EMIF CE3 setup - 32 bit async. */
1745 /* This is the PLD on the ASI5000 cards only */
1746 setting =
1747 (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) |
1748 (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) |
1749 (2L << MTYPE_OFS);
1750 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting);
1751 if (setting != boot_loader_read_mem32(pao, dsp_index,
1752 0x01800014))
1692
1693 /* EMIF CE3 setup - 32 bit async. */
1694 /* This is the PLD on the ASI5000 cards only */
1695 setting =
1696 (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) |
1697 (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) |
1698 (2L << MTYPE_OFS);
1699 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting);
1700 if (setting != boot_loader_read_mem32(pao, dsp_index,
1701 0x01800014))
1753 return hpi6205_error(dsp_index,
1754 HPI6205_ERROR_DSP_EMIF);
1702 return HPI6205_ERROR_DSP_EMIF;
1755
1756 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */
1757 /* need to use this else DSP code crashes? */
1758 boot_loader_write_mem32(pao, dsp_index, 0x01800018,
1759 0x07117000);
1760
1761 /* EMIF SDRAM Refresh Timing */
1762 /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */

--- 7 unchanged lines hidden (view full) ---

1770 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */
1771 write_data = 1;
1772 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);
1773 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data);
1774 /* C67 HPI is on lower 16bits of 32bit EMIF */
1775 read_data =
1776 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR);
1777 if (write_data != read_data) {
1703
1704 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */
1705 /* need to use this else DSP code crashes? */
1706 boot_loader_write_mem32(pao, dsp_index, 0x01800018,
1707 0x07117000);
1708
1709 /* EMIF SDRAM Refresh Timing */
1710 /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */

--- 7 unchanged lines hidden (view full) ---

1718 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */
1719 write_data = 1;
1720 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);
1721 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data);
1722 /* C67 HPI is on lower 16bits of 32bit EMIF */
1723 read_data =
1724 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR);
1725 if (write_data != read_data) {
1778 err = hpi6205_error(dsp_index,
1779 HPI6205_ERROR_C6713_HPIC);
1780 HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data,
1781 read_data);
1726 HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data,
1727 read_data);
1782
1783 return err;
1728 return HPI6205_ERROR_C6713_HPIC;
1784 }
1785 /* HPIA - walking ones test */
1786 write_data = 1;
1787 for (i = 0; i < 32; i++) {
1788 boot_loader_write_mem32(pao, 0, HPIAL_ADDR,
1789 write_data);
1790 boot_loader_write_mem32(pao, 0, HPIAH_ADDR,
1791 (write_data >> 16));
1792 read_data =
1793 0xFFFF & boot_loader_read_mem32(pao, 0,
1794 HPIAL_ADDR);
1795 read_data =
1796 read_data | ((0xFFFF &
1797 boot_loader_read_mem32(pao, 0,
1798 HPIAH_ADDR))
1799 << 16);
1800 if (read_data != write_data) {
1729 }
1730 /* HPIA - walking ones test */
1731 write_data = 1;
1732 for (i = 0; i < 32; i++) {
1733 boot_loader_write_mem32(pao, 0, HPIAL_ADDR,
1734 write_data);
1735 boot_loader_write_mem32(pao, 0, HPIAH_ADDR,
1736 (write_data >> 16));
1737 read_data =
1738 0xFFFF & boot_loader_read_mem32(pao, 0,
1739 HPIAL_ADDR);
1740 read_data =
1741 read_data | ((0xFFFF &
1742 boot_loader_read_mem32(pao, 0,
1743 HPIAH_ADDR))
1744 << 16);
1745 if (read_data != write_data) {
1801 err = hpi6205_error(dsp_index,
1802 HPI6205_ERROR_C6713_HPIA);
1803 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n",
1804 write_data, read_data);
1746 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n",
1747 write_data, read_data);
1805 return err;
1748 return HPI6205_ERROR_C6713_HPIA;
1806 }
1807 write_data = write_data << 1;
1808 }
1809
1810 /* setup C67x PLL
1811 * ** C6713 datasheet says we cannot program PLL from HPI,
1812 * and indeed if we try to set the PLL multiply from the HPI,
1813 * the PLL does not seem to lock, so we enable the PLL and

--- 28 unchanged lines hidden (view full) ---

1842 (2L << MTYPE_OFS));
1843
1844 hpios_delay_micro_seconds(1000);
1845
1846 /* check that we can read one of the PLL registers */
1847 /* PLL should not be bypassed! */
1848 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)
1849 != 0x0001) {
1749 }
1750 write_data = write_data << 1;
1751 }
1752
1753 /* setup C67x PLL
1754 * ** C6713 datasheet says we cannot program PLL from HPI,
1755 * and indeed if we try to set the PLL multiply from the HPI,
1756 * the PLL does not seem to lock, so we enable the PLL and

--- 28 unchanged lines hidden (view full) ---

1785 (2L << MTYPE_OFS));
1786
1787 hpios_delay_micro_seconds(1000);
1788
1789 /* check that we can read one of the PLL registers */
1790 /* PLL should not be bypassed! */
1791 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)
1792 != 0x0001) {
1850 err = hpi6205_error(dsp_index,
1851 HPI6205_ERROR_C6713_PLL);
1852 return err;
1793 return HPI6205_ERROR_C6713_PLL;
1853 }
1854 /* setup C67x EMIF (note this is the only use of
1855 BAR1 via BootLoader_WriteMem32) */
1856 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
1857 0x000034A8);
1858 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
1859 0x00000030);
1860 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT,
1861 0x001BDF29);
1862 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL,
1863 0x47117000);
1864 boot_loader_write_mem32(pao, dsp_index,
1865 C6713_EMIF_SDRAMTIMING, 0x00000410);
1866
1867 hpios_delay_micro_seconds(1000);
1868 } else if (dsp_index == 2) {
1869 /* DSP 2 is a C6713 */
1794 }
1795 /* setup C67x EMIF (note this is the only use of
1796 BAR1 via BootLoader_WriteMem32) */
1797 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
1798 0x000034A8);
1799 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
1800 0x00000030);
1801 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT,
1802 0x001BDF29);
1803 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL,
1804 0x47117000);
1805 boot_loader_write_mem32(pao, dsp_index,
1806 C6713_EMIF_SDRAMTIMING, 0x00000410);
1807
1808 hpios_delay_micro_seconds(1000);
1809 } else if (dsp_index == 2) {
1810 /* DSP 2 is a C6713 */
1811 }
1870
1812
1871 } else
1872 err = hpi6205_error(dsp_index, HPI6205_ERROR_BAD_DSPINDEX);
1873 return err;
1813 return 0;
1874}
1875
1876static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
1877 u32 start_address, u32 length)
1878{
1879 u32 i = 0, j = 0;
1880 u32 test_addr = 0;
1881 u32 test_data = 0, data = 0;

--- 9 unchanged lines hidden (view full) ---

1891 test_data = 0x00000001;
1892 for (j = 0; j < 32; j++) {
1893 boot_loader_write_mem32(pao, dsp_index, test_addr,
1894 test_data);
1895 data = boot_loader_read_mem32(pao, dsp_index,
1896 test_addr);
1897 if (data != test_data) {
1898 HPI_DEBUG_LOG(VERBOSE,
1814}
1815
1816static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
1817 u32 start_address, u32 length)
1818{
1819 u32 i = 0, j = 0;
1820 u32 test_addr = 0;
1821 u32 test_data = 0, data = 0;

--- 9 unchanged lines hidden (view full) ---

1831 test_data = 0x00000001;
1832 for (j = 0; j < 32; j++) {
1833 boot_loader_write_mem32(pao, dsp_index, test_addr,
1834 test_data);
1835 data = boot_loader_read_mem32(pao, dsp_index,
1836 test_addr);
1837 if (data != test_data) {
1838 HPI_DEBUG_LOG(VERBOSE,
1899 "memtest error details "
1839 "Memtest error details "
1900 "%08x %08x %08x %i\n", test_addr,
1901 test_data, data, dsp_index);
1902 return 1; /* error */
1903 }
1904 test_data = test_data << 1;
1905 } /* for(j) */
1906 } /* for(i) */
1907
1908 /* for the next 100 locations test each location, leaving it as zero */
1909 /* write a zero to the next word in memory before we read */
1910 /* the previous write to make sure every memory location is unique */
1911 for (i = 0; i < 100; i++) {
1912 test_addr = start_address + i * 4;
1913 test_data = 0xA5A55A5A;
1914 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data);
1915 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);
1916 data = boot_loader_read_mem32(pao, dsp_index, test_addr);
1917 if (data != test_data) {
1918 HPI_DEBUG_LOG(VERBOSE,
1840 "%08x %08x %08x %i\n", test_addr,
1841 test_data, data, dsp_index);
1842 return 1; /* error */
1843 }
1844 test_data = test_data << 1;
1845 } /* for(j) */
1846 } /* for(i) */
1847
1848 /* for the next 100 locations test each location, leaving it as zero */
1849 /* write a zero to the next word in memory before we read */
1850 /* the previous write to make sure every memory location is unique */
1851 for (i = 0; i < 100; i++) {
1852 test_addr = start_address + i * 4;
1853 test_data = 0xA5A55A5A;
1854 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data);
1855 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);
1856 data = boot_loader_read_mem32(pao, dsp_index, test_addr);
1857 if (data != test_data) {
1858 HPI_DEBUG_LOG(VERBOSE,
1919 "memtest error details "
1859 "Memtest error details "
1920 "%08x %08x %08x %i\n", test_addr, test_data,
1921 data, dsp_index);
1922 return 1; /* error */
1923 }
1924 /* leave location as zero */
1925 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1926 }
1927

--- 13 unchanged lines hidden (view full) ---

1941 /* DSP 0 is a C6205 */
1942 /* 64K prog mem */
1943 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1944 0x10000);
1945 if (!err)
1946 /* 64K data mem */
1947 err = boot_loader_test_memory(pao, dsp_index,
1948 0x80000000, 0x10000);
1860 "%08x %08x %08x %i\n", test_addr, test_data,
1861 data, dsp_index);
1862 return 1; /* error */
1863 }
1864 /* leave location as zero */
1865 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1866 }
1867

--- 13 unchanged lines hidden (view full) ---

1881 /* DSP 0 is a C6205 */
1882 /* 64K prog mem */
1883 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1884 0x10000);
1885 if (!err)
1886 /* 64K data mem */
1887 err = boot_loader_test_memory(pao, dsp_index,
1888 0x80000000, 0x10000);
1949 } else if ((dsp_index == 1) || (dsp_index == 2)) {
1950 /* DSP 1&2 are a C6713 */
1889 } else if (dsp_index == 1) {
1890 /* DSP 1 is a C6713 */
1951 /* 192K internal mem */
1952 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1953 0x30000);
1954 if (!err)
1955 /* 64K internal mem / L2 cache */
1956 err = boot_loader_test_memory(pao, dsp_index,
1957 0x00030000, 0x10000);
1891 /* 192K internal mem */
1892 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1893 0x30000);
1894 if (!err)
1895 /* 64K internal mem / L2 cache */
1896 err = boot_loader_test_memory(pao, dsp_index,
1897 0x00030000, 0x10000);
1958 } else
1959 return hpi6205_error(dsp_index, HPI6205_ERROR_BAD_DSPINDEX);
1898 }
1960
1961 if (err)
1899
1900 if (err)
1962 return hpi6205_error(dsp_index, HPI6205_ERROR_DSP_INTMEM);
1901 return HPI6205_ERROR_DSP_INTMEM;
1963 else
1964 return 0;
1965}
1966
1967static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
1968 int dsp_index)
1969{
1970 u32 dRAM_start_address = 0;
1971 u32 dRAM_size = 0;
1972
1973 if (dsp_index == 0) {
1974 /* only test for SDRAM if an ASI5000 card */
1902 else
1903 return 0;
1904}
1905
1906static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
1907 int dsp_index)
1908{
1909 u32 dRAM_start_address = 0;
1910 u32 dRAM_size = 0;
1911
1912 if (dsp_index == 0) {
1913 /* only test for SDRAM if an ASI5000 card */
1975 if (pao->pci.subsys_device_id == 0x5000) {
1914 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
1976 /* DSP 0 is always C6205 */
1977 dRAM_start_address = 0x00400000;
1978 dRAM_size = 0x200000;
1979 /*dwDRAMinc=1024; */
1980 } else
1981 return 0;
1915 /* DSP 0 is always C6205 */
1916 dRAM_start_address = 0x00400000;
1917 dRAM_size = 0x200000;
1918 /*dwDRAMinc=1024; */
1919 } else
1920 return 0;
1982 } else if ((dsp_index == 1) || (dsp_index == 2)) {
1921 } else if (dsp_index == 1) {
1983 /* DSP 1 is a C6713 */
1984 dRAM_start_address = 0x80000000;
1985 dRAM_size = 0x200000;
1986 /*dwDRAMinc=1024; */
1922 /* DSP 1 is a C6713 */
1923 dRAM_start_address = 0x80000000;
1924 dRAM_size = 0x200000;
1925 /*dwDRAMinc=1024; */
1987 } else
1988 return hpi6205_error(dsp_index, HPI6205_ERROR_BAD_DSPINDEX);
1926 }
1989
1990 if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address,
1991 dRAM_size))
1927
1928 if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address,
1929 dRAM_size))
1992 return hpi6205_error(dsp_index, HPI6205_ERROR_DSP_EXTMEM);
1930 return HPI6205_ERROR_DSP_EXTMEM;
1993 return 0;
1994}
1995
1996static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index)
1997{
1998 u32 data = 0;
1999 if (dsp_index == 0) {
2000 /* only test for DSP0 PLD on ASI5000 card */
1931 return 0;
1932}
1933
1934static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index)
1935{
1936 u32 data = 0;
1937 if (dsp_index == 0) {
1938 /* only test for DSP0 PLD on ASI5000 card */
2001 if (pao->pci.subsys_device_id == 0x5000) {
1939 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
2002 /* PLD is located at CE3=0x03000000 */
2003 data = boot_loader_read_mem32(pao, dsp_index,
2004 0x03000008);
2005 if ((data & 0xF) != 0x5)
1940 /* PLD is located at CE3=0x03000000 */
1941 data = boot_loader_read_mem32(pao, dsp_index,
1942 0x03000008);
1943 if ((data & 0xF) != 0x5)
2006 return hpi6205_error(dsp_index,
2007 HPI6205_ERROR_DSP_PLD);
1944 return HPI6205_ERROR_DSP_PLD;
2008 data = boot_loader_read_mem32(pao, dsp_index,
2009 0x0300000C);
2010 if ((data & 0xF) != 0xA)
1945 data = boot_loader_read_mem32(pao, dsp_index,
1946 0x0300000C);
1947 if ((data & 0xF) != 0xA)
2011 return hpi6205_error(dsp_index,
2012 HPI6205_ERROR_DSP_PLD);
1948 return HPI6205_ERROR_DSP_PLD;
2013 }
2014 } else if (dsp_index == 1) {
2015 /* DSP 1 is a C6713 */
1949 }
1950 } else if (dsp_index == 1) {
1951 /* DSP 1 is a C6713 */
2016 if (pao->pci.subsys_device_id == 0x8700) {
1952 if (pao->pci.pci_dev->subsystem_device == 0x8700) {
2017 /* PLD is located at CE1=0x90000000 */
2018 data = boot_loader_read_mem32(pao, dsp_index,
2019 0x90000010);
2020 if ((data & 0xFF) != 0xAA)
1953 /* PLD is located at CE1=0x90000000 */
1954 data = boot_loader_read_mem32(pao, dsp_index,
1955 0x90000010);
1956 if ((data & 0xFF) != 0xAA)
2021 return hpi6205_error(dsp_index,
2022 HPI6205_ERROR_DSP_PLD);
1957 return HPI6205_ERROR_DSP_PLD;
2023 /* 8713 - LED on */
2024 boot_loader_write_mem32(pao, dsp_index, 0x90000000,
2025 0x02);
2026 }
2027 }
2028 return 0;
2029}
2030

--- 43 unchanged lines hidden (view full) ---

2074#ifdef HPI6205_NO_HSR_POLL
2075 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT);
2076 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2077 HPI6205_TIMEOUT - temp2, this_copy);
2078
2079 if (!temp2) {
2080 /* timed out */
2081 HPI_DEBUG_LOG(ERROR,
1958 /* 8713 - LED on */
1959 boot_loader_write_mem32(pao, dsp_index, 0x90000000,
1960 0x02);
1961 }
1962 }
1963 return 0;
1964}
1965

--- 43 unchanged lines hidden (view full) ---

2009#ifdef HPI6205_NO_HSR_POLL
2010 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT);
2011 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2012 HPI6205_TIMEOUT - temp2, this_copy);
2013
2014 if (!temp2) {
2015 /* timed out */
2016 HPI_DEBUG_LOG(ERROR,
2082 "timed out waiting for " "state %d got %d\n",
2017 "Timed out waiting for " "state %d got %d\n",
2083 operation, interface->dsp_ack);
2084
2085 break;
2086 }
2087#else
2088 /* spin waiting on the result */
2089 time_out = HPI6205_TIMEOUT;
2090 temp2 = 0;
2091 while ((temp2 == 0) && time_out--) {
2092 /* give 16k bus mastering transfer time to happen */
2093 /*(16k / 132Mbytes/s = 122usec) */
2094 hpios_delay_micro_seconds(20);
2095 temp2 = ioread32(phw->prHSR);
2096 temp2 &= C6205_HSR_INTSRC;
2097 }
2098 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2099 HPI6205_TIMEOUT - time_out, this_copy);
2100 if (temp2 == C6205_HSR_INTSRC) {
2101 HPI_DEBUG_LOG(VERBOSE,
2018 operation, interface->dsp_ack);
2019
2020 break;
2021 }
2022#else
2023 /* spin waiting on the result */
2024 time_out = HPI6205_TIMEOUT;
2025 temp2 = 0;
2026 while ((temp2 == 0) && time_out--) {
2027 /* give 16k bus mastering transfer time to happen */
2028 /*(16k / 132Mbytes/s = 122usec) */
2029 hpios_delay_micro_seconds(20);
2030 temp2 = ioread32(phw->prHSR);
2031 temp2 &= C6205_HSR_INTSRC;
2032 }
2033 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2034 HPI6205_TIMEOUT - time_out, this_copy);
2035 if (temp2 == C6205_HSR_INTSRC) {
2036 HPI_DEBUG_LOG(VERBOSE,
2102 "interrupt from HIF <data> OK\n");
2037 "Interrupt from HIF <data> OK\n");
2103 /*
2104 if(interface->dwDspAck != nOperation) {
2105 HPI_DEBUG_LOG(DEBUG("interface->dwDspAck=%d,
2106 expected %d \n",
2107 interface->dwDspAck,nOperation);
2108 }
2109 */
2110 }
2111/* need to handle this differently... */
2112 else {
2113 HPI_DEBUG_LOG(ERROR,
2038 /*
2039 if(interface->dwDspAck != nOperation) {
2040 HPI_DEBUG_LOG(DEBUG("interface->dwDspAck=%d,
2041 expected %d \n",
2042 interface->dwDspAck,nOperation);
2043 }
2044 */
2045 }
2046/* need to handle this differently... */
2047 else {
2048 HPI_DEBUG_LOG(ERROR,
2114 "interrupt from HIF <data> BAD\n");
2049 "Interrupt from HIF <data> BAD\n");
2115 err = HPI_ERROR_DSP_HARDWARE;
2116 }
2117
2118 /* reset the interrupt from the DSP */
2119 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
2120#endif
2121 if (operation == H620_HIF_GET_DATA)
2122 memcpy(&p_data[data_transferred],

--- 55 unchanged lines hidden (view full) ---

2178 u32 temp2;
2179#endif
2180 u32 time_out, time_out2;
2181 struct hpi_hw_obj *phw = pao->priv;
2182 struct bus_master_interface *interface = phw->p_interface_buffer;
2183 u16 err = 0;
2184
2185 message_count++;
2050 err = HPI_ERROR_DSP_HARDWARE;
2051 }
2052
2053 /* reset the interrupt from the DSP */
2054 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
2055#endif
2056 if (operation == H620_HIF_GET_DATA)
2057 memcpy(&p_data[data_transferred],

--- 55 unchanged lines hidden (view full) ---

2113 u32 temp2;
2114#endif
2115 u32 time_out, time_out2;
2116 struct hpi_hw_obj *phw = pao->priv;
2117 struct bus_master_interface *interface = phw->p_interface_buffer;
2118 u16 err = 0;
2119
2120 message_count++;
2121 if (phm->size > sizeof(interface->u)) {
2122 /* really MESSAGE buffer too small */
2123 phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
2124 phr->specific_error = sizeof(interface->u);
2125 phr->size = sizeof(struct hpi_response_header);
2126 HPI_DEBUG_LOG(ERROR,
2127 "message len %d too big for buffer %ld \n", phm->size,
2128 sizeof(interface->u));
2129 return 0;
2130 }
2131
2186 /* Assume buffer of type struct bus_master_interface
2187 is allocated "noncacheable" */
2188
2189 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2190 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n");
2132 /* Assume buffer of type struct bus_master_interface
2133 is allocated "noncacheable" */
2134
2135 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2136 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n");
2191 return hpi6205_error(0, HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT);
2137 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2192 }
2138 }
2193 interface->u.message_buffer = *phm;
2139
2140 memcpy(&interface->u.message_buffer, phm, phm->size);
2194 /* signal we want a response */
2195 send_dsp_command(phw, H620_HIF_GET_RESP);
2196
2197 time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT);
2198
2141 /* signal we want a response */
2142 send_dsp_command(phw, H620_HIF_GET_RESP);
2143
2144 time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT);
2145
2199 if (time_out2 == 0) {
2146 if (!time_out2) {
2200 HPI_DEBUG_LOG(ERROR,
2147 HPI_DEBUG_LOG(ERROR,
2201 "(%u) timed out waiting for " "GET_RESP state [%x]\n",
2148 "(%u) Timed out waiting for " "GET_RESP state [%x]\n",
2202 message_count, interface->dsp_ack);
2203 } else {
2204 HPI_DEBUG_LOG(VERBOSE,
2205 "(%u) transition to GET_RESP after %u\n",
2206 message_count, HPI6205_TIMEOUT - time_out2);
2207 }
2208 /* spin waiting on HIF interrupt flag (end of msg process) */
2209 time_out = HPI6205_TIMEOUT;

--- 17 unchanged lines hidden (view full) ---

2227 HPI_DEBUG_LOG(VERBOSE,
2228 "(%u)int with GET_RESP after %u\n",
2229 message_count, HPI6205_TIMEOUT - time_out);
2230 }
2231
2232 } else {
2233 /* can we do anything else in response to the error ? */
2234 HPI_DEBUG_LOG(ERROR,
2149 message_count, interface->dsp_ack);
2150 } else {
2151 HPI_DEBUG_LOG(VERBOSE,
2152 "(%u) transition to GET_RESP after %u\n",
2153 message_count, HPI6205_TIMEOUT - time_out2);
2154 }
2155 /* spin waiting on HIF interrupt flag (end of msg process) */
2156 time_out = HPI6205_TIMEOUT;

--- 17 unchanged lines hidden (view full) ---

2174 HPI_DEBUG_LOG(VERBOSE,
2175 "(%u)int with GET_RESP after %u\n",
2176 message_count, HPI6205_TIMEOUT - time_out);
2177 }
2178
2179 } else {
2180 /* can we do anything else in response to the error ? */
2181 HPI_DEBUG_LOG(ERROR,
2235 "interrupt from HIF module BAD (function %x)\n",
2182 "Interrupt from HIF module BAD (function %x)\n",
2236 phm->function);
2237 }
2238
2239 /* reset the interrupt from the DSP */
2240 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
2241#endif
2242
2243 /* read the result */
2183 phm->function);
2184 }
2185
2186 /* reset the interrupt from the DSP */
2187 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
2188#endif
2189
2190 /* read the result */
2244 if (time_out != 0)
2245 *phr = interface->u.response_buffer;
2246
2191 if (time_out) {
2192 if (interface->u.response_buffer.size <= phr->size)
2193 memcpy(phr, &interface->u.response_buffer,
2194 interface->u.response_buffer.size);
2195 else {
2196 HPI_DEBUG_LOG(ERROR,
2197 "response len %d too big for buffer %d\n",
2198 interface->u.response_buffer.size, phr->size);
2199 memcpy(phr, &interface->u.response_buffer,
2200 sizeof(struct hpi_response_header));
2201 phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
2202 phr->specific_error =
2203 interface->u.response_buffer.size;
2204 phr->size = sizeof(struct hpi_response_header);
2205 }
2206 }
2247 /* set interface back to idle */
2248 send_dsp_command(phw, H620_HIF_IDLE);
2249
2207 /* set interface back to idle */
2208 send_dsp_command(phw, H620_HIF_IDLE);
2209
2250 if ((time_out == 0) || (time_out2 == 0)) {
2210 if (!time_out || !time_out2) {
2251 HPI_DEBUG_LOG(DEBUG, "something timed out!\n");
2211 HPI_DEBUG_LOG(DEBUG, "something timed out!\n");
2252 return hpi6205_error(0, HPI6205_ERROR_MSG_RESP_TIMEOUT);
2212 return HPI6205_ERROR_MSG_RESP_TIMEOUT;
2253 }
2254 /* special case for adapter close - */
2255 /* wait for the DSP to indicate it is idle */
2256 if (phm->function == HPI_ADAPTER_CLOSE) {
2257 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2258 HPI_DEBUG_LOG(DEBUG,
2213 }
2214 /* special case for adapter close - */
2215 /* wait for the DSP to indicate it is idle */
2216 if (phm->function == HPI_ADAPTER_CLOSE) {
2217 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2218 HPI_DEBUG_LOG(DEBUG,
2259 "timeout waiting for idle "
2219 "Timeout waiting for idle "
2260 "(on adapter_close)\n");
2220 "(on adapter_close)\n");
2261 return hpi6205_error(0,
2262 HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT);
2221 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2263 }
2264 }
2265 err = hpi_validate_response(phm, phr);
2266 return err;
2267}
2268
2269static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
2270 struct hpi_response *phr)

--- 61 unchanged lines hidden --- 		2222 }
2223 }
2224 err = hpi_validate_response(phm, phr);
2225 return err;
2226}
2227
2228static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
2229 struct hpi_response *phr)

--- 61 unchanged lines hidden ---