tegrahdmi.c (73cd0490819d2a693928c5977280dd31b756cb42) tegrahdmi.c (ad781b550f9a8829e3dae4bd3d18c4a126a53d04)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Nvidia Tegra HDMI codec support
4 */
5
6#include <linux/init.h>
7#include <linux/slab.h>
8#include <linux/module.h>
9#include <sound/core.h>
10#include <sound/tlv.h>
11#include <sound/hdaudio.h>
12#include <sound/hda_codec.h>
13#include "hda_local.h"
14#include "hdmi_local.h"
15
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Nvidia Tegra HDMI codec support
4 */
5
6#include <linux/init.h>
7#include <linux/slab.h>
8#include <linux/module.h>
9#include <sound/core.h>
10#include <sound/tlv.h>
11#include <sound/hdaudio.h>
12#include <sound/hda_codec.h>
13#include "hda_local.h"
14#include "hdmi_local.h"
15
16enum {
17 MODEL_TEGRA,
18 MODEL_TEGRA234,
19};
20
16/*
17 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
18 * accessed using vendor-defined verbs. These registers can be used for
19 * interoperability between the HDA and HDMI drivers.
20 */
21
22/* Audio Function Group node */
23#define NVIDIA_AFG_NID 0x01

--- 212 unchanged lines hidden (view full) ---

236 for (i = 0; i < spec->num_cvts; i++)
237 snd_hda_codec_write(codec, spec->cvt_nids[i], 0,
238 AC_VERB_SET_DIGI_CONVERT_1,
239 AC_DIG1_ENABLE);
240
241 snd_hda_hdmi_generic_init_per_pins(codec);
242
243 codec->depop_delay = 10;
21/*
22 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
23 * accessed using vendor-defined verbs. These registers can be used for
24 * interoperability between the HDA and HDMI drivers.
25 */
26
27/* Audio Function Group node */
28#define NVIDIA_AFG_NID 0x01

--- 212 unchanged lines hidden (view full) ---

241 for (i = 0; i < spec->num_cvts; i++)
242 snd_hda_codec_write(codec, spec->cvt_nids[i], 0,
243 AC_VERB_SET_DIGI_CONVERT_1,
244 AC_DIG1_ENABLE);
245
246 snd_hda_hdmi_generic_init_per_pins(codec);
247
248 codec->depop_delay = 10;
244 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
245 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
246 nvhdmi_chmap_cea_alloc_validate_get_type;
247 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
248
249 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
250 nvhdmi_chmap_cea_alloc_validate_get_type;
251 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
252 spec->nv_dp_workaround = true;
253
254 return 0;
255}
256
249 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
250 nvhdmi_chmap_cea_alloc_validate_get_type;
251 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
252
253 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
254 nvhdmi_chmap_cea_alloc_validate_get_type;
255 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
256 spec->nv_dp_workaround = true;
257
258 return 0;
259}
260
257static int patch_tegra_hdmi(struct hda_codec *codec)
261static int tegrahdmi_probe(struct hda_codec *codec,
262 const struct hda_device_id *id)
258{
263{
259 int err;
260
261 err = snd_hda_hdmi_generic_alloc(codec);
262 if (err < 0)
263 return err;
264
265 return tegra_hdmi_init(codec);
266}
267
268static int patch_tegra234_hdmi(struct hda_codec *codec)
269{
270 struct hdmi_spec *spec;
271 int err;
272
273 err = snd_hda_hdmi_generic_alloc(codec);
274 if (err < 0)
275 return err;
276
264 struct hdmi_spec *spec;
265 int err;
266
267 err = snd_hda_hdmi_generic_alloc(codec);
268 if (err < 0)
269 return err;
270
277 codec->dp_mst = true;
278 spec = codec->spec;
279 spec->dyn_pin_out = true;
280 spec->hdmi_intr_trig_ctrl = true;
271 if (id->driver_data == MODEL_TEGRA234) {
272 codec->dp_mst = true;
273 spec = codec->spec;
274 spec->dyn_pin_out = true;
275 spec->hdmi_intr_trig_ctrl = true;
276 }
281
282 return tegra_hdmi_init(codec);
283}
284
277
278 return tegra_hdmi_init(codec);
279}
280
285/*
286 * patch entries
287 */
281static const struct hda_codec_ops tegrahdmi_codec_ops = {
282 .probe = tegrahdmi_probe,
283 .remove = snd_hda_hdmi_generic_remove,
284 .init = snd_hda_hdmi_generic_init,
285 .build_pcms = tegra_hdmi_build_pcms,
286 .build_controls = snd_hda_hdmi_generic_build_controls,
287 .unsol_event = snd_hda_hdmi_generic_unsol_event,
288 .suspend = snd_hda_hdmi_generic_suspend,
289 .resume = snd_hda_hdmi_generic_resume,
290};
291
288static const struct hda_device_id snd_hda_id_tegrahdmi[] = {
292static const struct hda_device_id snd_hda_id_tegrahdmi[] = {
289HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
290HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
291HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
292HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
293HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
294HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
295HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
296HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
297HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi),
298HDA_CODEC_ENTRY(0x10de0033, "SoC 33 HDMI/DP", patch_tegra234_hdmi),
299HDA_CODEC_ENTRY(0x10de0034, "Tegra264 HDMI/DP", patch_tegra234_hdmi),
300HDA_CODEC_ENTRY(0x10de0035, "SoC 35 HDMI/DP", patch_tegra234_hdmi),
301{} /* terminator */
293 HDA_CODEC_ID_MODEL(0x10de0020, "Tegra30 HDMI", MODEL_TEGRA),
294 HDA_CODEC_ID_MODEL(0x10de0022, "Tegra114 HDMI", MODEL_TEGRA),
295 HDA_CODEC_ID_MODEL(0x10de0028, "Tegra124 HDMI", MODEL_TEGRA),
296 HDA_CODEC_ID_MODEL(0x10de0029, "Tegra210 HDMI/DP", MODEL_TEGRA),
297 HDA_CODEC_ID_MODEL(0x10de002d, "Tegra186 HDMI/DP0", MODEL_TEGRA),
298 HDA_CODEC_ID_MODEL(0x10de002e, "Tegra186 HDMI/DP1", MODEL_TEGRA),
299 HDA_CODEC_ID_MODEL(0x10de002f, "Tegra194 HDMI/DP2", MODEL_TEGRA),
300 HDA_CODEC_ID_MODEL(0x10de0030, "Tegra194 HDMI/DP3", MODEL_TEGRA),
301 HDA_CODEC_ID_MODEL(0x10de0031, "Tegra234 HDMI/DP", MODEL_TEGRA234),
302 HDA_CODEC_ID_MODEL(0x10de0034, "Tegra264 HDMI/DP", MODEL_TEGRA234),
303 {} /* terminator */
302};
303MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_tegrahdmi);
304
305MODULE_LICENSE("GPL");
306MODULE_DESCRIPTION("Nvidia Tegra HDMI HD-audio codec");
307MODULE_IMPORT_NS("SND_HDA_CODEC_HDMI");
308
309static struct hda_codec_driver tegrahdmi_driver = {
310 .id = snd_hda_id_tegrahdmi,
304};
305MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_tegrahdmi);
306
307MODULE_LICENSE("GPL");
308MODULE_DESCRIPTION("Nvidia Tegra HDMI HD-audio codec");
309MODULE_IMPORT_NS("SND_HDA_CODEC_HDMI");
310
311static struct hda_codec_driver tegrahdmi_driver = {
312 .id = snd_hda_id_tegrahdmi,
313 .ops = &tegrahdmi_codec_ops,
311};
312
313module_hda_codec_driver(tegrahdmi_driver);
314};
315
316module_hda_codec_driver(tegrahdmi_driver);