intelhdmi.c (73cd0490819d2a693928c5977280dd31b756cb42) intelhdmi.c (ad781b550f9a8829e3dae4bd3d18c4a126a53d04)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Intel HDMI codec support
4 */
5
6#include <linux/init.h>
7#include <linux/slab.h>
8#include <linux/module.h>

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13#include "hda_local.h"
14#include "hdmi_local.h"
15
16static bool enable_silent_stream =
17IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
18module_param(enable_silent_stream, bool, 0644);
19MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
20
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Intel HDMI codec support
4 */
5
6#include <linux/init.h>
7#include <linux/slab.h>
8#include <linux/module.h>

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13#include "hda_local.h"
14#include "hdmi_local.h"
15
16static bool enable_silent_stream =
17IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
18module_param(enable_silent_stream, bool, 0644);
19MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
20
21enum {
22 MODEL_HSW,
23 MODEL_GLK,
24 MODEL_ICL,
25 MODEL_TGL,
26 MODEL_ADLP,
27 MODEL_BYT,
28 MODEL_CPT,
29};
30
21#define INTEL_GET_VENDOR_VERB 0xf81
22#define INTEL_SET_VENDOR_VERB 0x781
23#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
24#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
25
26static void intel_haswell_enable_all_pins(struct hda_codec *codec,
27 bool update_tree)
28{

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62}
63
64/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
65 * Otherwise you may get severe h/w communication errors.
66 */
67static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
68 unsigned int power_state)
69{
31#define INTEL_GET_VENDOR_VERB 0xf81
32#define INTEL_SET_VENDOR_VERB 0x781
33#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
34#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
35
36static void intel_haswell_enable_all_pins(struct hda_codec *codec,
37 bool update_tree)
38{

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72}
73
74/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
75 * Otherwise you may get severe h/w communication errors.
76 */
77static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
78 unsigned int power_state)
79{
70 if (power_state == AC_PWRST_D0) {
71 intel_haswell_enable_all_pins(codec, false);
72 intel_haswell_fixup_enable_dp12(codec);
80 /* check codec->spec: it can be called before the probe gets called */
81 if (codec->spec) {
82 if (power_state == AC_PWRST_D0) {
83 intel_haswell_enable_all_pins(codec, false);
84 intel_haswell_fixup_enable_dp12(codec);
85 }
73 }
74
75 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
76 snd_hda_codec_set_power_to_all(codec, fg, power_state);
77}
78
79/* There is a fixed mapping between audio pin node and display port.
80 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:

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451 intel_verify_pin_cvt_connect(codec, per_pin);
452 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
453 per_pin->dev_id, per_pin->mux_idx);
454 } else {
455 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
456 }
457}
458
86 }
87
88 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
89 snd_hda_codec_set_power_to_all(codec, fg, power_state);
90}
91
92/* There is a fixed mapping between audio pin node and display port.
93 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:

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464 intel_verify_pin_cvt_connect(codec, per_pin);
465 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
466 per_pin->dev_id, per_pin->mux_idx);
467 } else {
468 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
469 }
470}
471
459static int i915_adlp_hdmi_suspend(struct hda_codec *codec)
472static int i915_hdmi_suspend(struct hda_codec *codec)
460{
461 struct hdmi_spec *spec = codec->spec;
462 bool silent_streams = false;
463 int pin_idx, res;
464
465 res = snd_hda_hdmi_generic_suspend(codec);
473{
474 struct hdmi_spec *spec = codec->spec;
475 bool silent_streams = false;
476 int pin_idx, res;
477
478 res = snd_hda_hdmi_generic_suspend(codec);
479 if (spec->silent_stream_type != SILENT_STREAM_KAE)
480 return res;
466
467 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
468 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
469
470 if (per_pin->silent_stream) {
471 silent_streams = true;
472 break;
473 }

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490 } else {
491 codec->no_stream_clean_at_suspend = 0;
492 codec->forced_resume = 0;
493 }
494
495 return res;
496}
497
481
482 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
483 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
484
485 if (per_pin->silent_stream) {
486 silent_streams = true;
487 break;
488 }

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505 } else {
506 codec->no_stream_clean_at_suspend = 0;
507 codec->forced_resume = 0;
508 }
509
510 return res;
511}
512
498static int i915_adlp_hdmi_resume(struct hda_codec *codec)
513static int i915_hdmi_resume(struct hda_codec *codec)
499{
500 struct hdmi_spec *spec = codec->spec;
501 int pin_idx, res;
502
503 res = snd_hda_hdmi_generic_resume(codec);
514{
515 struct hdmi_spec *spec = codec->spec;
516 int pin_idx, res;
517
518 res = snd_hda_hdmi_generic_resume(codec);
519 if (spec->silent_stream_type != SILENT_STREAM_KAE)
520 return res;
504
505 /* KAE not programmed at suspend, nothing to do here */
506 if (!codec->no_stream_clean_at_suspend)
507 return res;
508
509 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
510 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
511

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534 }
535
536 return res;
537}
538
539/* precondition and allocation for Intel codecs */
540static int alloc_intel_hdmi(struct hda_codec *codec)
541{
521
522 /* KAE not programmed at suspend, nothing to do here */
523 if (!codec->no_stream_clean_at_suspend)
524 return res;
525
526 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
527 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
528

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551 }
552
553 return res;
554}
555
556/* precondition and allocation for Intel codecs */
557static int alloc_intel_hdmi(struct hda_codec *codec)
558{
542 int err;
543
544 /* requires i915 binding */
545 if (!codec->bus->core.audio_component) {
546 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
547 /* set probe_id here to prevent generic fallback binding */
548 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
549 return -ENODEV;
550 }
551
559 /* requires i915 binding */
560 if (!codec->bus->core.audio_component) {
561 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
562 /* set probe_id here to prevent generic fallback binding */
563 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
564 return -ENODEV;
565 }
566
552 err = snd_hda_hdmi_generic_alloc(codec);
553 if (err < 0)
554 return err;
555 /* no need to handle unsol events */
556 codec->patch_ops.unsol_event = NULL;
557 return 0;
567 return snd_hda_hdmi_generic_alloc(codec);
558}
559
560/* parse and post-process for Intel codecs */
561static int parse_intel_hdmi(struct hda_codec *codec)
562{
563 int err, retries = 3;
564
565 do {

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575}
576
577/* Intel Haswell and onwards; audio component with eld notifier */
578static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
579 const int *port_map, int port_num, int dev_num,
580 bool send_silent_stream)
581{
582 struct hdmi_spec *spec;
568}
569
570/* parse and post-process for Intel codecs */
571static int parse_intel_hdmi(struct hda_codec *codec)
572{
573 int err, retries = 3;
574
575 do {

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585}
586
587/* Intel Haswell and onwards; audio component with eld notifier */
588static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
589 const int *port_map, int port_num, int dev_num,
590 bool send_silent_stream)
591{
592 struct hdmi_spec *spec;
583 int err;
584
593
585 err = alloc_intel_hdmi(codec);
586 if (err < 0)
587 return err;
588 spec = codec->spec;
589 codec->dp_mst = true;
590 spec->vendor_nid = vendor_nid;
591 spec->port_map = port_map;
592 spec->port_num = port_num;
593 spec->intel_hsw_fixup = true;
594 spec->dev_num = dev_num;
595
596 intel_haswell_enable_all_pins(codec, true);
597 intel_haswell_fixup_enable_dp12(codec);
598
599 codec->display_power_control = 1;
600
594 spec = codec->spec;
595 codec->dp_mst = true;
596 spec->vendor_nid = vendor_nid;
597 spec->port_map = port_map;
598 spec->port_num = port_num;
599 spec->intel_hsw_fixup = true;
600 spec->dev_num = dev_num;
601
602 intel_haswell_enable_all_pins(codec, true);
603 intel_haswell_fixup_enable_dp12(codec);
604
605 codec->display_power_control = 1;
606
601 codec->patch_ops.set_power_state = haswell_set_power_state;
602 codec->depop_delay = 0;
603 codec->auto_runtime_pm = 1;
604
605 spec->ops.setup_stream = i915_hsw_setup_stream;
606 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
607 spec->ops.silent_stream = i915_set_silent_stream;
608
609 /*
610 * Enable silent stream feature, if it is enabled via
611 * module param or Kconfig option
612 */
613 if (send_silent_stream)
614 spec->silent_stream_type = SILENT_STREAM_I915;
615
616 return parse_intel_hdmi(codec);
617}
618
607 codec->depop_delay = 0;
608 codec->auto_runtime_pm = 1;
609
610 spec->ops.setup_stream = i915_hsw_setup_stream;
611 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
612 spec->ops.silent_stream = i915_set_silent_stream;
613
614 /*
615 * Enable silent stream feature, if it is enabled via
616 * module param or Kconfig option
617 */
618 if (send_silent_stream)
619 spec->silent_stream_type = SILENT_STREAM_I915;
620
621 return parse_intel_hdmi(codec);
622}
623
619static int patch_i915_hsw_hdmi(struct hda_codec *codec)
624static int probe_i915_hsw_hdmi(struct hda_codec *codec)
620{
621 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
622 enable_silent_stream);
623}
624
625{
626 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
627 enable_silent_stream);
628}
629
625static int patch_i915_glk_hdmi(struct hda_codec *codec)
630static int probe_i915_glk_hdmi(struct hda_codec *codec)
626{
627 /*
628 * Silent stream calls audio component .get_power() from
629 * .pin_eld_notify(). On GLK this will deadlock in i915 due
630 * to the audio vs. CDCLK workaround.
631 */
632 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
633}
634
631{
632 /*
633 * Silent stream calls audio component .get_power() from
634 * .pin_eld_notify(). On GLK this will deadlock in i915 due
635 * to the audio vs. CDCLK workaround.
636 */
637 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
638}
639
635static int patch_i915_icl_hdmi(struct hda_codec *codec)
640static int probe_i915_icl_hdmi(struct hda_codec *codec)
636{
637 /*
638 * pin to port mapping table where the value indicate the pin number and
639 * the index indicate the port number.
640 */
641 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
642
643 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
644 enable_silent_stream);
645}
646
641{
642 /*
643 * pin to port mapping table where the value indicate the pin number and
644 * the index indicate the port number.
645 */
646 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
647
648 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
649 enable_silent_stream);
650}
651
647static int patch_i915_tgl_hdmi(struct hda_codec *codec)
652static int probe_i915_tgl_hdmi(struct hda_codec *codec)
648{
649 /*
650 * pin to port mapping table where the value indicate the pin number and
651 * the index indicate the port number.
652 */
653 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
654
655 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
656 enable_silent_stream);
657}
658
653{
654 /*
655 * pin to port mapping table where the value indicate the pin number and
656 * the index indicate the port number.
657 */
658 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
659
660 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
661 enable_silent_stream);
662}
663
659static int patch_i915_adlp_hdmi(struct hda_codec *codec)
664static int probe_i915_adlp_hdmi(struct hda_codec *codec)
660{
661 struct hdmi_spec *spec;
662 int res;
663
665{
666 struct hdmi_spec *spec;
667 int res;
668
664 res = patch_i915_tgl_hdmi(codec);
669 res = probe_i915_tgl_hdmi(codec);
665 if (!res) {
666 spec = codec->spec;
667
670 if (!res) {
671 spec = codec->spec;
672
668 if (spec->silent_stream_type) {
673 if (spec->silent_stream_type)
669 spec->silent_stream_type = SILENT_STREAM_KAE;
674 spec->silent_stream_type = SILENT_STREAM_KAE;
670
671 codec->patch_ops.resume = i915_adlp_hdmi_resume;
672 codec->patch_ops.suspend = i915_adlp_hdmi_suspend;
673 }
674 }
675
676 return res;
677}
678
679/* Intel Baytrail and Braswell; with eld notifier */
675 }
676
677 return res;
678}
679
680/* Intel Baytrail and Braswell; with eld notifier */
680static int patch_i915_byt_hdmi(struct hda_codec *codec)
681static int probe_i915_byt_hdmi(struct hda_codec *codec)
681{
682 struct hdmi_spec *spec;
682{
683 struct hdmi_spec *spec;
683 int err;
684
684
685 err = alloc_intel_hdmi(codec);
686 if (err < 0)
687 return err;
688 spec = codec->spec;
689
690 /* For Valleyview/Cherryview, only the display codec is in the display
691 * power well and can use link_power ops to request/release the power.
692 */
693 codec->display_power_control = 1;
694
695 codec->depop_delay = 0;
696 codec->auto_runtime_pm = 1;
697
698 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
699
700 return parse_intel_hdmi(codec);
701}
702
703/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
685 spec = codec->spec;
686
687 /* For Valleyview/Cherryview, only the display codec is in the display
688 * power well and can use link_power ops to request/release the power.
689 */
690 codec->display_power_control = 1;
691
692 codec->depop_delay = 0;
693 codec->auto_runtime_pm = 1;
694
695 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
696
697 return parse_intel_hdmi(codec);
698}
699
700/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
704static int patch_i915_cpt_hdmi(struct hda_codec *codec)
701static int probe_i915_cpt_hdmi(struct hda_codec *codec)
705{
702{
703 return parse_intel_hdmi(codec);
704}
705
706/*
707 * common driver probe
708 */
709static int intelhdmi_probe(struct hda_codec *codec, const struct hda_device_id *id)
710{
706 int err;
707
708 err = alloc_intel_hdmi(codec);
709 if (err < 0)
710 return err;
711 int err;
712
713 err = alloc_intel_hdmi(codec);
714 if (err < 0)
715 return err;
711 return parse_intel_hdmi(codec);
716
717 switch (id->driver_data) {
718 case MODEL_HSW:
719 err = probe_i915_hsw_hdmi(codec);
720 break;
721 case MODEL_GLK:
722 err = probe_i915_glk_hdmi(codec);
723 break;
724 case MODEL_ICL:
725 err = probe_i915_icl_hdmi(codec);
726 break;
727 case MODEL_TGL:
728 err = probe_i915_tgl_hdmi(codec);
729 break;
730 case MODEL_ADLP:
731 err = probe_i915_adlp_hdmi(codec);
732 break;
733 case MODEL_BYT:
734 err = probe_i915_byt_hdmi(codec);
735 break;
736 case MODEL_CPT:
737 err = probe_i915_cpt_hdmi(codec);
738 break;
739 default:
740 err = -EINVAL;
741 break;
742 }
743
744 if (err < 0) {
745 snd_hda_hdmi_generic_spec_free(codec);
746 return err;
747 }
748
749 return 0;
712}
713
750}
751
752static const struct hda_codec_ops intelhdmi_codec_ops = {
753 .probe = intelhdmi_probe,
754 .remove = snd_hda_hdmi_generic_remove,
755 .init = snd_hda_hdmi_generic_init,
756 .build_pcms = snd_hda_hdmi_generic_build_pcms,
757 .build_controls = snd_hda_hdmi_generic_build_controls,
758 .unsol_event = snd_hda_hdmi_generic_unsol_event,
759 .suspend = i915_hdmi_suspend,
760 .resume = i915_hdmi_resume,
761 .set_power_state = haswell_set_power_state,
762};
763
714/*
715 * driver entries
716 */
717static const struct hda_device_id snd_hda_id_intelhdmi[] = {
764/*
765 * driver entries
766 */
767static const struct hda_device_id snd_hda_id_intelhdmi[] = {
718HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
719HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
720HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
721HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
722HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
723HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
724HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
725HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
726HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
727HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
728HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
729HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
730HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
731HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
732HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi),
733HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi),
734HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
735HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi),
736HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi),
737HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
738HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
739HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi),
740HDA_CODEC_ENTRY(0x8086281d, "Meteor Lake HDMI", patch_i915_adlp_hdmi),
741HDA_CODEC_ENTRY(0x8086281e, "Battlemage HDMI", patch_i915_adlp_hdmi),
742HDA_CODEC_ENTRY(0x8086281f, "Raptor Lake P HDMI", patch_i915_adlp_hdmi),
743HDA_CODEC_ENTRY(0x80862820, "Lunar Lake HDMI", patch_i915_adlp_hdmi),
744HDA_CODEC_ENTRY(0x80862822, "Panther Lake HDMI", patch_i915_adlp_hdmi),
745HDA_CODEC_ENTRY(0x80862823, "Wildcat Lake HDMI", patch_i915_adlp_hdmi),
746HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
747HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
748{} /* terminator */
768 HDA_CODEC_ID_MODEL(0x80860054, "IbexPeak HDMI", MODEL_CPT),
769 HDA_CODEC_ID_MODEL(0x80862800, "Geminilake HDMI", MODEL_GLK),
770 HDA_CODEC_ID_MODEL(0x80862804, "IbexPeak HDMI", MODEL_CPT),
771 HDA_CODEC_ID_MODEL(0x80862805, "CougarPoint HDMI", MODEL_CPT),
772 HDA_CODEC_ID_MODEL(0x80862806, "PantherPoint HDMI", MODEL_CPT),
773 HDA_CODEC_ID_MODEL(0x80862807, "Haswell HDMI", MODEL_HSW),
774 HDA_CODEC_ID_MODEL(0x80862808, "Broadwell HDMI", MODEL_HSW),
775 HDA_CODEC_ID_MODEL(0x80862809, "Skylake HDMI", MODEL_HSW),
776 HDA_CODEC_ID_MODEL(0x8086280a, "Broxton HDMI", MODEL_HSW),
777 HDA_CODEC_ID_MODEL(0x8086280b, "Kabylake HDMI", MODEL_HSW),
778 HDA_CODEC_ID_MODEL(0x8086280c, "Cannonlake HDMI", MODEL_GLK),
779 HDA_CODEC_ID_MODEL(0x8086280d, "Geminilake HDMI", MODEL_GLK),
780 HDA_CODEC_ID_MODEL(0x8086280f, "Icelake HDMI", MODEL_ICL),
781 HDA_CODEC_ID_MODEL(0x80862812, "Tigerlake HDMI", MODEL_TGL),
782 HDA_CODEC_ID_MODEL(0x80862814, "DG1 HDMI", MODEL_TGL),
783 HDA_CODEC_ID_MODEL(0x80862815, "Alderlake HDMI", MODEL_TGL),
784 HDA_CODEC_ID_MODEL(0x80862816, "Rocketlake HDMI", MODEL_TGL),
785 HDA_CODEC_ID_MODEL(0x80862818, "Raptorlake HDMI", MODEL_TGL),
786 HDA_CODEC_ID_MODEL(0x80862819, "DG2 HDMI", MODEL_TGL),
787 HDA_CODEC_ID_MODEL(0x8086281a, "Jasperlake HDMI", MODEL_ICL),
788 HDA_CODEC_ID_MODEL(0x8086281b, "Elkhartlake HDMI", MODEL_ICL),
789 HDA_CODEC_ID_MODEL(0x8086281c, "Alderlake-P HDMI", MODEL_ADLP),
790 HDA_CODEC_ID_MODEL(0x8086281d, "Meteor Lake HDMI", MODEL_ADLP),
791 HDA_CODEC_ID_MODEL(0x8086281e, "Battlemage HDMI", MODEL_ADLP),
792 HDA_CODEC_ID_MODEL(0x8086281f, "Raptor Lake P HDMI", MODEL_ADLP),
793 HDA_CODEC_ID_MODEL(0x80862820, "Lunar Lake HDMI", MODEL_ADLP),
794 HDA_CODEC_ID_MODEL(0x80862822, "Panther Lake HDMI", MODEL_ADLP),
795 HDA_CODEC_ID_MODEL(0x80862823, "Wildcat Lake HDMI", MODEL_ADLP),
796 HDA_CODEC_ID_MODEL(0x80862882, "Valleyview2 HDMI", MODEL_BYT),
797 HDA_CODEC_ID_MODEL(0x80862883, "Braswell HDMI", MODEL_BYT),
798 {} /* terminator */
749};
750MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_intelhdmi);
751
752MODULE_LICENSE("GPL");
753MODULE_DESCRIPTION("Intel HDMI HD-audio codec");
754MODULE_IMPORT_NS("SND_HDA_CODEC_HDMI");
755
756static struct hda_codec_driver intelhdmi_driver = {
757 .id = snd_hda_id_intelhdmi,
799};
800MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_intelhdmi);
801
802MODULE_LICENSE("GPL");
803MODULE_DESCRIPTION("Intel HDMI HD-audio codec");
804MODULE_IMPORT_NS("SND_HDA_CODEC_HDMI");
805
806static struct hda_codec_driver intelhdmi_driver = {
807 .id = snd_hda_id_intelhdmi,
808 .ops = &intelhdmi_codec_ops,
758};
759
760module_hda_codec_driver(intelhdmi_driver);
809};
810
811module_hda_codec_driver(intelhdmi_driver);