msm_drm.h (762f99f4f3cb41a775b5157dd761217beba65873) msm_drm.h (f7ddbf5581b474fe4a0a29244acaa1bf72234675)
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

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62 * restarting interrupted ioctls). The following struct is logically the
63 * same as 'struct timespec' but 32/64b ABI safe.
64 */
65struct drm_msm_timespec {
66 __s64 tv_sec; /* seconds */
67 __s64 tv_nsec; /* nanoseconds */
68};
69
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

--- 53 unchanged lines hidden (view full) ---

62 * restarting interrupted ioctls). The following struct is logically the
63 * same as 'struct timespec' but 32/64b ABI safe.
64 */
65struct drm_msm_timespec {
66 __s64 tv_sec; /* seconds */
67 __s64 tv_nsec; /* nanoseconds */
68};
69
70#define MSM_PARAM_GPU_ID 0x01
71#define MSM_PARAM_GMEM_SIZE 0x02
72#define MSM_PARAM_CHIP_ID 0x03
73#define MSM_PARAM_MAX_FREQ 0x04
74#define MSM_PARAM_TIMESTAMP 0x05
75#define MSM_PARAM_GMEM_BASE 0x06
76#define MSM_PARAM_PRIORITIES 0x07 /* The # of priority levels */
77#define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */
78#define MSM_PARAM_FAULTS 0x09
79#define MSM_PARAM_SUSPENDS 0x0a
70/* Below "RO" indicates a read-only param, "WO" indicates write-only, and
71 * "RW" indicates a param that can be both read (GET_PARAM) and written
72 * (SET_PARAM)
73 */
74#define MSM_PARAM_GPU_ID 0x01 /* RO */
75#define MSM_PARAM_GMEM_SIZE 0x02 /* RO */
76#define MSM_PARAM_CHIP_ID 0x03 /* RO */
77#define MSM_PARAM_MAX_FREQ 0x04 /* RO */
78#define MSM_PARAM_TIMESTAMP 0x05 /* RO */
79#define MSM_PARAM_GMEM_BASE 0x06 /* RO */
80#define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */
81#define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */
82#define MSM_PARAM_FAULTS 0x09 /* RO */
83#define MSM_PARAM_SUSPENDS 0x0a /* RO */
80
81/* For backwards compat. The original support for preemption was based on
82 * a single ring per priority level so # of priority levels equals the #
83 * of rings. With drm/scheduler providing additional levels of priority,
84 * the number of priorities is greater than the # of rings. The param is
85 * renamed to better reflect this.
86 */
87#define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES

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328 __u64 data;
329 __u32 id;
330 __u32 param;
331 __u32 len;
332 __u32 pad;
333};
334
335#define DRM_MSM_GET_PARAM 0x00
84
85/* For backwards compat. The original support for preemption was based on
86 * a single ring per priority level so # of priority levels equals the #
87 * of rings. With drm/scheduler providing additional levels of priority,
88 * the number of priorities is greater than the # of rings. The param is
89 * renamed to better reflect this.
90 */
91#define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES

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332 __u64 data;
333 __u32 id;
334 __u32 param;
335 __u32 len;
336 __u32 pad;
337};
338
339#define DRM_MSM_GET_PARAM 0x00
336/* placeholder:
337#define DRM_MSM_SET_PARAM 0x01
340#define DRM_MSM_SET_PARAM 0x01
338 */
339#define DRM_MSM_GEM_NEW 0x02
340#define DRM_MSM_GEM_INFO 0x03
341#define DRM_MSM_GEM_CPU_PREP 0x04
342#define DRM_MSM_GEM_CPU_FINI 0x05
343#define DRM_MSM_GEM_SUBMIT 0x06
344#define DRM_MSM_WAIT_FENCE 0x07
345#define DRM_MSM_GEM_MADVISE 0x08
346/* placeholder:
347#define DRM_MSM_GEM_SVM_NEW 0x09
348 */
349#define DRM_MSM_SUBMITQUEUE_NEW 0x0A
350#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
351#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
352
353#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
341#define DRM_MSM_GEM_NEW 0x02
342#define DRM_MSM_GEM_INFO 0x03
343#define DRM_MSM_GEM_CPU_PREP 0x04
344#define DRM_MSM_GEM_CPU_FINI 0x05
345#define DRM_MSM_GEM_SUBMIT 0x06
346#define DRM_MSM_WAIT_FENCE 0x07
347#define DRM_MSM_GEM_MADVISE 0x08
348/* placeholder:
349#define DRM_MSM_GEM_SVM_NEW 0x09
350 */
351#define DRM_MSM_SUBMITQUEUE_NEW 0x0A
352#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
353#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
354
355#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
356#define DRM_IOCTL_MSM_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)
354#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
355#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
356#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
357#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
358#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
359#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
360#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
361#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
362#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
363#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
364
365#if defined(__cplusplus)
366}
367#endif
368
369#endif /* __MSM_DRM_H__ */
357#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
358#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
359#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
360#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
361#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
362#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
363#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
364#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
365#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
366#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
367
368#if defined(__cplusplus)
369}
370#endif
371
372#endif /* __MSM_DRM_H__ */