amdxdna_accel.h (ac49797c1815d4f8f04b7053b2998c546283c89e) amdxdna_accel.h (aac243092b707bb3018e951d470cc1a9bcbaba6c)
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
4 */
5
6#ifndef _UAPI_AMDXDNA_ACCEL_H_
7#define _UAPI_AMDXDNA_ACCEL_H_
8
9#include <linux/stddef.h>
10#include "drm.h"
11
12#if defined(__cplusplus)
13extern "C" {
14#endif
15
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
4 */
5
6#ifndef _UAPI_AMDXDNA_ACCEL_H_
7#define _UAPI_AMDXDNA_ACCEL_H_
8
9#include <linux/stddef.h>
10#include "drm.h"
11
12#if defined(__cplusplus)
13extern "C" {
14#endif
15
16#define AMDXDNA_INVALID_CMD_HANDLE (~0UL)
16#define AMDXDNA_INVALID_ADDR (~0UL)
17#define AMDXDNA_INVALID_CTX_HANDLE 0
18#define AMDXDNA_INVALID_BO_HANDLE 0
17#define AMDXDNA_INVALID_ADDR (~0UL)
18#define AMDXDNA_INVALID_CTX_HANDLE 0
19#define AMDXDNA_INVALID_BO_HANDLE 0
20#define AMDXDNA_INVALID_FENCE_HANDLE 0
19
20enum amdxdna_device_type {
21 AMDXDNA_DEV_TYPE_UNKNOWN = -1,
22 AMDXDNA_DEV_TYPE_KMQ,
23};
24
25enum amdxdna_drm_ioctl_id {
26 DRM_AMDXDNA_CREATE_HWCTX,
27 DRM_AMDXDNA_DESTROY_HWCTX,
28 DRM_AMDXDNA_CONFIG_HWCTX,
29 DRM_AMDXDNA_CREATE_BO,
30 DRM_AMDXDNA_GET_BO_INFO,
31 DRM_AMDXDNA_SYNC_BO,
21
22enum amdxdna_device_type {
23 AMDXDNA_DEV_TYPE_UNKNOWN = -1,
24 AMDXDNA_DEV_TYPE_KMQ,
25};
26
27enum amdxdna_drm_ioctl_id {
28 DRM_AMDXDNA_CREATE_HWCTX,
29 DRM_AMDXDNA_DESTROY_HWCTX,
30 DRM_AMDXDNA_CONFIG_HWCTX,
31 DRM_AMDXDNA_CREATE_BO,
32 DRM_AMDXDNA_GET_BO_INFO,
33 DRM_AMDXDNA_SYNC_BO,
34 DRM_AMDXDNA_EXEC_CMD,
32};
33
34/**
35 * struct qos_info - QoS information for driver.
36 * @gops: Giga operations per second.
37 * @fps: Frames per second.
38 * @dma_bandwidth: DMA bandwidtha.
39 * @latency: Frame response latency.

--- 156 unchanged lines hidden (view full) ---

196 __u32 handle;
197#define SYNC_DIRECT_TO_DEVICE 0U
198#define SYNC_DIRECT_FROM_DEVICE 1U
199 __u32 direction;
200 __u64 offset;
201 __u64 size;
202};
203
35};
36
37/**
38 * struct qos_info - QoS information for driver.
39 * @gops: Giga operations per second.
40 * @fps: Frames per second.
41 * @dma_bandwidth: DMA bandwidtha.
42 * @latency: Frame response latency.

--- 156 unchanged lines hidden (view full) ---

199 __u32 handle;
200#define SYNC_DIRECT_TO_DEVICE 0U
201#define SYNC_DIRECT_FROM_DEVICE 1U
202 __u32 direction;
203 __u64 offset;
204 __u64 size;
205};
206
207enum amdxdna_cmd_type {
208 AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0,
209 AMDXDNA_CMD_SUBMIT_DEPENDENCY,
210 AMDXDNA_CMD_SUBMIT_SIGNAL,
211};
212
213/**
214 * struct amdxdna_drm_exec_cmd - Execute command.
215 * @ext: MBZ.
216 * @ext_flags: MBZ.
217 * @hwctx: Hardware context handle.
218 * @type: One of command type in enum amdxdna_cmd_type.
219 * @cmd_handles: Array of command handles or the command handle itself
220 * in case of just one.
221 * @args: Array of arguments for all command handles.
222 * @cmd_count: Number of command handles in the cmd_handles array.
223 * @arg_count: Number of arguments in the args array.
224 * @seq: Returned sequence number for this command.
225 */
226struct amdxdna_drm_exec_cmd {
227 __u64 ext;
228 __u64 ext_flags;
229 __u32 hwctx;
230 __u32 type;
231 __u64 cmd_handles;
232 __u64 args;
233 __u32 cmd_count;
234 __u32 arg_count;
235 __u64 seq;
236};
237
204#define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \
205 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \
206 struct amdxdna_drm_create_hwctx)
207
208#define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \
209 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \
210 struct amdxdna_drm_destroy_hwctx)
211

--- 8 unchanged lines hidden (view full) ---

220#define DRM_IOCTL_AMDXDNA_GET_BO_INFO \
221 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \
222 struct amdxdna_drm_get_bo_info)
223
224#define DRM_IOCTL_AMDXDNA_SYNC_BO \
225 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \
226 struct amdxdna_drm_sync_bo)
227
238#define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \
239 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \
240 struct amdxdna_drm_create_hwctx)
241
242#define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \
243 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \
244 struct amdxdna_drm_destroy_hwctx)
245

--- 8 unchanged lines hidden (view full) ---

254#define DRM_IOCTL_AMDXDNA_GET_BO_INFO \
255 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \
256 struct amdxdna_drm_get_bo_info)
257
258#define DRM_IOCTL_AMDXDNA_SYNC_BO \
259 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \
260 struct amdxdna_drm_sync_bo)
261
262#define DRM_IOCTL_AMDXDNA_EXEC_CMD \
263 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \
264 struct amdxdna_drm_exec_cmd)
265
228#if defined(__cplusplus)
229} /* extern c end */
230#endif
231
232#endif /* _UAPI_AMDXDNA_ACCEL_H_ */
266#if defined(__cplusplus)
267} /* extern c end */
268#endif
269
270#endif /* _UAPI_AMDXDNA_ACCEL_H_ */