ocelot.h (c1bd8a2b9fbc304995fb03356f878579e50d3dd8) ocelot.h (d8ea7ff3995ead5193313c72c0d97c9c16c83be9)
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/* Copyright (c) 2017 Microsemi Corporation
3 */
4
5#ifndef _SOC_MSCC_OCELOT_H
6#define _SOC_MSCC_OCELOT_H
7
8#include <linux/ptp_clock_kernel.h>

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49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
51 */
52
53/* Reserve some destination PGIDs at the end of the range:
54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
55 * of the switch port net devices, towards the CPU port module.
56 * PGID_UC: the flooding destinations for unknown unicast traffic.
1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/* Copyright (c) 2017 Microsemi Corporation
3 */
4
5#ifndef _SOC_MSCC_OCELOT_H
6#define _SOC_MSCC_OCELOT_H
7
8#include <linux/ptp_clock_kernel.h>

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49 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
50 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
51 */
52
53/* Reserve some destination PGIDs at the end of the range:
54 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
55 * of the switch port net devices, towards the CPU port module.
56 * PGID_UC: the flooding destinations for unknown unicast traffic.
57 * PGID_MC: the flooding destinations for broadcast and non-IP multicast
58 * traffic.
57 * PGID_MC: the flooding destinations for non-IP multicast traffic.
59 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
60 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
58 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
59 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
60 * PGID_BC: the flooding destinations for broadcast traffic.
61 */
61 */
62#define PGID_CPU 59
63#define PGID_UC 60
64#define PGID_MC 61
65#define PGID_MCIPV4 62
66#define PGID_MCIPV6 63
62#define PGID_CPU 58
63#define PGID_UC 59
64#define PGID_MC 60
65#define PGID_MCIPV4 61
66#define PGID_MCIPV6 62
67#define PGID_BC 63
67
68#define for_each_unicast_dest_pgid(ocelot, pgid) \
69 for ((pgid) = 0; \
70 (pgid) < (ocelot)->num_phys_ports; \
71 (pgid)++)
72
73#define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \
74 for ((pgid) = (ocelot)->num_phys_ports + 1; \

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81 (pgid)++)
82
83/* Aggregation PGIDs, one per Link Aggregation Code */
84#define PGID_AGGR 64
85
86/* Source PGIDs, one per physical port */
87#define PGID_SRC 80
88
68
69#define for_each_unicast_dest_pgid(ocelot, pgid) \
70 for ((pgid) = 0; \
71 (pgid) < (ocelot)->num_phys_ports; \
72 (pgid)++)
73
74#define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \
75 for ((pgid) = (ocelot)->num_phys_ports + 1; \

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82 (pgid)++)
83
84/* Aggregation PGIDs, one per Link Aggregation Code */
85#define PGID_AGGR 64
86
87/* Source PGIDs, one per physical port */
88#define PGID_SRC 80
89
89#define IFH_INJ_BYPASS BIT(31)
90#define IFH_INJ_POP_CNT_DISABLE (3 << 28)
91
92#define IFH_TAG_TYPE_C 0
93#define IFH_TAG_TYPE_S 1
94
95#define IFH_REW_OP_NOOP 0x0
96#define IFH_REW_OP_DSCP 0x1
97#define IFH_REW_OP_ONE_STEP_PTP 0x2
98#define IFH_REW_OP_TWO_STEP_PTP 0x3
99#define IFH_REW_OP_ORIGIN_PTP 0x5
100
90#define IFH_TAG_TYPE_C 0
91#define IFH_TAG_TYPE_S 1
92
93#define IFH_REW_OP_NOOP 0x0
94#define IFH_REW_OP_DSCP 0x1
95#define IFH_REW_OP_ONE_STEP_PTP 0x2
96#define IFH_REW_OP_TWO_STEP_PTP 0x3
97#define IFH_REW_OP_ORIGIN_PTP 0x5
98
101#define OCELOT_TAG_LEN 16
102#define OCELOT_SHORT_PREFIX_LEN 4
103#define OCELOT_LONG_PREFIX_LEN 16
104#define OCELOT_TOTAL_TAG_LEN (OCELOT_SHORT_PREFIX_LEN + OCELOT_TAG_LEN)
99#define OCELOT_NUM_TC 8
105
106#define OCELOT_SPEED_2500 0
107#define OCELOT_SPEED_1000 1
108#define OCELOT_SPEED_100 2
109#define OCELOT_SPEED_10 3
110
111#define OCELOT_PTP_PINS_NUM 4
112
113#define TARGET_OFFSET 24
114#define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
115#define REG(reg, offset) [reg & REG_MASK] = offset
116
117#define REG_RESERVED_ADDR 0xffffffff
118#define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
119
100
101#define OCELOT_SPEED_2500 0
102#define OCELOT_SPEED_1000 1
103#define OCELOT_SPEED_100 2
104#define OCELOT_SPEED_10 3
105
106#define OCELOT_PTP_PINS_NUM 4
107
108#define TARGET_OFFSET 24
109#define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
110#define REG(reg, offset) [reg & REG_MASK] = offset
111
112#define REG_RESERVED_ADDR 0xffffffff
113#define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
114
115#define OCELOT_MRP_CPUQ 7
116
120enum ocelot_target {
121 ANA = 1,
122 QS,
123 QSYS,
124 REW,
125 SYS,
126 S0,
127 S1,

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558
559struct ocelot;
560
561struct ocelot_ops {
562 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
563 int (*netdev_to_port)(struct net_device *dev);
564 int (*reset)(struct ocelot *ocelot);
565 u16 (*wm_enc)(u16 value);
117enum ocelot_target {
118 ANA = 1,
119 QS,
120 QSYS,
121 REW,
122 SYS,
123 S0,
124 S1,

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555
556struct ocelot;
557
558struct ocelot_ops {
559 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
560 int (*netdev_to_port)(struct net_device *dev);
561 int (*reset)(struct ocelot *ocelot);
562 u16 (*wm_enc)(u16 value);
563 u16 (*wm_dec)(u16 value);
564 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse);
566};
567
568struct ocelot_vcap_block {
569 struct list_head rules;
570 int count;
571 int pol_lpr;
572};
573
574struct ocelot_vlan {
575 bool valid;
576 u16 vid;
577};
578
565};
566
567struct ocelot_vcap_block {
568 struct list_head rules;
569 int count;
570 int pol_lpr;
571};
572
573struct ocelot_vlan {
574 bool valid;
575 u16 vid;
576};
577
578enum ocelot_sb {
579 OCELOT_SB_BUF,
580 OCELOT_SB_REF,
581 OCELOT_SB_NUM,
582};
583
584enum ocelot_sb_pool {
585 OCELOT_SB_POOL_ING,
586 OCELOT_SB_POOL_EGR,
587 OCELOT_SB_POOL_NUM,
588};
589
579struct ocelot_port {
580 struct ocelot *ocelot;
581
582 struct regmap *target;
583
584 bool vlan_aware;
585 /* VLAN that untagged frames are classified to, on ingress */
586 struct ocelot_vlan pvid_vlan;
587 /* The VLAN ID that will be transmitted as untagged, on egress */
588 struct ocelot_vlan native_vlan;
589
590 u8 ptp_cmd;
591 struct sk_buff_head tx_skbs;
592 u8 ts_id;
593 spinlock_t ts_id_lock;
594
595 phy_interface_t phy_mode;
596
597 u8 *xmit_template;
590struct ocelot_port {
591 struct ocelot *ocelot;
592
593 struct regmap *target;
594
595 bool vlan_aware;
596 /* VLAN that untagged frames are classified to, on ingress */
597 struct ocelot_vlan pvid_vlan;
598 /* The VLAN ID that will be transmitted as untagged, on egress */
599 struct ocelot_vlan native_vlan;
600
601 u8 ptp_cmd;
602 struct sk_buff_head tx_skbs;
603 u8 ts_id;
604 spinlock_t ts_id_lock;
605
606 phy_interface_t phy_mode;
607
608 u8 *xmit_template;
609 bool is_dsa_8021q_cpu;
610 bool learn_ena;
611
612 struct net_device *bond;
613 bool lag_tx_active;
598};
599
600struct ocelot {
601 struct device *dev;
614};
615
616struct ocelot {
617 struct device *dev;
618 struct devlink *devlink;
619 struct devlink_port *devlink_ports;
602
603 const struct ocelot_ops *ops;
604 struct regmap *targets[TARGET_MAX];
605 struct regmap_field *regfields[REGFIELD_MAX];
606 const u32 *const *map;
607 const struct ocelot_stat_layout *stats_layout;
608 unsigned int num_stats;
609
620
621 const struct ocelot_ops *ops;
622 struct regmap *targets[TARGET_MAX];
623 struct regmap_field *regfields[REGFIELD_MAX];
624 const u32 *const *map;
625 const struct ocelot_stat_layout *stats_layout;
626 unsigned int num_stats;
627
610 int shared_queue_sz;
628 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM];
629 int packet_buffer_size;
630 int num_frame_refs;
611 int num_mact_rows;
612
613 struct net_device *hw_bridge_dev;
614 u16 bridge_mask;
615 u16 bridge_fwd_mask;
616
617 struct ocelot_port **ports;
618

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627 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
628 * the CPU is located after the physical ports (at the
629 * num_phys_ports index).
630 */
631 u8 num_phys_ports;
632
633 int npi;
634
631 int num_mact_rows;
632
633 struct net_device *hw_bridge_dev;
634 u16 bridge_mask;
635 u16 bridge_fwd_mask;
636
637 struct ocelot_port **ports;
638

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647 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
648 * the CPU is located after the physical ports (at the
649 * num_phys_ports index).
650 */
651 u8 num_phys_ports;
652
653 int npi;
654
635 enum ocelot_tag_prefix inj_prefix;
636 enum ocelot_tag_prefix xtr_prefix;
655 enum ocelot_tag_prefix npi_inj_prefix;
656 enum ocelot_tag_prefix npi_xtr_prefix;
637
657
638 u32 *lags;
639
640 struct list_head multicast;
641 struct list_head pgids;
642
643 struct list_head dummy_rules;
644 struct ocelot_vcap_block block[3];
645 struct vcap_props *vcap;
646
647 /* Workqueue to check statistics for overflow with its lock */

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656 struct ptp_clock *ptp_clock;
657 struct ptp_clock_info ptp_info;
658 struct hwtstamp_config hwtstamp_config;
659 /* Protects the PTP interface state */
660 struct mutex ptp_lock;
661 /* Protects the PTP clock */
662 spinlock_t ptp_clock_lock;
663 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM];
658 struct list_head multicast;
659 struct list_head pgids;
660
661 struct list_head dummy_rules;
662 struct ocelot_vcap_block block[3];
663 struct vcap_props *vcap;
664
665 /* Workqueue to check statistics for overflow with its lock */

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674 struct ptp_clock *ptp_clock;
675 struct ptp_clock_info ptp_info;
676 struct hwtstamp_config hwtstamp_config;
677 /* Protects the PTP interface state */
678 struct mutex ptp_lock;
679 /* Protects the PTP clock */
680 spinlock_t ptp_clock_lock;
681 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM];
682
683#if IS_ENABLED(CONFIG_BRIDGE_MRP)
684 u16 mrp_ring_id;
685 struct net_device *mrp_p_port;
686 struct net_device *mrp_s_port;
687#endif
664};
665
666struct ocelot_policer {
667 u32 rate; /* kilobit per second */
668 u32 burst; /* bytes */
669};
670
671#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))

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714void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
715void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
716 u32 offset);
717u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
718 u32 reg, u32 offset);
719void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
720 u32 val, u32 reg, u32 offset);
721
688};
689
690struct ocelot_policer {
691 u32 rate; /* kilobit per second */
692 u32 burst; /* bytes */
693};
694
695#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))

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738void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
739void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
740 u32 offset);
741u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
742 u32 reg, u32 offset);
743void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
744 u32 val, u32 reg, u32 offset);
745
746/* Packet I/O */
747#if IS_ENABLED(CONFIG_MSCC_OCELOT_SWITCH_LIB)
748
749bool ocelot_can_inject(struct ocelot *ocelot, int grp);
750void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
751 u32 rew_op, struct sk_buff *skb);
752int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb);
753void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp);
754
755#else
756
757static inline bool ocelot_can_inject(struct ocelot *ocelot, int grp)
758{
759 return false;
760}
761
762static inline void ocelot_port_inject_frame(struct ocelot *ocelot, int port,
763 int grp, u32 rew_op,
764 struct sk_buff *skb)
765{
766}
767
768static inline int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp,
769 struct sk_buff **skb)
770{
771 return -EIO;
772}
773
774static inline void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
775{
776}
777
778#endif
779
722/* Hardware initialization */
723int ocelot_regfields_init(struct ocelot *ocelot,
724 const struct reg_field *const regfields);
725struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
726int ocelot_init(struct ocelot *ocelot);
727void ocelot_deinit(struct ocelot *ocelot);
728void ocelot_init_port(struct ocelot *ocelot, int port);
729void ocelot_deinit_port(struct ocelot *ocelot, int port);

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736void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
737int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
738int ocelot_get_ts_info(struct ocelot *ocelot, int port,
739 struct ethtool_ts_info *info);
740void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
741int ocelot_port_flush(struct ocelot *ocelot, int port);
742void ocelot_adjust_link(struct ocelot *ocelot, int port,
743 struct phy_device *phydev);
780/* Hardware initialization */
781int ocelot_regfields_init(struct ocelot *ocelot,
782 const struct reg_field *const regfields);
783struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
784int ocelot_init(struct ocelot *ocelot);
785void ocelot_deinit(struct ocelot *ocelot);
786void ocelot_init_port(struct ocelot *ocelot, int port);
787void ocelot_deinit_port(struct ocelot *ocelot, int port);

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794void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
795int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
796int ocelot_get_ts_info(struct ocelot *ocelot, int port,
797 struct ethtool_ts_info *info);
798void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
799int ocelot_port_flush(struct ocelot *ocelot, int port);
800void ocelot_adjust_link(struct ocelot *ocelot, int port,
801 struct phy_device *phydev);
744int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled,
745 struct switchdev_trans *trans);
802int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled);
746void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
803void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
804void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot);
805int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
806 struct switchdev_brport_flags val);
807void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
808 struct switchdev_brport_flags val);
747int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
748 struct net_device *bridge);
749int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
750 struct net_device *bridge);
751int ocelot_fdb_dump(struct ocelot *ocelot, int port,
752 dsa_fdb_dump_cb_t *cb, void *data);
753int ocelot_fdb_add(struct ocelot *ocelot, int port,
754 const unsigned char *addr, u16 vid);

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774int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
775 struct flow_cls_offload *f, bool ingress);
776int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
777 struct flow_cls_offload *f, bool ingress);
778int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
779 const struct switchdev_obj_port_mdb *mdb);
780int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
781 const struct switchdev_obj_port_mdb *mdb);
809int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
810 struct net_device *bridge);
811int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
812 struct net_device *bridge);
813int ocelot_fdb_dump(struct ocelot *ocelot, int port,
814 dsa_fdb_dump_cb_t *cb, void *data);
815int ocelot_fdb_add(struct ocelot *ocelot, int port,
816 const unsigned char *addr, u16 vid);

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836int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
837 struct flow_cls_offload *f, bool ingress);
838int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
839 struct flow_cls_offload *f, bool ingress);
840int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
841 const struct switchdev_obj_port_mdb *mdb);
842int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
843 const struct switchdev_obj_port_mdb *mdb);
844int ocelot_port_lag_join(struct ocelot *ocelot, int port,
845 struct net_device *bond,
846 struct netdev_lag_upper_info *info);
847void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
848 struct net_device *bond);
849void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active);
782
850
851int ocelot_devlink_sb_register(struct ocelot *ocelot);
852void ocelot_devlink_sb_unregister(struct ocelot *ocelot);
853int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index,
854 u16 pool_index,
855 struct devlink_sb_pool_info *pool_info);
856int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index,
857 u16 pool_index, u32 size,
858 enum devlink_sb_threshold_type threshold_type,
859 struct netlink_ext_ack *extack);
860int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port,
861 unsigned int sb_index, u16 pool_index,
862 u32 *p_threshold);
863int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port,
864 unsigned int sb_index, u16 pool_index,
865 u32 threshold, struct netlink_ext_ack *extack);
866int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port,
867 unsigned int sb_index, u16 tc_index,
868 enum devlink_sb_pool_type pool_type,
869 u16 *p_pool_index, u32 *p_threshold);
870int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port,
871 unsigned int sb_index, u16 tc_index,
872 enum devlink_sb_pool_type pool_type,
873 u16 pool_index, u32 threshold,
874 struct netlink_ext_ack *extack);
875int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index);
876int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index);
877int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port,
878 unsigned int sb_index, u16 pool_index,
879 u32 *p_cur, u32 *p_max);
880int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port,
881 unsigned int sb_index, u16 tc_index,
882 enum devlink_sb_pool_type pool_type,
883 u32 *p_cur, u32 *p_max);
884
885#if IS_ENABLED(CONFIG_BRIDGE_MRP)
886int ocelot_mrp_add(struct ocelot *ocelot, int port,
887 const struct switchdev_obj_mrp *mrp);
888int ocelot_mrp_del(struct ocelot *ocelot, int port,
889 const struct switchdev_obj_mrp *mrp);
890int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
891 const struct switchdev_obj_ring_role_mrp *mrp);
892int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
893 const struct switchdev_obj_ring_role_mrp *mrp);
894#else
895static inline int ocelot_mrp_add(struct ocelot *ocelot, int port,
896 const struct switchdev_obj_mrp *mrp)
897{
898 return -EOPNOTSUPP;
899}
900
901static inline int ocelot_mrp_del(struct ocelot *ocelot, int port,
902 const struct switchdev_obj_mrp *mrp)
903{
904 return -EOPNOTSUPP;
905}
906
907static inline int
908ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
909 const struct switchdev_obj_ring_role_mrp *mrp)
910{
911 return -EOPNOTSUPP;
912}
913
914static inline int
915ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
916 const struct switchdev_obj_ring_role_mrp *mrp)
917{
918 return -EOPNOTSUPP;
919}
783#endif
920#endif
921
922#endif