| at91_pmc.h (a5752e57bb63154fe9202d8d2282bad3bae3bced) | at91_pmc.h (df70aeef60839cb2732913fa41e61aba52ca942c) |
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| 1/* 2 * include/linux/clk/at91_pmc.h 3 * 4 * Copyright (C) 2005 Ivan Kokshaysky 5 * Copyright (C) SAN People 6 * 7 * Power Management Controller (PMC) - System peripherals registers. 8 * Based on AT91RM9200 datasheet revision E. --- 170 unchanged lines hidden (view full) --- 179#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ 180 181#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ 182#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ 183#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ 184 185#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ 186#define AT91_PMC_PCR_PID_MASK 0x3f | 1/* 2 * include/linux/clk/at91_pmc.h 3 * 4 * Copyright (C) 2005 Ivan Kokshaysky 5 * Copyright (C) SAN People 6 * 7 * Power Management Controller (PMC) - System peripherals registers. 8 * Based on AT91RM9200 datasheet revision E. --- 170 unchanged lines hidden (view full) --- 179#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ 180 181#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ 182#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ 183#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ 184 185#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ 186#define AT91_PMC_PCR_PID_MASK 0x3f |
| 187#define AT91_PMC_PCR_GCKCSS_OFFSET 8 188#define AT91_PMC_PCR_GCKCSS_MASK (0x7 << AT91_PMC_PCR_GCKCSS_OFFSET) 189#define AT91_PMC_PCR_GCKCSS(n) ((n) << AT91_PMC_PCR_GCKCSS_OFFSET) /* GCK Clock Source Selection */ |
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| 187#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ 188#define AT91_PMC_PCR_DIV_OFFSET 16 189#define AT91_PMC_PCR_DIV_MASK (0x3 << AT91_PMC_PCR_DIV_OFFSET) 190#define AT91_PMC_PCR_DIV(n) ((n) << AT91_PMC_PCR_DIV_OFFSET) /* Divisor Value */ | 190#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ 191#define AT91_PMC_PCR_DIV_OFFSET 16 192#define AT91_PMC_PCR_DIV_MASK (0x3 << AT91_PMC_PCR_DIV_OFFSET) 193#define AT91_PMC_PCR_DIV(n) ((n) << AT91_PMC_PCR_DIV_OFFSET) /* Divisor Value */ |
| 194#define AT91_PMC_PCR_GCKDIV_OFFSET 20 195#define AT91_PMC_PCR_GCKDIV_MASK (0xff << AT91_PMC_PCR_GCKDIV_OFFSET) 196#define AT91_PMC_PCR_GCKDIV(n) ((n) << AT91_PMC_PCR_GCKDIV_OFFSET) /* Generated Clock Divisor Value */ |
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| 191#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ | 197#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ |
| 198#define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */ |
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| 192 193#endif | 199 200#endif |