| exynos5420.h (f1615bbe9be4def59c3b3eaddb60722efeed16c2) | exynos5420.h (c0fb262bf226a5c943e4309662353d5fb905310a) |
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| 1/* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Author: Andrzej Haja <a.hajda@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * --- 189 unchanged lines hidden (view full) --- 198#define CLK_ACLK_FL1550_CAM 519 199#define CLK_ACLK550_CAM 520 200 201/* mux clocks */ 202#define CLK_MOUT_HDMI 640 203#define CLK_MOUT_G3D 641 204#define CLK_MOUT_VPLL 642 205#define CLK_MOUT_MAUDIO0 643 | 1/* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Author: Andrzej Haja <a.hajda@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * --- 189 unchanged lines hidden (view full) --- 198#define CLK_ACLK_FL1550_CAM 519 199#define CLK_ACLK550_CAM 520 200 201/* mux clocks */ 202#define CLK_MOUT_HDMI 640 203#define CLK_MOUT_G3D 641 204#define CLK_MOUT_VPLL 642 205#define CLK_MOUT_MAUDIO0 643 |
| 206#define CLK_MOUT_USER_ACLK333 644 207#define CLK_MOUT_SW_ACLK333 645 |
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| 206 207/* divider clocks */ 208#define CLK_DOUT_PIXEL 768 209 210/* must be greater than maximal clock id */ 211#define CLK_NR_CLKS 769 212 213#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ | 208 209/* divider clocks */ 210#define CLK_DOUT_PIXEL 768 211 212/* must be greater than maximal clock id */ 213#define CLK_NR_CLKS 769 214 215#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ |