| exynos5420.h (3f1cc53b5f6f26e80e3176936714ec5dcab74244) | exynos5420.h (f493602db56beee1514b37180599a1f3f66f816e) |
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| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Author: Andrzej Hajda <a.hajda@samsung.com> 5 * 6 * Device Tree binding constants for Exynos5420 clock controller. 7 */ 8 --- 217 unchanged lines hidden (view full) --- 226#define CLK_MOUT_BPLL 655 227#define CLK_MOUT_MX_MSPLL_CCORE 656 228#define CLK_MOUT_EPLL 657 229#define CLK_MOUT_MAU_EPLL 658 230#define CLK_MOUT_USER_MAU_EPLL 659 231#define CLK_MOUT_SCLK_SPLL 660 232#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 233#define CLK_MOUT_SW_ACLK_G3D 662 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Author: Andrzej Hajda <a.hajda@samsung.com> 5 * 6 * Device Tree binding constants for Exynos5420 clock controller. 7 */ 8 --- 217 unchanged lines hidden (view full) --- 226#define CLK_MOUT_BPLL 655 227#define CLK_MOUT_MX_MSPLL_CCORE 656 228#define CLK_MOUT_EPLL 657 229#define CLK_MOUT_MAU_EPLL 658 230#define CLK_MOUT_USER_MAU_EPLL 659 231#define CLK_MOUT_SCLK_SPLL 660 232#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 233#define CLK_MOUT_SW_ACLK_G3D 662 |
| 234#define CLK_MOUT_APLL 663 235#define CLK_MOUT_MSPLL_CPU 664 236#define CLK_MOUT_KPLL 665 237#define CLK_MOUT_MSPLL_KFC 666 |
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| 235/* divider clocks */ 236#define CLK_DOUT_PIXEL 768 237#define CLK_DOUT_ACLK400_WCORE 769 238#define CLK_DOUT_ACLK400_ISP 770 239#define CLK_DOUT_ACLK400_MSCL 771 240#define CLK_DOUT_ACLK200 772 241#define CLK_DOUT_ACLK200_FSYS2 773 242#define CLK_DOUT_ACLK100_NOC 774 --- 30 unchanged lines hidden --- | 240/* divider clocks */ 241#define CLK_DOUT_PIXEL 768 242#define CLK_DOUT_ACLK400_WCORE 769 243#define CLK_DOUT_ACLK400_ISP 770 244#define CLK_DOUT_ACLK400_MSCL 771 245#define CLK_DOUT_ACLK200 772 246#define CLK_DOUT_ACLK200_FSYS2 773 247#define CLK_DOUT_ACLK100_NOC 774 --- 30 unchanged lines hidden --- |