| exynos5420.h (3eb66e91a25497065c5322b1268cbc3953642227) | exynos5420.h (cc9bdecf4b8d20b3d3d0f8a6cb3e577548b5539f) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Author: Andrzej Hajda <a.hajda@samsung.com> 5 * 6 * Device Tree binding constants for Exynos5420 clock controller. 7 */ 8 --- 46 unchanged lines hidden (view full) --- 55#define CLK_SCLK_UNIPRO 154 56#define CLK_SCLK_PWM 155 57#define CLK_SCLK_GSCL_WA 156 58#define CLK_SCLK_GSCL_WB 157 59#define CLK_SCLK_HDMIPHY 158 60#define CLK_MAU_EPLL 159 61#define CLK_SCLK_HSIC_12M 160 62#define CLK_SCLK_MPHY_IXTAL24 161 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Author: Andrzej Hajda <a.hajda@samsung.com> 5 * 6 * Device Tree binding constants for Exynos5420 clock controller. 7 */ 8 --- 46 unchanged lines hidden (view full) --- 55#define CLK_SCLK_UNIPRO 154 56#define CLK_SCLK_PWM 155 57#define CLK_SCLK_GSCL_WA 156 58#define CLK_SCLK_GSCL_WB 157 59#define CLK_SCLK_HDMIPHY 158 60#define CLK_MAU_EPLL 159 61#define CLK_SCLK_HSIC_12M 160 62#define CLK_SCLK_MPHY_IXTAL24 161 |
| 63#define CLK_SCLK_BPLL 162 |
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| 63 64/* gate clocks */ 65#define CLK_UART0 257 66#define CLK_UART1 258 67#define CLK_UART2 259 68#define CLK_UART3 260 69#define CLK_I2C0 261 70#define CLK_I2C1 262 --- 119 unchanged lines hidden (view full) --- 190#define CLK_SCLK_PWM_ISP 513 191#define CLK_SCLK_ISP_SENSOR0 514 192#define CLK_SCLK_ISP_SENSOR1 515 193#define CLK_SCLK_ISP_SENSOR2 516 194#define CLK_ACLK432_SCALER 517 195#define CLK_ACLK432_CAM 518 196#define CLK_ACLK_FL1550_CAM 519 197#define CLK_ACLK550_CAM 520 | 64 65/* gate clocks */ 66#define CLK_UART0 257 67#define CLK_UART1 258 68#define CLK_UART2 259 69#define CLK_UART3 260 70#define CLK_I2C0 261 71#define CLK_I2C1 262 --- 119 unchanged lines hidden (view full) --- 191#define CLK_SCLK_PWM_ISP 513 192#define CLK_SCLK_ISP_SENSOR0 514 193#define CLK_SCLK_ISP_SENSOR1 515 194#define CLK_SCLK_ISP_SENSOR2 516 195#define CLK_ACLK432_SCALER 517 196#define CLK_ACLK432_CAM 518 197#define CLK_ACLK_FL1550_CAM 519 198#define CLK_ACLK550_CAM 520 |
| 199#define CLK_CLKM_PHY0 521 200#define CLK_CLKM_PHY1 522 201#define CLK_ACLK_PPMU_DREX0_0 523 202#define CLK_ACLK_PPMU_DREX0_1 524 203#define CLK_ACLK_PPMU_DREX1_0 525 204#define CLK_ACLK_PPMU_DREX1_1 526 205#define CLK_PCLK_PPMU_DREX0_0 527 206#define CLK_PCLK_PPMU_DREX0_1 528 207#define CLK_PCLK_PPMU_DREX1_0 529 208#define CLK_PCLK_PPMU_DREX1_1 530 |
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| 198 199/* mux clocks */ 200#define CLK_MOUT_HDMI 640 201#define CLK_MOUT_G3D 641 202#define CLK_MOUT_VPLL 642 203#define CLK_MOUT_MAUDIO0 643 204#define CLK_MOUT_USER_ACLK333 644 205#define CLK_MOUT_SW_ACLK333 645 --- 6 unchanged lines hidden (view full) --- 212#define CLK_MOUT_USER_ACLK300_GSCL 652 213#define CLK_MOUT_SW_ACLK300_GSCL 653 214#define CLK_MOUT_MCLK_CDREX 654 215#define CLK_MOUT_BPLL 655 216#define CLK_MOUT_MX_MSPLL_CCORE 656 217#define CLK_MOUT_EPLL 657 218#define CLK_MOUT_MAU_EPLL 658 219#define CLK_MOUT_USER_MAU_EPLL 659 | 209 210/* mux clocks */ 211#define CLK_MOUT_HDMI 640 212#define CLK_MOUT_G3D 641 213#define CLK_MOUT_VPLL 642 214#define CLK_MOUT_MAUDIO0 643 215#define CLK_MOUT_USER_ACLK333 644 216#define CLK_MOUT_SW_ACLK333 645 --- 6 unchanged lines hidden (view full) --- 223#define CLK_MOUT_USER_ACLK300_GSCL 652 224#define CLK_MOUT_SW_ACLK300_GSCL 653 225#define CLK_MOUT_MCLK_CDREX 654 226#define CLK_MOUT_BPLL 655 227#define CLK_MOUT_MX_MSPLL_CCORE 656 228#define CLK_MOUT_EPLL 657 229#define CLK_MOUT_MAU_EPLL 658 230#define CLK_MOUT_USER_MAU_EPLL 659 |
| 231#define CLK_MOUT_SCLK_SPLL 660 232#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 |
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| 220 221/* divider clocks */ 222#define CLK_DOUT_PIXEL 768 223#define CLK_DOUT_ACLK400_WCORE 769 224#define CLK_DOUT_ACLK400_ISP 770 225#define CLK_DOUT_ACLK400_MSCL 771 226#define CLK_DOUT_ACLK200 772 227#define CLK_DOUT_ACLK200_FSYS2 773 --- 15 unchanged lines hidden (view full) --- 243#define CLK_DOUT_ACLK300_GSCL 789 244#define CLK_DOUT_ACLK400_DISP1 790 245#define CLK_DOUT_PCLK_CDREX 791 246#define CLK_DOUT_SCLK_CDREX 792 247#define CLK_DOUT_ACLK_CDREX1 793 248#define CLK_DOUT_CCLK_DREX0 794 249#define CLK_DOUT_CLK2X_PHY0 795 250#define CLK_DOUT_PCLK_CORE_MEM 796 | 233 234/* divider clocks */ 235#define CLK_DOUT_PIXEL 768 236#define CLK_DOUT_ACLK400_WCORE 769 237#define CLK_DOUT_ACLK400_ISP 770 238#define CLK_DOUT_ACLK400_MSCL 771 239#define CLK_DOUT_ACLK200 772 240#define CLK_DOUT_ACLK200_FSYS2 773 --- 15 unchanged lines hidden (view full) --- 256#define CLK_DOUT_ACLK300_GSCL 789 257#define CLK_DOUT_ACLK400_DISP1 790 258#define CLK_DOUT_PCLK_CDREX 791 259#define CLK_DOUT_SCLK_CDREX 792 260#define CLK_DOUT_ACLK_CDREX1 793 261#define CLK_DOUT_CCLK_DREX0 794 262#define CLK_DOUT_CLK2X_PHY0 795 263#define CLK_DOUT_PCLK_CORE_MEM 796 |
| 264#define CLK_FF_DOUT_SPLL2 797 265#define CLK_DOUT_PCLK_DREX0 798 266#define CLK_DOUT_PCLK_DREX1 799 |
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| 251 252/* must be greater than maximal clock id */ | 267 268/* must be greater than maximal clock id */ |
| 253#define CLK_NR_CLKS 797 | 269#define CLK_NR_CLKS 800 |
| 254 255#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ | 270 271#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ |