| exynos5420.h (0898782247ae533d1f4e47a06bc5d4870931b284) | exynos5420.h (3f1cc53b5f6f26e80e3176936714ec5dcab74244) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Author: Andrzej Hajda <a.hajda@samsung.com> 5 * 6 * Device Tree binding constants for Exynos5420 clock controller. 7 */ 8 --- 216 unchanged lines hidden (view full) --- 225#define CLK_MOUT_MCLK_CDREX 654 226#define CLK_MOUT_BPLL 655 227#define CLK_MOUT_MX_MSPLL_CCORE 656 228#define CLK_MOUT_EPLL 657 229#define CLK_MOUT_MAU_EPLL 658 230#define CLK_MOUT_USER_MAU_EPLL 659 231#define CLK_MOUT_SCLK_SPLL 660 232#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Author: Andrzej Hajda <a.hajda@samsung.com> 5 * 6 * Device Tree binding constants for Exynos5420 clock controller. 7 */ 8 --- 216 unchanged lines hidden (view full) --- 225#define CLK_MOUT_MCLK_CDREX 654 226#define CLK_MOUT_BPLL 655 227#define CLK_MOUT_MX_MSPLL_CCORE 656 228#define CLK_MOUT_EPLL 657 229#define CLK_MOUT_MAU_EPLL 658 230#define CLK_MOUT_USER_MAU_EPLL 659 231#define CLK_MOUT_SCLK_SPLL 660 232#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 |
| 233#define CLK_MOUT_SW_ACLK_G3D 662 |
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| 233 234/* divider clocks */ 235#define CLK_DOUT_PIXEL 768 236#define CLK_DOUT_ACLK400_WCORE 769 237#define CLK_DOUT_ACLK400_ISP 770 238#define CLK_DOUT_ACLK400_MSCL 771 239#define CLK_DOUT_ACLK200 772 240#define CLK_DOUT_ACLK200_FSYS2 773 --- 31 unchanged lines hidden --- | 234 235/* divider clocks */ 236#define CLK_DOUT_PIXEL 768 237#define CLK_DOUT_ACLK400_WCORE 769 238#define CLK_DOUT_ACLK400_ISP 770 239#define CLK_DOUT_ACLK400_MSCL 771 240#define CLK_DOUT_ACLK200 772 241#define CLK_DOUT_ACLK200_FSYS2 773 --- 31 unchanged lines hidden --- |