| exynos5250.h (3eb66e91a25497065c5322b1268cbc3953642227) | exynos5250.h (f493602db56beee1514b37180599a1f3f66f816e) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Author: Andrzej Hajda <a.hajda@samsung.com> 5 * 6 * Device Tree binding constants for Exynos5250 clock controller. 7 */ 8 --- 158 unchanged lines hidden (view full) --- 167#define CLK_SMMU_FIMC_LITE1 364 168#define CLK_CAMIF_TOP 365 169 170/* mux clocks */ 171#define CLK_MOUT_HDMI 1024 172#define CLK_MOUT_GPLL 1025 173#define CLK_MOUT_ACLK200_DISP1_SUB 1026 174#define CLK_MOUT_ACLK300_DISP1_SUB 1027 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Author: Andrzej Hajda <a.hajda@samsung.com> 5 * 6 * Device Tree binding constants for Exynos5250 clock controller. 7 */ 8 --- 158 unchanged lines hidden (view full) --- 167#define CLK_SMMU_FIMC_LITE1 364 168#define CLK_CAMIF_TOP 365 169 170/* mux clocks */ 171#define CLK_MOUT_HDMI 1024 172#define CLK_MOUT_GPLL 1025 173#define CLK_MOUT_ACLK200_DISP1_SUB 1026 174#define CLK_MOUT_ACLK300_DISP1_SUB 1027 |
| 175#define CLK_MOUT_APLL 1028 176#define CLK_MOUT_MPLL 1029 |
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| 175 176/* must be greater than maximal clock id */ | 177 178/* must be greater than maximal clock id */ |
| 177#define CLK_NR_CLKS 1028 | 179#define CLK_NR_CLKS 1030 |
| 178 179#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ | 180 181#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ |