io_ti.h (1da177e4c3f41524e886b7f1b8a0c1fc7321cac2) io_ti.h (a320471147fe61ed9260295958f07cc23ec360c8)
1/*****************************************************************************
1/*****************************************************************************
2 *
3 * Copyright (C) 1997-2002 Inside Out Networks, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *

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17#ifndef _IO_TI_H_
18#define _IO_TI_H_
19
20/* Address Space */
21#define DTK_ADDR_SPACE_XDATA 0x03 /* Addr is placed in XDATA space */
22#define DTK_ADDR_SPACE_I2C_TYPE_II 0x82 /* Addr is placed in I2C area */
23#define DTK_ADDR_SPACE_I2C_TYPE_III 0x83 /* Addr is placed in I2C area */
24
2 *
3 * Copyright (C) 1997-2002 Inside Out Networks, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *

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17#ifndef _IO_TI_H_
18#define _IO_TI_H_
19
20/* Address Space */
21#define DTK_ADDR_SPACE_XDATA 0x03 /* Addr is placed in XDATA space */
22#define DTK_ADDR_SPACE_I2C_TYPE_II 0x82 /* Addr is placed in I2C area */
23#define DTK_ADDR_SPACE_I2C_TYPE_III 0x83 /* Addr is placed in I2C area */
24
25// UART Defines
26#define UMPMEM_BASE_UART1 0xFFA0 /* UMP UART1 base address */
27#define UMPMEM_BASE_UART2 0xFFB0 /* UMP UART2 base address */
28#define UMPMEM_OFFS_UART_LSR 0x05 /* UMP UART LSR register offset */
25/* UART Defines */
26#define UMPMEM_BASE_UART1 0xFFA0 /* UMP UART1 base address */
27#define UMPMEM_BASE_UART2 0xFFB0 /* UMP UART2 base address */
28#define UMPMEM_OFFS_UART_LSR 0x05 /* UMP UART LSR register offset */
29
30/* Bits per character */
31#define UMP_UART_CHAR5BITS 0x00
32#define UMP_UART_CHAR6BITS 0x01
33#define UMP_UART_CHAR7BITS 0x02
34#define UMP_UART_CHAR8BITS 0x03
35
36/* Parity */

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49#define UMP_UART_LSR_OV_MASK 0x01
50#define UMP_UART_LSR_PE_MASK 0x02
51#define UMP_UART_LSR_FE_MASK 0x04
52#define UMP_UART_LSR_BR_MASK 0x08
53#define UMP_UART_LSR_ER_MASK 0x0F
54#define UMP_UART_LSR_RX_MASK 0x10
55#define UMP_UART_LSR_TX_MASK 0x20
56
29
30/* Bits per character */
31#define UMP_UART_CHAR5BITS 0x00
32#define UMP_UART_CHAR6BITS 0x01
33#define UMP_UART_CHAR7BITS 0x02
34#define UMP_UART_CHAR8BITS 0x03
35
36/* Parity */

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49#define UMP_UART_LSR_OV_MASK 0x01
50#define UMP_UART_LSR_PE_MASK 0x02
51#define UMP_UART_LSR_FE_MASK 0x04
52#define UMP_UART_LSR_BR_MASK 0x08
53#define UMP_UART_LSR_ER_MASK 0x0F
54#define UMP_UART_LSR_RX_MASK 0x10
55#define UMP_UART_LSR_TX_MASK 0x20
56
57#define UMP_UART_LSR_DATA_MASK ( LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK )
57#define UMP_UART_LSR_DATA_MASK (LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK)
58
59/* Port Settings Constants) */
60#define UMP_MASK_UART_FLAGS_RTS_FLOW 0x0001
61#define UMP_MASK_UART_FLAGS_RTS_DISABLE 0x0002
62#define UMP_MASK_UART_FLAGS_PARITY 0x0008
63#define UMP_MASK_UART_FLAGS_OUT_X_DSR_FLOW 0x0010
64#define UMP_MASK_UART_FLAGS_OUT_X_CTS_FLOW 0x0020
65#define UMP_MASK_UART_FLAGS_OUT_X 0x0040

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74#define UMP_PIPE_TRANS_TIMEOUT_ENA 0x80
75#define UMP_PIPE_TRANSFER_MODE_MASK 0x03
76#define UMP_PIPE_TRANS_TIMEOUT_MASK 0x7C
77
78/* Purge port Direction Mask Bits */
79#define UMP_PORT_DIR_OUT 0x01
80#define UMP_PORT_DIR_IN 0x02
81
58
59/* Port Settings Constants) */
60#define UMP_MASK_UART_FLAGS_RTS_FLOW 0x0001
61#define UMP_MASK_UART_FLAGS_RTS_DISABLE 0x0002
62#define UMP_MASK_UART_FLAGS_PARITY 0x0008
63#define UMP_MASK_UART_FLAGS_OUT_X_DSR_FLOW 0x0010
64#define UMP_MASK_UART_FLAGS_OUT_X_CTS_FLOW 0x0020
65#define UMP_MASK_UART_FLAGS_OUT_X 0x0040

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74#define UMP_PIPE_TRANS_TIMEOUT_ENA 0x80
75#define UMP_PIPE_TRANSFER_MODE_MASK 0x03
76#define UMP_PIPE_TRANS_TIMEOUT_MASK 0x7C
77
78/* Purge port Direction Mask Bits */
79#define UMP_PORT_DIR_OUT 0x01
80#define UMP_PORT_DIR_IN 0x02
81
82// Address of Port 0
83#define UMPM_UART1_PORT 0x03
82/* Address of Port 0 */
83#define UMPM_UART1_PORT 0x03
84
84
85// Commands
86#define UMPC_SET_CONFIG 0x05
87#define UMPC_OPEN_PORT 0x06
88#define UMPC_CLOSE_PORT 0x07
89#define UMPC_START_PORT 0x08
90#define UMPC_STOP_PORT 0x09
91#define UMPC_TEST_PORT 0x0A
92#define UMPC_PURGE_PORT 0x0B
85/* Commands */
86#define UMPC_SET_CONFIG 0x05
87#define UMPC_OPEN_PORT 0x06
88#define UMPC_CLOSE_PORT 0x07
89#define UMPC_START_PORT 0x08
90#define UMPC_STOP_PORT 0x09
91#define UMPC_TEST_PORT 0x0A
92#define UMPC_PURGE_PORT 0x0B
93
93
94#define UMPC_COMPLETE_READ 0x80 // Force the Firmware to complete the current Read
95#define UMPC_HARDWARE_RESET 0x81 // Force UMP back into BOOT Mode
96#define UMPC_COPY_DNLD_TO_I2C 0x82 // Copy current download image to type 0xf2 record in 16k I2C
97 // firmware will change 0xff record to type 2 record when complete
94/* Force the Firmware to complete the current Read */
95#define UMPC_COMPLETE_READ 0x80
96/* Force UMP back into BOOT Mode */
97#define UMPC_HARDWARE_RESET 0x81
98/*
99 * Copy current download image to type 0xf2 record in 16k I2C
100 * firmware will change 0xff record to type 2 record when complete
101 */
102#define UMPC_COPY_DNLD_TO_I2C 0x82
98
103
99 // Special function register commands
100 // wIndex is register address
101 // wValue is MSB/LSB mask/data
102#define UMPC_WRITE_SFR 0x83 // Write SFR Register
104/*
105 * Special function register commands
106 * wIndex is register address
107 * wValue is MSB/LSB mask/data
108 */
109#define UMPC_WRITE_SFR 0x83 /* Write SFR Register */
103
110
104 // wIndex is register address
105#define UMPC_READ_SFR 0x84 // Read SRF Register
111/* wIndex is register address */
112#define UMPC_READ_SFR 0x84 /* Read SRF Register */
106
113
107 // Set or Clear DTR (wValue bit 0 Set/Clear) wIndex ModuleID (port)
114/* Set or Clear DTR (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
108#define UMPC_SET_CLR_DTR 0x85
109
115#define UMPC_SET_CLR_DTR 0x85
116
110 // Set or Clear RTS (wValue bit 0 Set/Clear) wIndex ModuleID (port)
117/* Set or Clear RTS (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
111#define UMPC_SET_CLR_RTS 0x86
112
118#define UMPC_SET_CLR_RTS 0x86
119
113 // Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port)
120/* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
114#define UMPC_SET_CLR_LOOPBACK 0x87
115
121#define UMPC_SET_CLR_LOOPBACK 0x87
122
116 // Set or Clear BREAK (wValue bit 0 Set/Clear) wIndex ModuleID (port)
123/* Set or Clear BREAK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
117#define UMPC_SET_CLR_BREAK 0x88
118
124#define UMPC_SET_CLR_BREAK 0x88
125
119 // Read MSR wIndex ModuleID (port)
126/* Read MSR wIndex ModuleID (port) */
120#define UMPC_READ_MSR 0x89
121
127#define UMPC_READ_MSR 0x89
128
122 /* Toolkit commands */
123 /* Read-write group */
124#define UMPC_MEMORY_READ 0x92
125#define UMPC_MEMORY_WRITE 0x93
129/* Toolkit commands */
130/* Read-write group */
131#define UMPC_MEMORY_READ 0x92
132#define UMPC_MEMORY_WRITE 0x93
126
127/*
128 * UMP DMA Definitions
129 */
130#define UMPD_OEDB1_ADDRESS 0xFF08
131#define UMPD_OEDB2_ADDRESS 0xFF10
132
133
134/*
135 * UMP DMA Definitions
136 */
137#define UMPD_OEDB1_ADDRESS 0xFF08
138#define UMPD_OEDB2_ADDRESS 0xFF10
139
133struct out_endpoint_desc_block
134{
140struct out_endpoint_desc_block {
135 __u8 Configuration;
136 __u8 XBufAddr;
137 __u8 XByteCount;
138 __u8 Unused1;
139 __u8 Unused2;
140 __u8 YBufAddr;
141 __u8 YByteCount;
142 __u8 BufferSize;
143} __attribute__((packed));
144
145
146/*
147 * TYPE DEFINITIONS
148 * Structures for Firmware commands
149 */
141 __u8 Configuration;
142 __u8 XBufAddr;
143 __u8 XByteCount;
144 __u8 Unused1;
145 __u8 Unused2;
146 __u8 YBufAddr;
147 __u8 YByteCount;
148 __u8 BufferSize;
149} __attribute__((packed));
150
151
152/*
153 * TYPE DEFINITIONS
154 * Structures for Firmware commands
155 */
150struct ump_uart_config /* UART settings */
151{
156/* UART settings */
157struct ump_uart_config {
152 __u16 wBaudRate; /* Baud rate */
153 __u16 wFlags; /* Bitmap mask of flags */
154 __u8 bDataBits; /* 5..8 - data bits per character */
155 __u8 bParity; /* Parity settings */
156 __u8 bStopBits; /* Stop bits settings */
157 char cXon; /* XON character */
158 char cXoff; /* XOFF character */
159 __u8 bUartMode; /* Will be updated when a user */
160 /* interface is defined */
161} __attribute__((packed));
162
163
164/*
165 * TYPE DEFINITIONS
166 * Structures for USB interrupts
167 */
158 __u16 wBaudRate; /* Baud rate */
159 __u16 wFlags; /* Bitmap mask of flags */
160 __u8 bDataBits; /* 5..8 - data bits per character */
161 __u8 bParity; /* Parity settings */
162 __u8 bStopBits; /* Stop bits settings */
163 char cXon; /* XON character */
164 char cXoff; /* XOFF character */
165 __u8 bUartMode; /* Will be updated when a user */
166 /* interface is defined */
167} __attribute__((packed));
168
169
170/*
171 * TYPE DEFINITIONS
172 * Structures for USB interrupts
173 */
168struct ump_interrupt /* Interrupt packet structure */
169{
174/* Interrupt packet structure */
175struct ump_interrupt {
170 __u8 bICode; /* Interrupt code (interrupt num) */
171 __u8 bIInfo; /* Interrupt information */
172} __attribute__((packed));
173
174
175#define TIUMP_GET_PORT_FROM_CODE(c) (((c) >> 4) - 3)
176#define TIUMP_GET_FUNC_FROM_CODE(c) ((c) & 0x0f)
177#define TIUMP_INTERRUPT_CODE_LSR 0x03
178#define TIUMP_INTERRUPT_CODE_MSR 0x04
179
180#endif
176 __u8 bICode; /* Interrupt code (interrupt num) */
177 __u8 bIInfo; /* Interrupt information */
178} __attribute__((packed));
179
180
181#define TIUMP_GET_PORT_FROM_CODE(c) (((c) >> 4) - 3)
182#define TIUMP_GET_FUNC_FROM_CODE(c) ((c) & 0x0f)
183#define TIUMP_INTERRUPT_CODE_LSR 0x03
184#define TIUMP_INTERRUPT_CODE_MSR 0x04
185
186#endif