cp210x.c (c441bfb5f2866de71e092c1b9d866a65978dfe1a) cp210x.c (6f7ec77cc8b64ff5037c1945e4650c65c458037d)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Silicon Laboratories CP210x USB to RS232 serial adaptor driver
4 *
5 * Copyright (C) 2005 Craig Shelley (craig@microtron.org.uk)
6 * Copyright (C) 2010-2021 Johan Hovold (johan@kernel.org)
7 *
8 * Support to set flow control line levels using TIOCMGET and TIOCMSET

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532#define CP2104_GPIO2_RS485_MODE BIT(2)
533
534/* CP2102N configuration array indices */
535#define CP210X_2NCONFIG_CONFIG_VERSION_IDX 2
536#define CP210X_2NCONFIG_GPIO_MODE_IDX 581
537#define CP210X_2NCONFIG_GPIO_RSTLATCH_IDX 587
538#define CP210X_2NCONFIG_GPIO_CONTROL_IDX 600
539
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Silicon Laboratories CP210x USB to RS232 serial adaptor driver
4 *
5 * Copyright (C) 2005 Craig Shelley (craig@microtron.org.uk)
6 * Copyright (C) 2010-2021 Johan Hovold (johan@kernel.org)
7 *
8 * Support to set flow control line levels using TIOCMGET and TIOCMSET

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532#define CP2104_GPIO2_RS485_MODE BIT(2)
533
534/* CP2102N configuration array indices */
535#define CP210X_2NCONFIG_CONFIG_VERSION_IDX 2
536#define CP210X_2NCONFIG_GPIO_MODE_IDX 581
537#define CP210X_2NCONFIG_GPIO_RSTLATCH_IDX 587
538#define CP210X_2NCONFIG_GPIO_CONTROL_IDX 600
539
540/* CP2102N QFN20 port configuration values */
541#define CP2102N_QFN20_GPIO2_TXLED_MODE BIT(2)
542#define CP2102N_QFN20_GPIO3_RXLED_MODE BIT(3)
543#define CP2102N_QFN20_GPIO1_RS485_MODE BIT(4)
544#define CP2102N_QFN20_GPIO0_CLK_MODE BIT(6)
545
540/* CP210X_VENDOR_SPECIFIC, CP210X_WRITE_LATCH call writes these 0x2 bytes. */
541struct cp210x_gpio_write {
542 u8 mask;
543 u8 state;
544};
545
546/*
547 * Helper to get interface number when we only have struct usb_serial.

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1728 * the direction of an open-drain pin.
1729 */
1730 gpio_latch = (gpio_rst_latch >> 3) & 0x0f;
1731
1732 /* 0 indicates open-drain mode, 1 is push-pull */
1733 priv->gpio_pushpull = (gpio_pushpull >> 3) & 0x0f;
1734
1735 /* 0 indicates GPIO mode, 1 is alternate function */
546/* CP210X_VENDOR_SPECIFIC, CP210X_WRITE_LATCH call writes these 0x2 bytes. */
547struct cp210x_gpio_write {
548 u8 mask;
549 u8 state;
550};
551
552/*
553 * Helper to get interface number when we only have struct usb_serial.

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1734 * the direction of an open-drain pin.
1735 */
1736 gpio_latch = (gpio_rst_latch >> 3) & 0x0f;
1737
1738 /* 0 indicates open-drain mode, 1 is push-pull */
1739 priv->gpio_pushpull = (gpio_pushpull >> 3) & 0x0f;
1740
1741 /* 0 indicates GPIO mode, 1 is alternate function */
1736 priv->gpio_altfunc = (gpio_ctrl >> 2) & 0x0f;
1742 if (priv->partnum == CP210X_PARTNUM_CP2102N_QFN20) {
1743 /* QFN20 is special... */
1744 if (gpio_ctrl & CP2102N_QFN20_GPIO0_CLK_MODE) /* GPIO 0 */
1745 priv->gpio_altfunc |= BIT(0);
1746 if (gpio_ctrl & CP2102N_QFN20_GPIO1_RS485_MODE) /* GPIO 1 */
1747 priv->gpio_altfunc |= BIT(1);
1748 if (gpio_ctrl & CP2102N_QFN20_GPIO2_TXLED_MODE) /* GPIO 2 */
1749 priv->gpio_altfunc |= BIT(2);
1750 if (gpio_ctrl & CP2102N_QFN20_GPIO3_RXLED_MODE) /* GPIO 3 */
1751 priv->gpio_altfunc |= BIT(3);
1752 } else {
1753 priv->gpio_altfunc = (gpio_ctrl >> 2) & 0x0f;
1754 }
1737
1738 if (priv->partnum == CP210X_PARTNUM_CP2102N_QFN28) {
1739 /*
1740 * For the QFN28 package, GPIO4-6 are controlled by
1741 * the low three bits of the mode/latch fields.
1742 * Contrary to the document linked above, the bits for
1743 * the SUSPEND pins are elsewhere. No alternate
1744 * function is available for these pins.

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1755
1756 if (priv->partnum == CP210X_PARTNUM_CP2102N_QFN28) {
1757 /*
1758 * For the QFN28 package, GPIO4-6 are controlled by
1759 * the low three bits of the mode/latch fields.
1760 * Contrary to the document linked above, the bits for
1761 * the SUSPEND pins are elsewhere. No alternate
1762 * function is available for these pins.

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