r8a66597.h (29fab0cd897519be9009ba8c898410ab83b378e9) r8a66597.h (9424ea29658ce5bcdcf527ddf9617b9507ddf1aa)
1/*
2 * R8A66597 HCD (Host Controller Driver)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
6 * Portions Copyright (C) 2004-2005 David Brownell
7 * Portions Copyright (C) 1999 Roman Weissgaerber
8 *

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182#define DENDE 0x0010 /* b4: Dend enable */
183#define OBUS 0x0004 /* b2: OUTbus mode */
184
185/* CFIFO/DxFIFO Port Select Register */
186#define RCNT 0x8000 /* b15: Read count mode */
187#define REW 0x4000 /* b14: Buffer rewind */
188#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
189#define DREQE 0x1000 /* b12: DREQ output enable */
1/*
2 * R8A66597 HCD (Host Controller Driver)
3 *
4 * Copyright (C) 2006-2007 Renesas Solutions Corp.
5 * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
6 * Portions Copyright (C) 2004-2005 David Brownell
7 * Portions Copyright (C) 1999 Roman Weissgaerber
8 *

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182#define DENDE 0x0010 /* b4: Dend enable */
183#define OBUS 0x0004 /* b2: OUTbus mode */
184
185/* CFIFO/DxFIFO Port Select Register */
186#define RCNT 0x8000 /* b15: Read count mode */
187#define REW 0x4000 /* b14: Buffer rewind */
188#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
189#define DREQE 0x1000 /* b12: DREQ output enable */
190#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
191#define MBW 0x0800
192#else
190#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
193#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
194#endif
191#define MBW_8 0x0000 /* 8bit */
192#define MBW_16 0x0400 /* 16bit */
193#define BIGEND 0x0100 /* b8: Big endian mode */
194#define BYTE_LITTLE 0x0000 /* little dendian */
195#define BYTE_BIG 0x0100 /* big endifan */
196#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
197#define CURPIPE 0x000F /* b2-0: PIPE select */
198

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390#define UPPHUB 0x7800
391#define HUBPORT 0x0700
392#define USBSPD 0x00C0
393#define RTPORT 0x0001
394
395#define R8A66597_MAX_NUM_PIPE 10
396#define R8A66597_BUF_BSIZE 8
397#define R8A66597_MAX_DEVICE 10
195#define MBW_8 0x0000 /* 8bit */
196#define MBW_16 0x0400 /* 16bit */
197#define BIGEND 0x0100 /* b8: Big endian mode */
198#define BYTE_LITTLE 0x0000 /* little dendian */
199#define BYTE_BIG 0x0100 /* big endifan */
200#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
201#define CURPIPE 0x000F /* b2-0: PIPE select */
202

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394#define UPPHUB 0x7800
395#define HUBPORT 0x0700
396#define USBSPD 0x00C0
397#define RTPORT 0x0001
398
399#define R8A66597_MAX_NUM_PIPE 10
400#define R8A66597_BUF_BSIZE 8
401#define R8A66597_MAX_DEVICE 10
402#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
403#define R8A66597_MAX_ROOT_HUB 1
404#else
398#define R8A66597_MAX_ROOT_HUB 2
405#define R8A66597_MAX_ROOT_HUB 2
406#endif
399#define R8A66597_MAX_SAMPLING 5
400#define R8A66597_RH_POLL_TIME 10
401#define R8A66597_MAX_DMA_CHANNEL 2
402#define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
403#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
404#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
405#define make_devsel(addr) (addr << 12)
406

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525{
526 return inw(r8a66597->reg + offset);
527}
528
529static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
530 unsigned long offset, u16 *buf,
531 int len)
532{
407#define R8A66597_MAX_SAMPLING 5
408#define R8A66597_RH_POLL_TIME 10
409#define R8A66597_MAX_DMA_CHANNEL 2
410#define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
411#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
412#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
413#define make_devsel(addr) (addr << 12)
414

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533{
534 return inw(r8a66597->reg + offset);
535}
536
537static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
538 unsigned long offset, u16 *buf,
539 int len)
540{
541#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
542 unsigned long fifoaddr = r8a66597->reg + offset;
543 unsigned long count;
544
545 count = len / 4;
546 insl(fifoaddr, buf, count);
547
548 if (len & 0x00000003) {
549 unsigned long tmp = inl(fifoaddr);
550 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
551 }
552#else
533 len = (len + 1) / 2;
534 insw(r8a66597->reg + offset, buf, len);
553 len = (len + 1) / 2;
554 insw(r8a66597->reg + offset, buf, len);
555#endif
535}
536
537static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
538 unsigned long offset)
539{
540 outw(val, r8a66597->reg + offset);
541}
542
543static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
544 unsigned long offset, u16 *buf,
545 int len)
546{
547 unsigned long fifoaddr = r8a66597->reg + offset;
556}
557
558static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
559 unsigned long offset)
560{
561 outw(val, r8a66597->reg + offset);
562}
563
564static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
565 unsigned long offset, u16 *buf,
566 int len)
567{
568 unsigned long fifoaddr = r8a66597->reg + offset;
569#if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
570 unsigned long count;
571 unsigned char *pb;
572 int i;
573
574 count = len / 4;
575 outsl(fifoaddr, buf, count);
576
577 if (len & 0x00000003) {
578 pb = (unsigned char *)buf + count * 4;
579 for (i = 0; i < (len & 0x00000003); i++) {
580 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
581 outb(pb[i], fifoaddr + i);
582 else
583 outb(pb[i], fifoaddr + 3 - i);
584 }
585 }
586#else
548 int odd = len & 0x0001;
549
550 len = len / 2;
551 outsw(fifoaddr, buf, len);
552 if (unlikely(odd)) {
553 buf = &buf[len];
554 outb((unsigned char)*buf, fifoaddr);
555 }
587 int odd = len & 0x0001;
588
589 len = len / 2;
590 outsw(fifoaddr, buf, len);
591 if (unlikely(odd)) {
592 buf = &buf[len];
593 outb((unsigned char)*buf, fifoaddr);
594 }
595#endif
556}
557
558static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
559 u16 val, u16 pat, unsigned long offset)
560{
561 u16 tmp;
562 tmp = r8a66597_read(r8a66597, offset);
563 tmp = tmp & (~pat);

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580 return port == 0 ? SYSSTS0 : SYSSTS1;
581}
582
583static inline unsigned long get_dvstctr_reg(int port)
584{
585 return port == 0 ? DVSTCTR0 : DVSTCTR1;
586}
587
596}
597
598static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
599 u16 val, u16 pat, unsigned long offset)
600{
601 u16 tmp;
602 tmp = r8a66597_read(r8a66597, offset);
603 tmp = tmp & (~pat);

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620 return port == 0 ? SYSSTS0 : SYSSTS1;
621}
622
623static inline unsigned long get_dvstctr_reg(int port)
624{
625 return port == 0 ? DVSTCTR0 : DVSTCTR1;
626}
627
628static inline unsigned long get_dmacfg_reg(int port)
629{
630 return port == 0 ? DMA0CFG : DMA1CFG;
631}
632
588static inline unsigned long get_intenb_reg(int port)
589{
590 return port == 0 ? INTENB1 : INTENB2;
591}
592
593static inline unsigned long get_intsts_reg(int port)
594{
595 return port == 0 ? INTSTS1 : INTSTS2;

--- 40 unchanged lines hidden --- 		633static inline unsigned long get_intenb_reg(int port)
634{
635 return port == 0 ? INTENB1 : INTENB2;
636}
637
638static inline unsigned long get_intsts_reg(int port)
639{
640 return port == 0 ? INTSTS1 : INTSTS2;

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