ehci-sched.c (196705c9bbc03540429b0f7cf9ee35c2f928a534) ehci-sched.c (6dbd682b7c6d58916096616cdf94852641bc09d9)
1/*
2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.

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39/*-------------------------------------------------------------------------*/
40
41/*
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
45 */
46static union ehci_shadow *
1/*
2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.

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39/*-------------------------------------------------------------------------*/
40
41/*
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
45 */
46static union ehci_shadow *
47periodic_next_shadow (union ehci_shadow *periodic, __le32 tag)
47periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
48 __hc32 tag)
48{
49{
49 switch (tag) {
50 switch (hc32_to_cpu(ehci, tag)) {
50 case Q_TYPE_QH:
51 return &periodic->qh->qh_next;
52 case Q_TYPE_FSTN:
53 return &periodic->fstn->fstn_next;
54 case Q_TYPE_ITD:
55 return &periodic->itd->itd_next;
56 // case Q_TYPE_SITD:
57 default:
58 return &periodic->sitd->sitd_next;
59 }
60}
61
62/* caller must hold ehci->lock */
63static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
64{
51 case Q_TYPE_QH:
52 return &periodic->qh->qh_next;
53 case Q_TYPE_FSTN:
54 return &periodic->fstn->fstn_next;
55 case Q_TYPE_ITD:
56 return &periodic->itd->itd_next;
57 // case Q_TYPE_SITD:
58 default:
59 return &periodic->sitd->sitd_next;
60 }
61}
62
63/* caller must hold ehci->lock */
64static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
65{
65 union ehci_shadow *prev_p = &ehci->pshadow [frame];
66 __le32 *hw_p = &ehci->periodic [frame];
66 union ehci_shadow *prev_p = &ehci->pshadow[frame];
67 __hc32 *hw_p = &ehci->periodic[frame];
67 union ehci_shadow here = *prev_p;
68
69 /* find predecessor of "ptr"; hw and shadow lists are in sync */
70 while (here.ptr && here.ptr != ptr) {
68 union ehci_shadow here = *prev_p;
69
70 /* find predecessor of "ptr"; hw and shadow lists are in sync */
71 while (here.ptr && here.ptr != ptr) {
71 prev_p = periodic_next_shadow (prev_p, Q_NEXT_TYPE (*hw_p));
72 prev_p = periodic_next_shadow(ehci, prev_p,
73 Q_NEXT_TYPE(ehci, *hw_p));
72 hw_p = here.hw_next;
73 here = *prev_p;
74 }
75 /* an interrupt entry (at list end) could have been shared */
76 if (!here.ptr)
77 return;
78
79 /* update shadow and hardware lists ... the old "next" pointers
80 * from ptr may still be in use, the caller updates them.
81 */
74 hw_p = here.hw_next;
75 here = *prev_p;
76 }
77 /* an interrupt entry (at list end) could have been shared */
78 if (!here.ptr)
79 return;
80
81 /* update shadow and hardware lists ... the old "next" pointers
82 * from ptr may still be in use, the caller updates them.
83 */
82 *prev_p = *periodic_next_shadow (&here, Q_NEXT_TYPE (*hw_p));
84 *prev_p = *periodic_next_shadow(ehci, &here,
85 Q_NEXT_TYPE(ehci, *hw_p));
83 *hw_p = *here.hw_next;
84}
85
86/* how many of the uframe's 125 usecs are allocated? */
87static unsigned short
88periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
89{
86 *hw_p = *here.hw_next;
87}
88
89/* how many of the uframe's 125 usecs are allocated? */
90static unsigned short
91periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
92{
90 __le32 *hw_p = &ehci->periodic [frame];
93 __hc32 *hw_p = &ehci->periodic [frame];
91 union ehci_shadow *q = &ehci->pshadow [frame];
92 unsigned usecs = 0;
93
94 while (q->ptr) {
94 union ehci_shadow *q = &ehci->pshadow [frame];
95 unsigned usecs = 0;
96
97 while (q->ptr) {
95 switch (Q_NEXT_TYPE (*hw_p)) {
98 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
96 case Q_TYPE_QH:
97 /* is it in the S-mask? */
99 case Q_TYPE_QH:
100 /* is it in the S-mask? */
98 if (q->qh->hw_info2 & cpu_to_le32 (1 << uframe))
101 if (q->qh->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
99 usecs += q->qh->usecs;
100 /* ... or C-mask? */
102 usecs += q->qh->usecs;
103 /* ... or C-mask? */
101 if (q->qh->hw_info2 & cpu_to_le32 (1 << (8 + uframe)))
104 if (q->qh->hw_info2 & cpu_to_hc32(ehci,
105 1 << (8 + uframe)))
102 usecs += q->qh->c_usecs;
103 hw_p = &q->qh->hw_next;
104 q = &q->qh->qh_next;
105 break;
106 // case Q_TYPE_FSTN:
107 default:
108 /* for "save place" FSTNs, count the relevant INTR
109 * bandwidth from the previous frame
110 */
106 usecs += q->qh->c_usecs;
107 hw_p = &q->qh->hw_next;
108 q = &q->qh->qh_next;
109 break;
110 // case Q_TYPE_FSTN:
111 default:
112 /* for "save place" FSTNs, count the relevant INTR
113 * bandwidth from the previous frame
114 */
111 if (q->fstn->hw_prev != EHCI_LIST_END) {
115 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
112 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
113 }
114 hw_p = &q->fstn->hw_next;
115 q = &q->fstn->fstn_next;
116 break;
117 case Q_TYPE_ITD:
118 usecs += q->itd->usecs [uframe];
119 hw_p = &q->itd->hw_next;
120 q = &q->itd->itd_next;
121 break;
122 case Q_TYPE_SITD:
123 /* is it in the S-mask? (count SPLIT, DATA) */
116 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
117 }
118 hw_p = &q->fstn->hw_next;
119 q = &q->fstn->fstn_next;
120 break;
121 case Q_TYPE_ITD:
122 usecs += q->itd->usecs [uframe];
123 hw_p = &q->itd->hw_next;
124 q = &q->itd->itd_next;
125 break;
126 case Q_TYPE_SITD:
127 /* is it in the S-mask? (count SPLIT, DATA) */
124 if (q->sitd->hw_uframe & cpu_to_le32 (1 << uframe)) {
128 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
129 1 << uframe)) {
125 if (q->sitd->hw_fullspeed_ep &
130 if (q->sitd->hw_fullspeed_ep &
126 __constant_cpu_to_le32 (1<<31))
131 cpu_to_hc32(ehci, 1<<31))
127 usecs += q->sitd->stream->usecs;
128 else /* worst case for OUT start-split */
129 usecs += HS_USECS_ISO (188);
130 }
131
132 /* ... C-mask? (count CSPLIT, DATA) */
133 if (q->sitd->hw_uframe &
132 usecs += q->sitd->stream->usecs;
133 else /* worst case for OUT start-split */
134 usecs += HS_USECS_ISO (188);
135 }
136
137 /* ... C-mask? (count CSPLIT, DATA) */
138 if (q->sitd->hw_uframe &
134 cpu_to_le32 (1 << (8 + uframe))) {
139 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
135 /* worst case for IN complete-split */
136 usecs += q->sitd->stream->c_usecs;
137 }
138
139 hw_p = &q->sitd->hw_next;
140 q = &q->sitd->sitd_next;
141 break;
142 }

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168/* Which uframe does the low/fullspeed transfer start in?
169 *
170 * The parameter is the mask of ssplits in "H-frame" terms
171 * and this returns the transfer start uframe in "B-frame" terms,
172 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
173 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
174 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
175 */
140 /* worst case for IN complete-split */
141 usecs += q->sitd->stream->c_usecs;
142 }
143
144 hw_p = &q->sitd->hw_next;
145 q = &q->sitd->sitd_next;
146 break;
147 }

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173/* Which uframe does the low/fullspeed transfer start in?
174 *
175 * The parameter is the mask of ssplits in "H-frame" terms
176 * and this returns the transfer start uframe in "B-frame" terms,
177 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
178 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
179 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
180 */
176static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __le32 mask)
181static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
177{
182{
178 unsigned char smask = QH_SMASK & le32_to_cpu(mask);
183 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
179 if (!smask) {
180 ehci_err(ehci, "invalid empty smask!\n");
181 /* uframe 7 can't have bw so this will indicate failure */
182 return 7;
183 }
184 return ffs(smask) - 1;
185}
186

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212static void
213periodic_tt_usecs (
214 struct ehci_hcd *ehci,
215 struct usb_device *dev,
216 unsigned frame,
217 unsigned short tt_usecs[8]
218)
219{
184 if (!smask) {
185 ehci_err(ehci, "invalid empty smask!\n");
186 /* uframe 7 can't have bw so this will indicate failure */
187 return 7;
188 }
189 return ffs(smask) - 1;
190}
191

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217static void
218periodic_tt_usecs (
219 struct ehci_hcd *ehci,
220 struct usb_device *dev,
221 unsigned frame,
222 unsigned short tt_usecs[8]
223)
224{
220 __le32 *hw_p = &ehci->periodic [frame];
225 __hc32 *hw_p = &ehci->periodic [frame];
221 union ehci_shadow *q = &ehci->pshadow [frame];
222 unsigned char uf;
223
224 memset(tt_usecs, 0, 16);
225
226 while (q->ptr) {
226 union ehci_shadow *q = &ehci->pshadow [frame];
227 unsigned char uf;
228
229 memset(tt_usecs, 0, 16);
230
231 while (q->ptr) {
227 switch (Q_NEXT_TYPE(*hw_p)) {
232 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
228 case Q_TYPE_ITD:
229 hw_p = &q->itd->hw_next;
230 q = &q->itd->itd_next;
231 continue;
232 case Q_TYPE_QH:
233 if (same_tt(dev, q->qh->dev)) {
234 uf = tt_start_uframe(ehci, q->qh->hw_info2);
235 tt_usecs[uf] += q->qh->tt_usecs;

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242 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
243 tt_usecs[uf] += q->sitd->stream->tt_usecs;
244 }
245 hw_p = &q->sitd->hw_next;
246 q = &q->sitd->sitd_next;
247 continue;
248 // case Q_TYPE_FSTN:
249 default:
233 case Q_TYPE_ITD:
234 hw_p = &q->itd->hw_next;
235 q = &q->itd->itd_next;
236 continue;
237 case Q_TYPE_QH:
238 if (same_tt(dev, q->qh->dev)) {
239 uf = tt_start_uframe(ehci, q->qh->hw_info2);
240 tt_usecs[uf] += q->qh->tt_usecs;

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247 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
248 tt_usecs[uf] += q->sitd->stream->tt_usecs;
249 }
250 hw_p = &q->sitd->hw_next;
251 q = &q->sitd->sitd_next;
252 continue;
253 // case Q_TYPE_FSTN:
254 default:
250 ehci_dbg(ehci,
251 "ignoring periodic frame %d FSTN\n", frame);
255 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
256 frame);
252 hw_p = &q->fstn->hw_next;
253 q = &q->fstn->fstn_next;
254 }
255 }
256
257 carryover_tt_bandwidth(tt_usecs);
258
259 if (max_tt_usecs[7] < tt_usecs[7])

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363 return 0;
364
365 /* note bandwidth wastage: split never follows csplit
366 * (different dev or endpoint) until the next uframe.
367 * calling convention doesn't make that distinction.
368 */
369 for (; frame < ehci->periodic_size; frame += period) {
370 union ehci_shadow here;
257 hw_p = &q->fstn->hw_next;
258 q = &q->fstn->fstn_next;
259 }
260 }
261
262 carryover_tt_bandwidth(tt_usecs);
263
264 if (max_tt_usecs[7] < tt_usecs[7])

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368 return 0;
369
370 /* note bandwidth wastage: split never follows csplit
371 * (different dev or endpoint) until the next uframe.
372 * calling convention doesn't make that distinction.
373 */
374 for (; frame < ehci->periodic_size; frame += period) {
375 union ehci_shadow here;
371 __le32 type;
376 __hc32 type;
372
373 here = ehci->pshadow [frame];
377
378 here = ehci->pshadow [frame];
374 type = Q_NEXT_TYPE (ehci->periodic [frame]);
379 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
375 while (here.ptr) {
380 while (here.ptr) {
376 switch (type) {
381 switch (hc32_to_cpu(ehci, type)) {
377 case Q_TYPE_ITD:
382 case Q_TYPE_ITD:
378 type = Q_NEXT_TYPE (here.itd->hw_next);
383 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
379 here = here.itd->itd_next;
380 continue;
381 case Q_TYPE_QH:
382 if (same_tt (dev, here.qh->dev)) {
383 u32 mask;
384
384 here = here.itd->itd_next;
385 continue;
386 case Q_TYPE_QH:
387 if (same_tt (dev, here.qh->dev)) {
388 u32 mask;
389
385 mask = le32_to_cpu (here.qh->hw_info2);
390 mask = hc32_to_cpu(ehci,
391 here.qh->hw_info2);
386 /* "knows" no gap is needed */
387 mask |= mask >> 8;
388 if (mask & uf_mask)
389 break;
390 }
392 /* "knows" no gap is needed */
393 mask |= mask >> 8;
394 if (mask & uf_mask)
395 break;
396 }
391 type = Q_NEXT_TYPE (here.qh->hw_next);
397 type = Q_NEXT_TYPE(ehci, here.qh->hw_next);
392 here = here.qh->qh_next;
393 continue;
394 case Q_TYPE_SITD:
395 if (same_tt (dev, here.sitd->urb->dev)) {
396 u16 mask;
397
398 here = here.qh->qh_next;
399 continue;
400 case Q_TYPE_SITD:
401 if (same_tt (dev, here.sitd->urb->dev)) {
402 u16 mask;
403
398 mask = le32_to_cpu (here.sitd
404 mask = hc32_to_cpu(ehci, here.sitd
399 ->hw_uframe);
400 /* FIXME assumes no gap for IN! */
401 mask |= mask >> 8;
402 if (mask & uf_mask)
403 break;
404 }
405 ->hw_uframe);
406 /* FIXME assumes no gap for IN! */
407 mask |= mask >> 8;
408 if (mask & uf_mask)
409 break;
410 }
405 type = Q_NEXT_TYPE (here.sitd->hw_next);
411 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
406 here = here.sitd->sitd_next;
407 continue;
408 // case Q_TYPE_FSTN:
409 default:
410 ehci_dbg (ehci,
411 "periodic frame %d bogus type %d\n",
412 frame, type);
413 }

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470
471 ehci->next_uframe = -1;
472 return 0;
473}
474
475/*-------------------------------------------------------------------------*/
476#ifdef CONFIG_CPU_FREQ
477
412 here = here.sitd->sitd_next;
413 continue;
414 // case Q_TYPE_FSTN:
415 default:
416 ehci_dbg (ehci,
417 "periodic frame %d bogus type %d\n",
418 frame, type);
419 }

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476
477 ehci->next_uframe = -1;
478 return 0;
479}
480
481/*-------------------------------------------------------------------------*/
482#ifdef CONFIG_CPU_FREQ
483
478/* ignore/inactivate bit in QH hw_info1 */
479#define INACTIVATE_BIT __constant_cpu_to_le32(QH_INACTIVATE)
480
481#define HALT_BIT __constant_cpu_to_le32(QTD_STS_HALT)
482#define ACTIVE_BIT __constant_cpu_to_le32(QTD_STS_ACTIVE)
483#define STATUS_BIT __constant_cpu_to_le32(QTD_STS_STS)
484
485static int safe_to_modify_i (struct ehci_hcd *ehci, struct ehci_qh *qh)
486{
487 int now; /* current (frame * 8) + uframe */
488 int prev_start, next_start; /* uframes from/to split start */
489 int start_uframe = ffs(le32_to_cpup (&qh->hw_info2) & QH_SMASK);
490 int end_uframe = fls((le32_to_cpup (&qh->hw_info2) & QH_CMASK) >> 8);
491 int split_duration = end_uframe - start_uframe;
492
493 now = readl(&ehci->regs->frame_index) % (ehci->periodic_size << 3);
494
484static int safe_to_modify_i (struct ehci_hcd *ehci, struct ehci_qh *qh)
485{
486 int now; /* current (frame * 8) + uframe */
487 int prev_start, next_start; /* uframes from/to split start */
488 int start_uframe = ffs(le32_to_cpup (&qh->hw_info2) & QH_SMASK);
489 int end_uframe = fls((le32_to_cpup (&qh->hw_info2) & QH_CMASK) >> 8);
490 int split_duration = end_uframe - start_uframe;
491
492 now = readl(&ehci->regs->frame_index) % (ehci->periodic_size << 3);
493
495 next_start = ((1024 << 3) + (qh->start << 3) + start_uframe - now) %
496 (qh->period << 3);
494 next_start = ((1024 << 3) + (qh->start << 3) + start_uframe - now)
495 % (qh->period << 3);
497 prev_start = (qh->period << 3) - next_start;
498
499 /*
500 * Make sure there will be at least one uframe when qh is safe.
501 */
502 if ((qh->period << 3) <= (ehci->i_thresh + 2 + split_duration))
503 /* never safe */
504 return -EINVAL;
505
506 /*
507 * Wait 1 uframe after transaction should have started, to make
508 * sure controller has time to write back overlay, so we can
509 * check QTD_STS_STS to see if transaction is in progress.
510 */
511 if ((next_start > ehci->i_thresh) && (prev_start > 1))
512 /* safe to set "i" bit if split isn't in progress */
496 prev_start = (qh->period << 3) - next_start;
497
498 /*
499 * Make sure there will be at least one uframe when qh is safe.
500 */
501 if ((qh->period << 3) <= (ehci->i_thresh + 2 + split_duration))
502 /* never safe */
503 return -EINVAL;
504
505 /*
506 * Wait 1 uframe after transaction should have started, to make
507 * sure controller has time to write back overlay, so we can
508 * check QTD_STS_STS to see if transaction is in progress.
509 */
510 if ((next_start > ehci->i_thresh) && (prev_start > 1))
511 /* safe to set "i" bit if split isn't in progress */
513 return (qh->hw_token & STATUS_BIT) ? 0 : 1;
512 return (qh->hw_token & STATUS_BIT(ehci)) ? 0 : 1;
514 else
515 return 0;
516}
517
518/* Set inactivate bit for all the split interrupt QHs. */
519static void qh_inactivate_split_intr_qhs (struct ehci_hcd *ehci)
520{
521 struct ehci_qh *qh;
522 int not_done, safe;
513 else
514 return 0;
515}
516
517/* Set inactivate bit for all the split interrupt QHs. */
518static void qh_inactivate_split_intr_qhs (struct ehci_hcd *ehci)
519{
520 struct ehci_qh *qh;
521 int not_done, safe;
522 u32 inactivate = INACTIVATE_BIT(ehci);
523 u32 active = ACTIVE_BIT(ehci);
523
524 do {
525 not_done = 0;
526 list_for_each_entry(qh, &ehci->split_intr_qhs,
524
525 do {
526 not_done = 0;
527 list_for_each_entry(qh, &ehci->split_intr_qhs,
527 split_intr_qhs) {
528 if (qh->hw_info1 & INACTIVATE_BIT)
528 split_intr_qhs) {
529 if (qh->hw_info1 & inactivate)
529 /* already off */
530 continue;
531 /*
532 * To avoid setting "I" after the start split happens,
533 * don't set it if the QH might be cached in the
534 * controller. Some HCs (Broadcom/ServerWorks HT1000)
535 * will stop in the middle of a split transaction when
536 * the "I" bit is set.
537 */
538 safe = safe_to_modify_i(ehci, qh);
539 if (safe == 0) {
540 not_done = 1;
541 } else if (safe > 0) {
530 /* already off */
531 continue;
532 /*
533 * To avoid setting "I" after the start split happens,
534 * don't set it if the QH might be cached in the
535 * controller. Some HCs (Broadcom/ServerWorks HT1000)
536 * will stop in the middle of a split transaction when
537 * the "I" bit is set.
538 */
539 safe = safe_to_modify_i(ehci, qh);
540 if (safe == 0) {
541 not_done = 1;
542 } else if (safe > 0) {
542 qh->was_active = qh->hw_token & ACTIVE_BIT;
543 qh->hw_info1 |= INACTIVATE_BIT;
543 qh->was_active = qh->hw_token & active;
544 qh->hw_info1 |= inactivate;
544 }
545 }
546 } while (not_done);
547 wmb();
548}
549
550static void qh_reactivate_split_intr_qhs (struct ehci_hcd *ehci)
551{
552 struct ehci_qh *qh;
553 u32 token;
554 int not_done, safe;
545 }
546 }
547 } while (not_done);
548 wmb();
549}
550
551static void qh_reactivate_split_intr_qhs (struct ehci_hcd *ehci)
552{
553 struct ehci_qh *qh;
554 u32 token;
555 int not_done, safe;
556 u32 inactivate = INACTIVATE_BIT(ehci);
557 u32 active = ACTIVE_BIT(ehci);
558 u32 halt = HALT_BIT(ehci);
555
556 do {
557 not_done = 0;
558 list_for_each_entry(qh, &ehci->split_intr_qhs, split_intr_qhs) {
559
560 do {
561 not_done = 0;
562 list_for_each_entry(qh, &ehci->split_intr_qhs, split_intr_qhs) {
559 if (!(qh->hw_info1 & INACTIVATE_BIT)) /* already on */
563 if (!(qh->hw_info1 & inactivate)) /* already on */
560 continue;
561 /*
562 * Don't reactivate if cached, or controller might
563 * overwrite overlay after we modify it!
564 */
565 safe = safe_to_modify_i(ehci, qh);
566 if (safe == 0) {
567 not_done = 1;
568 } else if (safe > 0) {
569 /* See EHCI 1.0 section 4.15.2.4. */
570 token = qh->hw_token;
564 continue;
565 /*
566 * Don't reactivate if cached, or controller might
567 * overwrite overlay after we modify it!
568 */
569 safe = safe_to_modify_i(ehci, qh);
570 if (safe == 0) {
571 not_done = 1;
572 } else if (safe > 0) {
573 /* See EHCI 1.0 section 4.15.2.4. */
574 token = qh->hw_token;
571 qh->hw_token = (token | HALT_BIT) & ~ACTIVE_BIT;
575 qh->hw_token = (token | halt) & ~active;
572 wmb();
576 wmb();
573 qh->hw_info1 &= ~INACTIVATE_BIT;
577 qh->hw_info1 &= ~inactivate;
574 wmb();
578 wmb();
575 qh->hw_token = (token & ~HALT_BIT) | qh->was_active;
579 qh->hw_token = (token & ~halt) | qh->was_active;
576 }
577 }
578 } while (not_done);
579}
580#endif
581
582/* periodic schedule slots have iso tds (normal or split) first, then a
583 * sparse tree for active interrupt transfers.
584 *
585 * this just links in a qh; caller guarantees uframe masks are set right.
586 * no FSTN support (yet; ehci 0.96+)
587 */
588static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
589{
590 unsigned i;
591 unsigned period = qh->period;
592
593 dev_dbg (&qh->dev->dev,
594 "link qh%d-%04x/%p start %d [%d/%d us]\n",
580 }
581 }
582 } while (not_done);
583}
584#endif
585
586/* periodic schedule slots have iso tds (normal or split) first, then a
587 * sparse tree for active interrupt transfers.
588 *
589 * this just links in a qh; caller guarantees uframe masks are set right.
590 * no FSTN support (yet; ehci 0.96+)
591 */
592static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
593{
594 unsigned i;
595 unsigned period = qh->period;
596
597 dev_dbg (&qh->dev->dev,
598 "link qh%d-%04x/%p start %d [%d/%d us]\n",
595 period, le32_to_cpup (&qh->hw_info2) & (QH_CMASK | QH_SMASK),
599 period, hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
596 qh, qh->start, qh->usecs, qh->c_usecs);
597
598#ifdef CONFIG_CPU_FREQ
599 /*
600 * If low/full speed interrupt QHs are inactive (because of
601 * cpufreq changing processor speeds), start QH with I flag set--
602 * it will automatically be cleared when cpufreq is done.
603 */
604 if (ehci->cpufreq_changing)
605 if (!(qh->hw_info1 & (cpu_to_le32(1 << 13))))
600 qh, qh->start, qh->usecs, qh->c_usecs);
601
602#ifdef CONFIG_CPU_FREQ
603 /*
604 * If low/full speed interrupt QHs are inactive (because of
605 * cpufreq changing processor speeds), start QH with I flag set--
606 * it will automatically be cleared when cpufreq is done.
607 */
608 if (ehci->cpufreq_changing)
609 if (!(qh->hw_info1 & (cpu_to_le32(1 << 13))))
606 qh->hw_info1 |= INACTIVATE_BIT;
610 qh->hw_info1 |= INACTIVATE_BIT(ehci);
607#endif
608
609 /* high bandwidth, or otherwise every microframe */
610 if (period == 0)
611 period = 1;
612
613 for (i = qh->start; i < ehci->periodic_size; i += period) {
611#endif
612
613 /* high bandwidth, or otherwise every microframe */
614 if (period == 0)
615 period = 1;
616
617 for (i = qh->start; i < ehci->periodic_size; i += period) {
614 union ehci_shadow *prev = &ehci->pshadow [i];
615 __le32 *hw_p = &ehci->periodic [i];
618 union ehci_shadow *prev = &ehci->pshadow[i];
619 __hc32 *hw_p = &ehci->periodic[i];
616 union ehci_shadow here = *prev;
620 union ehci_shadow here = *prev;
617 __le32 type = 0;
621 __hc32 type = 0;
618
619 /* skip the iso nodes at list head */
620 while (here.ptr) {
622
623 /* skip the iso nodes at list head */
624 while (here.ptr) {
621 type = Q_NEXT_TYPE (*hw_p);
622 if (type == Q_TYPE_QH)
625 type = Q_NEXT_TYPE(ehci, *hw_p);
626 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
623 break;
627 break;
624 prev = periodic_next_shadow (prev, type);
628 prev = periodic_next_shadow(ehci, prev, type);
625 hw_p = &here.qh->hw_next;
626 here = *prev;
627 }
628
629 /* sorting each branch by period (slow-->fast)
630 * enables sharing interior tree nodes
631 */
632 while (here.ptr && qh != here.qh) {

--- 5 unchanged lines hidden (view full) ---

638 }
639 /* link in this qh, unless some earlier pass did that */
640 if (qh != here.qh) {
641 qh->qh_next = here;
642 if (here.qh)
643 qh->hw_next = *hw_p;
644 wmb ();
645 prev->qh = qh;
629 hw_p = &here.qh->hw_next;
630 here = *prev;
631 }
632
633 /* sorting each branch by period (slow-->fast)
634 * enables sharing interior tree nodes
635 */
636 while (here.ptr && qh != here.qh) {

--- 5 unchanged lines hidden (view full) ---

642 }
643 /* link in this qh, unless some earlier pass did that */
644 if (qh != here.qh) {
645 qh->qh_next = here;
646 if (here.qh)
647 qh->hw_next = *hw_p;
648 wmb ();
649 prev->qh = qh;
646 *hw_p = QH_NEXT (qh->qh_dma);
650 *hw_p = QH_NEXT (ehci, qh->qh_dma);
647 }
648 }
649 qh->qh_state = QH_STATE_LINKED;
650 qh_get (qh);
651
652 /* update per-qh bandwidth for usbfs */
653 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
654 ? ((qh->usecs + qh->c_usecs) / qh->period)

--- 17 unchanged lines hidden (view full) ---

672 unsigned i;
673 unsigned period;
674
675 // FIXME:
676 // IF this isn't high speed
677 // and this qh is active in the current uframe
678 // (and overlay token SplitXstate is false?)
679 // THEN
651 }
652 }
653 qh->qh_state = QH_STATE_LINKED;
654 qh_get (qh);
655
656 /* update per-qh bandwidth for usbfs */
657 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
658 ? ((qh->usecs + qh->c_usecs) / qh->period)

--- 17 unchanged lines hidden (view full) ---

676 unsigned i;
677 unsigned period;
678
679 // FIXME:
680 // IF this isn't high speed
681 // and this qh is active in the current uframe
682 // (and overlay token SplitXstate is false?)
683 // THEN
680 // qh->hw_info1 |= __constant_cpu_to_le32 (1 << 7 /* "ignore" */);
684 // qh->hw_info1 |= __constant_cpu_to_hc32(1 << 7 /* "ignore" */);
681
682#ifdef CONFIG_CPU_FREQ
683 /* remove qh from list of low/full speed interrupt QHs */
684 if (!(qh->hw_info1 & (cpu_to_le32(1 << 13)))) {
685 list_del_init(&qh->split_intr_qhs);
686 }
687#endif
688

--- 7 unchanged lines hidden (view full) ---

696 /* update per-qh bandwidth for usbfs */
697 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
698 ? ((qh->usecs + qh->c_usecs) / qh->period)
699 : (qh->usecs * 8);
700
701 dev_dbg (&qh->dev->dev,
702 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
703 qh->period,
685
686#ifdef CONFIG_CPU_FREQ
687 /* remove qh from list of low/full speed interrupt QHs */
688 if (!(qh->hw_info1 & (cpu_to_le32(1 << 13)))) {
689 list_del_init(&qh->split_intr_qhs);
690 }
691#endif
692

--- 7 unchanged lines hidden (view full) ---

700 /* update per-qh bandwidth for usbfs */
701 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
702 ? ((qh->usecs + qh->c_usecs) / qh->period)
703 : (qh->usecs * 8);
704
705 dev_dbg (&qh->dev->dev,
706 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
707 qh->period,
704 le32_to_cpup (&qh->hw_info2) & (QH_CMASK | QH_SMASK),
708 hc32_to_cpup(ehci, &qh->hw_info2) & (QH_CMASK | QH_SMASK),
705 qh, qh->start, qh->usecs, qh->c_usecs);
706
707 /* qh->qh_next still "live" to HC */
708 qh->qh_state = QH_STATE_UNLINK;
709 qh->qh_next.ptr = NULL;
710 qh_put (qh);
711
712 /* maybe turn off periodic schedule */

--- 9 unchanged lines hidden (view full) ---

722 qh_unlink_periodic (ehci, qh);
723
724 /* simple/paranoid: always delay, expecting the HC needs to read
725 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
726 * expect khubd to clean up after any CSPLITs we won't issue.
727 * active high speed queues may need bigger delays...
728 */
729 if (list_empty (&qh->qtd_list)
709 qh, qh->start, qh->usecs, qh->c_usecs);
710
711 /* qh->qh_next still "live" to HC */
712 qh->qh_state = QH_STATE_UNLINK;
713 qh->qh_next.ptr = NULL;
714 qh_put (qh);
715
716 /* maybe turn off periodic schedule */

--- 9 unchanged lines hidden (view full) ---

726 qh_unlink_periodic (ehci, qh);
727
728 /* simple/paranoid: always delay, expecting the HC needs to read
729 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
730 * expect khubd to clean up after any CSPLITs we won't issue.
731 * active high speed queues may need bigger delays...
732 */
733 if (list_empty (&qh->qtd_list)
730 || (__constant_cpu_to_le32 (QH_CMASK)
734 || (cpu_to_hc32(ehci, QH_CMASK)
731 & qh->hw_info2) != 0)
732 wait = 2;
733 else
734 wait = 55; /* worst case: 3 * 1024 */
735
736 udelay (wait);
737 qh->qh_state = QH_STATE_IDLE;
735 & qh->hw_info2) != 0)
736 wait = 2;
737 else
738 wait = 55; /* worst case: 3 * 1024 */
739
740 udelay (wait);
741 qh->qh_state = QH_STATE_IDLE;
738 qh->hw_next = EHCI_LIST_END;
742 qh->hw_next = EHCI_LIST_END(ehci);
739 wmb ();
740}
741
742/*-------------------------------------------------------------------------*/
743
744static int check_period (
745 struct ehci_hcd *ehci,
746 unsigned frame,

--- 40 unchanged lines hidden (view full) ---

787 return 1;
788}
789
790static int check_intr_schedule (
791 struct ehci_hcd *ehci,
792 unsigned frame,
793 unsigned uframe,
794 const struct ehci_qh *qh,
743 wmb ();
744}
745
746/*-------------------------------------------------------------------------*/
747
748static int check_period (
749 struct ehci_hcd *ehci,
750 unsigned frame,

--- 40 unchanged lines hidden (view full) ---

791 return 1;
792}
793
794static int check_intr_schedule (
795 struct ehci_hcd *ehci,
796 unsigned frame,
797 unsigned uframe,
798 const struct ehci_qh *qh,
795 __le32 *c_maskp
799 __hc32 *c_maskp
796)
797{
798 int retval = -ENOSPC;
799 u8 mask = 0;
800
801 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
802 goto done;
803

--- 15 unchanged lines hidden (view full) ---

819 if (!check_period (ehci, frame, i,
820 qh->period, qh->c_usecs))
821 goto done;
822 else
823 mask |= 1 << i;
824
825 retval = 0;
826
800)
801{
802 int retval = -ENOSPC;
803 u8 mask = 0;
804
805 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
806 goto done;
807

--- 15 unchanged lines hidden (view full) ---

823 if (!check_period (ehci, frame, i,
824 qh->period, qh->c_usecs))
825 goto done;
826 else
827 mask |= 1 << i;
828
829 retval = 0;
830
827 *c_maskp = cpu_to_le32 (mask << 8);
831 *c_maskp = cpu_to_hc32(ehci, mask << 8);
828 }
829#else
830 /* Make sure this tt's buffer is also available for CSPLITs.
831 * We pessimize a bit; probably the typical full speed case
832 * doesn't need the second CSPLIT.
833 *
834 * NOTE: both SPLIT and CSPLIT could be checked in just
835 * one smart pass...
836 */
837 mask = 0x03 << (uframe + qh->gap_uf);
832 }
833#else
834 /* Make sure this tt's buffer is also available for CSPLITs.
835 * We pessimize a bit; probably the typical full speed case
836 * doesn't need the second CSPLIT.
837 *
838 * NOTE: both SPLIT and CSPLIT could be checked in just
839 * one smart pass...
840 */
841 mask = 0x03 << (uframe + qh->gap_uf);
838 *c_maskp = cpu_to_le32 (mask << 8);
842 *c_maskp = cpu_to_hc32(ehci, mask << 8);
839
840 mask |= 1 << uframe;
841 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
842 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
843 qh->period, qh->c_usecs))
844 goto done;
845 if (!check_period (ehci, frame, uframe + qh->gap_uf,
846 qh->period, qh->c_usecs))
847 goto done;
848 retval = 0;
849 }
850#endif
851done:
852 return retval;
853}
854
855/* "first fit" scheduling policy used the first time through,
856 * or when the previous schedule slot can't be re-used.
857 */
843
844 mask |= 1 << uframe;
845 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
846 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
847 qh->period, qh->c_usecs))
848 goto done;
849 if (!check_period (ehci, frame, uframe + qh->gap_uf,
850 qh->period, qh->c_usecs))
851 goto done;
852 retval = 0;
853 }
854#endif
855done:
856 return retval;
857}
858
859/* "first fit" scheduling policy used the first time through,
860 * or when the previous schedule slot can't be re-used.
861 */
858static int qh_schedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
862static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
859{
860 int status;
861 unsigned uframe;
863{
864 int status;
865 unsigned uframe;
862 __le32 c_mask;
866 __hc32 c_mask;
863 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
864
865 qh_refresh(ehci, qh);
867 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
868
869 qh_refresh(ehci, qh);
866 qh->hw_next = EHCI_LIST_END;
870 qh->hw_next = EHCI_LIST_END(ehci);
867 frame = qh->start;
868
869 /* reuse the previous schedule slots, if we can */
870 if (frame < qh->period) {
871 frame = qh->start;
872
873 /* reuse the previous schedule slots, if we can */
874 if (frame < qh->period) {
871 uframe = ffs (le32_to_cpup (&qh->hw_info2) & QH_SMASK);
875 uframe = ffs(hc32_to_cpup(ehci, &qh->hw_info2) & QH_SMASK);
872 status = check_intr_schedule (ehci, frame, --uframe,
873 qh, &c_mask);
874 } else {
875 uframe = 0;
876 c_mask = 0;
877 status = -ENOSPC;
878 }
879

--- 19 unchanged lines hidden (view full) ---

899 frame = 0;
900 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
901 }
902 if (status)
903 goto done;
904 qh->start = frame;
905
906 /* reset S-frame and (maybe) C-frame masks */
876 status = check_intr_schedule (ehci, frame, --uframe,
877 qh, &c_mask);
878 } else {
879 uframe = 0;
880 c_mask = 0;
881 status = -ENOSPC;
882 }
883

--- 19 unchanged lines hidden (view full) ---

903 frame = 0;
904 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
905 }
906 if (status)
907 goto done;
908 qh->start = frame;
909
910 /* reset S-frame and (maybe) C-frame masks */
907 qh->hw_info2 &= __constant_cpu_to_le32(~(QH_CMASK | QH_SMASK));
911 qh->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
908 qh->hw_info2 |= qh->period
912 qh->hw_info2 |= qh->period
909 ? cpu_to_le32 (1 << uframe)
910 : __constant_cpu_to_le32 (QH_SMASK);
913 ? cpu_to_hc32(ehci, 1 << uframe)
914 : cpu_to_hc32(ehci, QH_SMASK);
911 qh->hw_info2 |= c_mask;
912 } else
913 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
914
915 /* stuff into the periodic schedule */
916 status = qh_link_periodic (ehci, qh);
917done:
918 return status;

--- 13 unchanged lines hidden (view full) ---

932 struct list_head empty;
933
934 /* get endpoint and transfer/schedule data */
935 epnum = ep->desc.bEndpointAddress;
936
937 spin_lock_irqsave (&ehci->lock, flags);
938
939 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
915 qh->hw_info2 |= c_mask;
916 } else
917 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
918
919 /* stuff into the periodic schedule */
920 status = qh_link_periodic (ehci, qh);
921done:
922 return status;

--- 13 unchanged lines hidden (view full) ---

936 struct list_head empty;
937
938 /* get endpoint and transfer/schedule data */
939 epnum = ep->desc.bEndpointAddress;
940
941 spin_lock_irqsave (&ehci->lock, flags);
942
943 if (unlikely(!test_bit(HCD_FLAG_HW_ACCESSIBLE,
940 &ehci_to_hcd(ehci)->flags))) {
944 &ehci_to_hcd(ehci)->flags))) {
941 status = -ESHUTDOWN;
942 goto done;
943 }
944
945 /* get qh and force any scheduling errors */
946 INIT_LIST_HEAD (&empty);
947 qh = qh_append_tds (ehci, urb, &empty, epnum, &ep->hcpriv);
948 if (qh == NULL) {

--- 73 unchanged lines hidden (view full) ---

1022 unsigned multi = hb_mult(maxp);
1023
1024 stream->highspeed = 1;
1025
1026 maxp = max_packet(maxp);
1027 buf1 |= maxp;
1028 maxp *= multi;
1029
945 status = -ESHUTDOWN;
946 goto done;
947 }
948
949 /* get qh and force any scheduling errors */
950 INIT_LIST_HEAD (&empty);
951 qh = qh_append_tds (ehci, urb, &empty, epnum, &ep->hcpriv);
952 if (qh == NULL) {

--- 73 unchanged lines hidden (view full) ---

1026 unsigned multi = hb_mult(maxp);
1027
1028 stream->highspeed = 1;
1029
1030 maxp = max_packet(maxp);
1031 buf1 |= maxp;
1032 maxp *= multi;
1033
1030 stream->buf0 = cpu_to_le32 ((epnum << 8) | dev->devnum);
1031 stream->buf1 = cpu_to_le32 (buf1);
1032 stream->buf2 = cpu_to_le32 (multi);
1034 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
1035 stream->buf1 = cpu_to_hc32(ehci, buf1);
1036 stream->buf2 = cpu_to_hc32(ehci, multi);
1033
1034 /* usbfs wants to report the average usecs per frame tied up
1035 * when transfers on this endpoint are scheduled ...
1036 */
1037 stream->usecs = HS_USECS_ISO (maxp);
1038 bandwidth = stream->usecs * 8;
1039 bandwidth /= 1 << (interval - 1);
1040

--- 26 unchanged lines hidden (view full) ---

1067 tmp = (1 << (hs_transfers + 2)) - 1;
1068 stream->raw_mask |= tmp << (8 + 2);
1069 } else
1070 stream->raw_mask = smask_out [hs_transfers - 1];
1071 bandwidth = stream->usecs + stream->c_usecs;
1072 bandwidth /= 1 << (interval + 2);
1073
1074 /* stream->splits gets created from raw_mask later */
1037
1038 /* usbfs wants to report the average usecs per frame tied up
1039 * when transfers on this endpoint are scheduled ...
1040 */
1041 stream->usecs = HS_USECS_ISO (maxp);
1042 bandwidth = stream->usecs * 8;
1043 bandwidth /= 1 << (interval - 1);
1044

--- 26 unchanged lines hidden (view full) ---

1071 tmp = (1 << (hs_transfers + 2)) - 1;
1072 stream->raw_mask |= tmp << (8 + 2);
1073 } else
1074 stream->raw_mask = smask_out [hs_transfers - 1];
1075 bandwidth = stream->usecs + stream->c_usecs;
1076 bandwidth /= 1 << (interval + 2);
1077
1078 /* stream->splits gets created from raw_mask later */
1075 stream->address = cpu_to_le32 (addr);
1079 stream->address = cpu_to_hc32(ehci, addr);
1076 }
1077 stream->bandwidth = bandwidth;
1078
1079 stream->udev = dev;
1080
1081 stream->bEndpointAddress = is_input | epnum;
1082 stream->interval = interval;
1083 stream->maxp = maxp;

--- 117 unchanged lines hidden (view full) ---

1201 iso_sched = kzalloc(size, mem_flags);
1202 if (likely (iso_sched != NULL)) {
1203 INIT_LIST_HEAD (&iso_sched->td_list);
1204 }
1205 return iso_sched;
1206}
1207
1208static inline void
1080 }
1081 stream->bandwidth = bandwidth;
1082
1083 stream->udev = dev;
1084
1085 stream->bEndpointAddress = is_input | epnum;
1086 stream->interval = interval;
1087 stream->maxp = maxp;

--- 117 unchanged lines hidden (view full) ---

1205 iso_sched = kzalloc(size, mem_flags);
1206 if (likely (iso_sched != NULL)) {
1207 INIT_LIST_HEAD (&iso_sched->td_list);
1208 }
1209 return iso_sched;
1210}
1211
1212static inline void
1209itd_sched_init (
1213itd_sched_init(
1214 struct ehci_hcd *ehci,
1210 struct ehci_iso_sched *iso_sched,
1211 struct ehci_iso_stream *stream,
1212 struct urb *urb
1213)
1214{
1215 unsigned i;
1216 dma_addr_t dma = urb->transfer_dma;
1217

--- 13 unchanged lines hidden (view full) ---

1231 buf = dma + urb->iso_frame_desc [i].offset;
1232
1233 trans = EHCI_ISOC_ACTIVE;
1234 trans |= buf & 0x0fff;
1235 if (unlikely (((i + 1) == urb->number_of_packets))
1236 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1237 trans |= EHCI_ITD_IOC;
1238 trans |= length << 16;
1215 struct ehci_iso_sched *iso_sched,
1216 struct ehci_iso_stream *stream,
1217 struct urb *urb
1218)
1219{
1220 unsigned i;
1221 dma_addr_t dma = urb->transfer_dma;
1222

--- 13 unchanged lines hidden (view full) ---

1236 buf = dma + urb->iso_frame_desc [i].offset;
1237
1238 trans = EHCI_ISOC_ACTIVE;
1239 trans |= buf & 0x0fff;
1240 if (unlikely (((i + 1) == urb->number_of_packets))
1241 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1242 trans |= EHCI_ITD_IOC;
1243 trans |= length << 16;
1239 uframe->transaction = cpu_to_le32 (trans);
1244 uframe->transaction = cpu_to_hc32(ehci, trans);
1240
1241 /* might need to cross a buffer page within a uframe */
1242 uframe->bufp = (buf & ~(u64)0x0fff);
1243 buf += length;
1244 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1245 uframe->cross = 1;
1246 }
1247}

--- 25 unchanged lines hidden (view full) ---

1273 unsigned num_itds;
1274 struct ehci_iso_sched *sched;
1275 unsigned long flags;
1276
1277 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1278 if (unlikely (sched == NULL))
1279 return -ENOMEM;
1280
1245
1246 /* might need to cross a buffer page within a uframe */
1247 uframe->bufp = (buf & ~(u64)0x0fff);
1248 buf += length;
1249 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1250 uframe->cross = 1;
1251 }
1252}

--- 25 unchanged lines hidden (view full) ---

1278 unsigned num_itds;
1279 struct ehci_iso_sched *sched;
1280 unsigned long flags;
1281
1282 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1283 if (unlikely (sched == NULL))
1284 return -ENOMEM;
1285
1281 itd_sched_init (sched, stream, urb);
1286 itd_sched_init(ehci, sched, stream, urb);
1282
1283 if (urb->interval < 8)
1284 num_itds = 1 + (sched->span + 7) / 8;
1285 else
1286 num_itds = urb->number_of_packets;
1287
1288 /* allocate/init ITDs */
1289 spin_lock_irqsave (&ehci->lock, flags);
1290 for (i = 0; i < num_itds; i++) {
1291
1292 /* free_list.next might be cache-hot ... but maybe
1293 * the HC caches it too. avoid that issue for now.
1294 */
1295
1296 /* prefer previously-allocated itds */
1297 if (likely (!list_empty(&stream->free_list))) {
1298 itd = list_entry (stream->free_list.prev,
1287
1288 if (urb->interval < 8)
1289 num_itds = 1 + (sched->span + 7) / 8;
1290 else
1291 num_itds = urb->number_of_packets;
1292
1293 /* allocate/init ITDs */
1294 spin_lock_irqsave (&ehci->lock, flags);
1295 for (i = 0; i < num_itds; i++) {
1296
1297 /* free_list.next might be cache-hot ... but maybe
1298 * the HC caches it too. avoid that issue for now.
1299 */
1300
1301 /* prefer previously-allocated itds */
1302 if (likely (!list_empty(&stream->free_list))) {
1303 itd = list_entry (stream->free_list.prev,
1299 struct ehci_itd, itd_list);
1304 struct ehci_itd, itd_list);
1300 list_del (&itd->itd_list);
1301 itd_dma = itd->itd_dma;
1302 } else
1303 itd = NULL;
1304
1305 if (!itd) {
1306 spin_unlock_irqrestore (&ehci->lock, flags);
1307 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,

--- 110 unchanged lines hidden (view full) ---

1418 return 0;
1419 } while (++uf < 8);
1420 }
1421
1422 /* we know urb->interval is 2^N uframes */
1423 uframe += period_uframes;
1424 } while (uframe < mod);
1425
1305 list_del (&itd->itd_list);
1306 itd_dma = itd->itd_dma;
1307 } else
1308 itd = NULL;
1309
1310 if (!itd) {
1311 spin_unlock_irqrestore (&ehci->lock, flags);
1312 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,

--- 110 unchanged lines hidden (view full) ---

1423 return 0;
1424 } while (++uf < 8);
1425 }
1426
1427 /* we know urb->interval is 2^N uframes */
1428 uframe += period_uframes;
1429 } while (uframe < mod);
1430
1426 stream->splits = cpu_to_le32(stream->raw_mask << (uframe & 7));
1431 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1427 return 1;
1428}
1429
1430/*
1431 * This scheduler plans almost as far into the future as it has actual
1432 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1433 * "as small as possible" to be cache-friendlier.) That limits the size
1434 * transfers you can stream reliably; avoid more than 64 msec per urb.

--- 104 unchanged lines hidden (view full) ---

1539 if (!stream->highspeed)
1540 urb->start_frame >>= 3;
1541 return 0;
1542}
1543
1544/*-------------------------------------------------------------------------*/
1545
1546static inline void
1432 return 1;
1433}
1434
1435/*
1436 * This scheduler plans almost as far into the future as it has actual
1437 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1438 * "as small as possible" to be cache-friendlier.) That limits the size
1439 * transfers you can stream reliably; avoid more than 64 msec per urb.

--- 104 unchanged lines hidden (view full) ---

1544 if (!stream->highspeed)
1545 urb->start_frame >>= 3;
1546 return 0;
1547}
1548
1549/*-------------------------------------------------------------------------*/
1550
1551static inline void
1547itd_init (struct ehci_iso_stream *stream, struct ehci_itd *itd)
1552itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1553 struct ehci_itd *itd)
1548{
1549 int i;
1550
1551 /* it's been recently zeroed */
1554{
1555 int i;
1556
1557 /* it's been recently zeroed */
1552 itd->hw_next = EHCI_LIST_END;
1558 itd->hw_next = EHCI_LIST_END(ehci);
1553 itd->hw_bufp [0] = stream->buf0;
1554 itd->hw_bufp [1] = stream->buf1;
1555 itd->hw_bufp [2] = stream->buf2;
1556
1557 for (i = 0; i < 8; i++)
1558 itd->index[i] = -1;
1559
1560 /* All other fields are filled when scheduling */
1561}
1562
1563static inline void
1559 itd->hw_bufp [0] = stream->buf0;
1560 itd->hw_bufp [1] = stream->buf1;
1561 itd->hw_bufp [2] = stream->buf2;
1562
1563 for (i = 0; i < 8; i++)
1564 itd->index[i] = -1;
1565
1566 /* All other fields are filled when scheduling */
1567}
1568
1569static inline void
1564itd_patch (
1570itd_patch(
1571 struct ehci_hcd *ehci,
1565 struct ehci_itd *itd,
1566 struct ehci_iso_sched *iso_sched,
1567 unsigned index,
1568 u16 uframe
1569)
1570{
1571 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1572 unsigned pg = itd->pg;
1573
1574 // BUG_ON (pg == 6 && uf->cross);
1575
1576 uframe &= 0x07;
1577 itd->index [uframe] = index;
1578
1572 struct ehci_itd *itd,
1573 struct ehci_iso_sched *iso_sched,
1574 unsigned index,
1575 u16 uframe
1576)
1577{
1578 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1579 unsigned pg = itd->pg;
1580
1581 // BUG_ON (pg == 6 && uf->cross);
1582
1583 uframe &= 0x07;
1584 itd->index [uframe] = index;
1585
1579 itd->hw_transaction [uframe] = uf->transaction;
1580 itd->hw_transaction [uframe] |= cpu_to_le32 (pg << 12);
1581 itd->hw_bufp [pg] |= cpu_to_le32 (uf->bufp & ~(u32)0);
1582 itd->hw_bufp_hi [pg] |= cpu_to_le32 ((u32)(uf->bufp >> 32));
1586 itd->hw_transaction[uframe] = uf->transaction;
1587 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1588 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1589 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1583
1584 /* iso_frame_desc[].offset must be strictly increasing */
1585 if (unlikely (uf->cross)) {
1586 u64 bufp = uf->bufp + 4096;
1590
1591 /* iso_frame_desc[].offset must be strictly increasing */
1592 if (unlikely (uf->cross)) {
1593 u64 bufp = uf->bufp + 4096;
1594
1587 itd->pg = ++pg;
1595 itd->pg = ++pg;
1588 itd->hw_bufp [pg] |= cpu_to_le32 (bufp & ~(u32)0);
1589 itd->hw_bufp_hi [pg] |= cpu_to_le32 ((u32)(bufp >> 32));
1596 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1597 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1590 }
1591}
1592
1593static inline void
1594itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1595{
1596 /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1597 itd->itd_next = ehci->pshadow [frame];
1598 itd->hw_next = ehci->periodic [frame];
1599 ehci->pshadow [frame].itd = itd;
1600 itd->frame = frame;
1601 wmb ();
1598 }
1599}
1600
1601static inline void
1602itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1603{
1604 /* always prepend ITD/SITD ... only QH tree is order-sensitive */
1605 itd->itd_next = ehci->pshadow [frame];
1606 itd->hw_next = ehci->periodic [frame];
1607 ehci->pshadow [frame].itd = itd;
1608 itd->frame = frame;
1609 wmb ();
1602 ehci->periodic [frame] = cpu_to_le32 (itd->itd_dma) | Q_TYPE_ITD;
1610 ehci->periodic[frame] = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1603}
1604
1605/* fit urb's itds into the selected schedule slot; activate as needed */
1606static int
1607itd_link_urb (
1608 struct ehci_hcd *ehci,
1609 struct urb *urb,
1610 unsigned mod,

--- 28 unchanged lines hidden (view full) ---

1639
1640 /* ASSERT: no itds for this endpoint in this uframe */
1641
1642 itd = list_entry (iso_sched->td_list.next,
1643 struct ehci_itd, itd_list);
1644 list_move_tail (&itd->itd_list, &stream->td_list);
1645 itd->stream = iso_stream_get (stream);
1646 itd->urb = usb_get_urb (urb);
1611}
1612
1613/* fit urb's itds into the selected schedule slot; activate as needed */
1614static int
1615itd_link_urb (
1616 struct ehci_hcd *ehci,
1617 struct urb *urb,
1618 unsigned mod,

--- 28 unchanged lines hidden (view full) ---

1647
1648 /* ASSERT: no itds for this endpoint in this uframe */
1649
1650 itd = list_entry (iso_sched->td_list.next,
1651 struct ehci_itd, itd_list);
1652 list_move_tail (&itd->itd_list, &stream->td_list);
1653 itd->stream = iso_stream_get (stream);
1654 itd->urb = usb_get_urb (urb);
1647 itd_init (stream, itd);
1655 itd_init (ehci, stream, itd);
1648 }
1649
1650 uframe = next_uframe & 0x07;
1651 frame = next_uframe >> 3;
1652
1653 itd->usecs [uframe] = stream->usecs;
1656 }
1657
1658 uframe = next_uframe & 0x07;
1659 frame = next_uframe >> 3;
1660
1661 itd->usecs [uframe] = stream->usecs;
1654 itd_patch (itd, iso_sched, packet, uframe);
1662 itd_patch(ehci, itd, iso_sched, packet, uframe);
1655
1656 next_uframe += stream->interval;
1657 stream->depth += stream->interval;
1658 next_uframe %= mod;
1659 packet++;
1660
1661 /* link completed itds into the schedule */
1662 if (((next_uframe >> 3) != frame)

--- 31 unchanged lines hidden (view full) ---

1694
1695 /* for each uframe with a packet */
1696 for (uframe = 0; uframe < 8; uframe++) {
1697 if (likely (itd->index[uframe] == -1))
1698 continue;
1699 urb_index = itd->index[uframe];
1700 desc = &urb->iso_frame_desc [urb_index];
1701
1663
1664 next_uframe += stream->interval;
1665 stream->depth += stream->interval;
1666 next_uframe %= mod;
1667 packet++;
1668
1669 /* link completed itds into the schedule */
1670 if (((next_uframe >> 3) != frame)

--- 31 unchanged lines hidden (view full) ---

1702
1703 /* for each uframe with a packet */
1704 for (uframe = 0; uframe < 8; uframe++) {
1705 if (likely (itd->index[uframe] == -1))
1706 continue;
1707 urb_index = itd->index[uframe];
1708 desc = &urb->iso_frame_desc [urb_index];
1709
1702 t = le32_to_cpup (&itd->hw_transaction [uframe]);
1710 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1703 itd->hw_transaction [uframe] = 0;
1704 stream->depth -= stream->interval;
1705
1706 /* report transfer status */
1707 if (unlikely (t & ISO_ERRS)) {
1708 urb->error_count++;
1709 if (t & EHCI_ISOC_BUF_ERR)
1710 desc->status = usb_pipein (urb->pipe)

--- 113 unchanged lines hidden (view full) ---

1824/*-------------------------------------------------------------------------*/
1825
1826/*
1827 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1828 * TTs in USB 2.0 hubs. These need microframe scheduling.
1829 */
1830
1831static inline void
1711 itd->hw_transaction [uframe] = 0;
1712 stream->depth -= stream->interval;
1713
1714 /* report transfer status */
1715 if (unlikely (t & ISO_ERRS)) {
1716 urb->error_count++;
1717 if (t & EHCI_ISOC_BUF_ERR)
1718 desc->status = usb_pipein (urb->pipe)

--- 113 unchanged lines hidden (view full) ---

1832/*-------------------------------------------------------------------------*/
1833
1834/*
1835 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1836 * TTs in USB 2.0 hubs. These need microframe scheduling.
1837 */
1838
1839static inline void
1832sitd_sched_init (
1840sitd_sched_init(
1841 struct ehci_hcd *ehci,
1833 struct ehci_iso_sched *iso_sched,
1834 struct ehci_iso_stream *stream,
1835 struct urb *urb
1836)
1837{
1838 unsigned i;
1839 dma_addr_t dma = urb->transfer_dma;
1840

--- 12 unchanged lines hidden (view full) ---

1853 length = urb->iso_frame_desc [i].length & 0x03ff;
1854 buf = dma + urb->iso_frame_desc [i].offset;
1855
1856 trans = SITD_STS_ACTIVE;
1857 if (((i + 1) == urb->number_of_packets)
1858 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1859 trans |= SITD_IOC;
1860 trans |= length << 16;
1842 struct ehci_iso_sched *iso_sched,
1843 struct ehci_iso_stream *stream,
1844 struct urb *urb
1845)
1846{
1847 unsigned i;
1848 dma_addr_t dma = urb->transfer_dma;
1849

--- 12 unchanged lines hidden (view full) ---

1862 length = urb->iso_frame_desc [i].length & 0x03ff;
1863 buf = dma + urb->iso_frame_desc [i].offset;
1864
1865 trans = SITD_STS_ACTIVE;
1866 if (((i + 1) == urb->number_of_packets)
1867 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1868 trans |= SITD_IOC;
1869 trans |= length << 16;
1861 packet->transaction = cpu_to_le32 (trans);
1870 packet->transaction = cpu_to_hc32(ehci, trans);
1862
1863 /* might need to cross a buffer page within a td */
1864 packet->bufp = buf;
1865 packet->buf1 = (buf + length) & ~0x0fff;
1866 if (packet->buf1 != (buf & ~(u64)0x0fff))
1867 packet->cross = 1;
1868
1869 /* OUT uses multiple start-splits */

--- 19 unchanged lines hidden (view full) ---

1889 int i;
1890 struct ehci_iso_sched *iso_sched;
1891 unsigned long flags;
1892
1893 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1894 if (iso_sched == NULL)
1895 return -ENOMEM;
1896
1871
1872 /* might need to cross a buffer page within a td */
1873 packet->bufp = buf;
1874 packet->buf1 = (buf + length) & ~0x0fff;
1875 if (packet->buf1 != (buf & ~(u64)0x0fff))
1876 packet->cross = 1;
1877
1878 /* OUT uses multiple start-splits */

--- 19 unchanged lines hidden (view full) ---

1898 int i;
1899 struct ehci_iso_sched *iso_sched;
1900 unsigned long flags;
1901
1902 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1903 if (iso_sched == NULL)
1904 return -ENOMEM;
1905
1897 sitd_sched_init (iso_sched, stream, urb);
1906 sitd_sched_init(ehci, iso_sched, stream, urb);
1898
1899 /* allocate/init sITDs */
1900 spin_lock_irqsave (&ehci->lock, flags);
1901 for (i = 0; i < urb->number_of_packets; i++) {
1902
1903 /* NOTE: for now, we don't try to handle wraparound cases
1904 * for IN (using sitd->hw_backpointer, like a FSTN), which
1905 * means we never need two sitds for full speed packets.

--- 35 unchanged lines hidden (view full) ---

1941
1942 spin_unlock_irqrestore (&ehci->lock, flags);
1943 return 0;
1944}
1945
1946/*-------------------------------------------------------------------------*/
1947
1948static inline void
1907
1908 /* allocate/init sITDs */
1909 spin_lock_irqsave (&ehci->lock, flags);
1910 for (i = 0; i < urb->number_of_packets; i++) {
1911
1912 /* NOTE: for now, we don't try to handle wraparound cases
1913 * for IN (using sitd->hw_backpointer, like a FSTN), which
1914 * means we never need two sitds for full speed packets.

--- 35 unchanged lines hidden (view full) ---

1950
1951 spin_unlock_irqrestore (&ehci->lock, flags);
1952 return 0;
1953}
1954
1955/*-------------------------------------------------------------------------*/
1956
1957static inline void
1949sitd_patch (
1958sitd_patch(
1959 struct ehci_hcd *ehci,
1950 struct ehci_iso_stream *stream,
1951 struct ehci_sitd *sitd,
1952 struct ehci_iso_sched *iso_sched,
1953 unsigned index
1954)
1955{
1956 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1957 u64 bufp = uf->bufp;
1958
1960 struct ehci_iso_stream *stream,
1961 struct ehci_sitd *sitd,
1962 struct ehci_iso_sched *iso_sched,
1963 unsigned index
1964)
1965{
1966 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1967 u64 bufp = uf->bufp;
1968
1959 sitd->hw_next = EHCI_LIST_END;
1969 sitd->hw_next = EHCI_LIST_END(ehci);
1960 sitd->hw_fullspeed_ep = stream->address;
1961 sitd->hw_uframe = stream->splits;
1962 sitd->hw_results = uf->transaction;
1970 sitd->hw_fullspeed_ep = stream->address;
1971 sitd->hw_uframe = stream->splits;
1972 sitd->hw_results = uf->transaction;
1963 sitd->hw_backpointer = EHCI_LIST_END;
1973 sitd->hw_backpointer = EHCI_LIST_END(ehci);
1964
1965 bufp = uf->bufp;
1974
1975 bufp = uf->bufp;
1966 sitd->hw_buf [0] = cpu_to_le32 (bufp);
1967 sitd->hw_buf_hi [0] = cpu_to_le32 (bufp >> 32);
1976 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1977 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1968
1978
1969 sitd->hw_buf [1] = cpu_to_le32 (uf->buf1);
1979 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1970 if (uf->cross)
1971 bufp += 4096;
1980 if (uf->cross)
1981 bufp += 4096;
1972 sitd->hw_buf_hi [1] = cpu_to_le32 (bufp >> 32);
1982 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1973 sitd->index = index;
1974}
1975
1976static inline void
1977sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1978{
1979 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1980 sitd->sitd_next = ehci->pshadow [frame];
1981 sitd->hw_next = ehci->periodic [frame];
1982 ehci->pshadow [frame].sitd = sitd;
1983 sitd->frame = frame;
1984 wmb ();
1983 sitd->index = index;
1984}
1985
1986static inline void
1987sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1988{
1989 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1990 sitd->sitd_next = ehci->pshadow [frame];
1991 sitd->hw_next = ehci->periodic [frame];
1992 ehci->pshadow [frame].sitd = sitd;
1993 sitd->frame = frame;
1994 wmb ();
1985 ehci->periodic [frame] = cpu_to_le32 (sitd->sitd_dma) | Q_TYPE_SITD;
1995 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1986}
1987
1988/* fit urb's sitds into the selected schedule slot; activate as needed */
1989static int
1990sitd_link_urb (
1991 struct ehci_hcd *ehci,
1992 struct urb *urb,
1993 unsigned mod,

--- 11 unchanged lines hidden (view full) ---

2005 /* usbfs ignores TT bandwidth */
2006 ehci_to_hcd(ehci)->self.bandwidth_allocated
2007 += stream->bandwidth;
2008 ehci_vdbg (ehci,
2009 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2010 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2011 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2012 (next_uframe >> 3) % ehci->periodic_size,
1996}
1997
1998/* fit urb's sitds into the selected schedule slot; activate as needed */
1999static int
2000sitd_link_urb (
2001 struct ehci_hcd *ehci,
2002 struct urb *urb,
2003 unsigned mod,

--- 11 unchanged lines hidden (view full) ---

2015 /* usbfs ignores TT bandwidth */
2016 ehci_to_hcd(ehci)->self.bandwidth_allocated
2017 += stream->bandwidth;
2018 ehci_vdbg (ehci,
2019 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2020 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2021 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2022 (next_uframe >> 3) % ehci->periodic_size,
2013 stream->interval, le32_to_cpu (stream->splits));
2023 stream->interval, hc32_to_cpu(ehci, stream->splits));
2014 stream->start = jiffies;
2015 }
2016 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2017
2018 /* fill sITDs frame by frame */
2019 for (packet = 0, sitd = NULL;
2020 packet < urb->number_of_packets;
2021 packet++) {

--- 4 unchanged lines hidden (view full) ---

2026 /* ASSERT: no itds for this endpoint in this frame */
2027
2028 sitd = list_entry (sched->td_list.next,
2029 struct ehci_sitd, sitd_list);
2030 list_move_tail (&sitd->sitd_list, &stream->td_list);
2031 sitd->stream = iso_stream_get (stream);
2032 sitd->urb = usb_get_urb (urb);
2033
2024 stream->start = jiffies;
2025 }
2026 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2027
2028 /* fill sITDs frame by frame */
2029 for (packet = 0, sitd = NULL;
2030 packet < urb->number_of_packets;
2031 packet++) {

--- 4 unchanged lines hidden (view full) ---

2036 /* ASSERT: no itds for this endpoint in this frame */
2037
2038 sitd = list_entry (sched->td_list.next,
2039 struct ehci_sitd, sitd_list);
2040 list_move_tail (&sitd->sitd_list, &stream->td_list);
2041 sitd->stream = iso_stream_get (stream);
2042 sitd->urb = usb_get_urb (urb);
2043
2034 sitd_patch (stream, sitd, sched, packet);
2044 sitd_patch(ehci, stream, sitd, sched, packet);
2035 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
2036 sitd);
2037
2038 next_uframe += stream->interval << 3;
2039 stream->depth += stream->interval << 3;
2040 }
2041 stream->next_uframe = next_uframe % mod;
2042

--- 21 unchanged lines hidden (view full) ---

2064 struct usb_iso_packet_descriptor *desc;
2065 u32 t;
2066 int urb_index = -1;
2067 struct ehci_iso_stream *stream = sitd->stream;
2068 struct usb_device *dev;
2069
2070 urb_index = sitd->index;
2071 desc = &urb->iso_frame_desc [urb_index];
2045 sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size,
2046 sitd);
2047
2048 next_uframe += stream->interval << 3;
2049 stream->depth += stream->interval << 3;
2050 }
2051 stream->next_uframe = next_uframe % mod;
2052

--- 21 unchanged lines hidden (view full) ---

2074 struct usb_iso_packet_descriptor *desc;
2075 u32 t;
2076 int urb_index = -1;
2077 struct ehci_iso_stream *stream = sitd->stream;
2078 struct usb_device *dev;
2079
2080 urb_index = sitd->index;
2081 desc = &urb->iso_frame_desc [urb_index];
2072 t = le32_to_cpup (&sitd->hw_results);
2082 t = hc32_to_cpup(ehci, &sitd->hw_results);
2073
2074 /* report transfer status */
2075 if (t & SITD_ERRS) {
2076 urb->error_count++;
2077 if (t & SITD_STS_DBE)
2078 desc->status = usb_pipein (urb->pipe)
2079 ? -ENOSR /* hc couldn't read */
2080 : -ECOMM; /* hc couldn't write */

--- 138 unchanged lines hidden (view full) ---

2219 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
2220 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2221 else
2222 clock = now_uframe + mod - 1;
2223 clock %= mod;
2224
2225 for (;;) {
2226 union ehci_shadow q, *q_p;
2083
2084 /* report transfer status */
2085 if (t & SITD_ERRS) {
2086 urb->error_count++;
2087 if (t & SITD_STS_DBE)
2088 desc->status = usb_pipein (urb->pipe)
2089 ? -ENOSR /* hc couldn't read */
2090 : -ECOMM; /* hc couldn't write */

--- 138 unchanged lines hidden (view full) ---

2229 if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
2230 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2231 else
2232 clock = now_uframe + mod - 1;
2233 clock %= mod;
2234
2235 for (;;) {
2236 union ehci_shadow q, *q_p;
2227 __le32 type, *hw_p;
2237 __hc32 type, *hw_p;
2228 unsigned uframes;
2229
2230 /* don't scan past the live uframe */
2231 frame = now_uframe >> 3;
2232 if (frame == (clock >> 3))
2233 uframes = now_uframe & 0x07;
2234 else {
2235 /* safe to scan the whole frame at once */
2236 now_uframe |= 0x07;
2237 uframes = 8;
2238 }
2239
2240restart:
2241 /* scan each element in frame's queue for completions */
2242 q_p = &ehci->pshadow [frame];
2243 hw_p = &ehci->periodic [frame];
2244 q.ptr = q_p->ptr;
2238 unsigned uframes;
2239
2240 /* don't scan past the live uframe */
2241 frame = now_uframe >> 3;
2242 if (frame == (clock >> 3))
2243 uframes = now_uframe & 0x07;
2244 else {
2245 /* safe to scan the whole frame at once */
2246 now_uframe |= 0x07;
2247 uframes = 8;
2248 }
2249
2250restart:
2251 /* scan each element in frame's queue for completions */
2252 q_p = &ehci->pshadow [frame];
2253 hw_p = &ehci->periodic [frame];
2254 q.ptr = q_p->ptr;
2245 type = Q_NEXT_TYPE (*hw_p);
2255 type = Q_NEXT_TYPE(ehci, *hw_p);
2246 modified = 0;
2247
2248 while (q.ptr != NULL) {
2249 unsigned uf;
2250 union ehci_shadow temp;
2251 int live;
2252
2253 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2256 modified = 0;
2257
2258 while (q.ptr != NULL) {
2259 unsigned uf;
2260 union ehci_shadow temp;
2261 int live;
2262
2263 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2254 switch (type) {
2264 switch (hc32_to_cpu(ehci, type)) {
2255 case Q_TYPE_QH:
2256 /* handle any completions */
2257 temp.qh = qh_get (q.qh);
2265 case Q_TYPE_QH:
2266 /* handle any completions */
2267 temp.qh = qh_get (q.qh);
2258 type = Q_NEXT_TYPE (q.qh->hw_next);
2268 type = Q_NEXT_TYPE(ehci, q.qh->hw_next);
2259 q = q.qh->qh_next;
2260 modified = qh_completions (ehci, temp.qh);
2261 if (unlikely (list_empty (&temp.qh->qtd_list)))
2262 intr_deschedule (ehci, temp.qh);
2263 qh_put (temp.qh);
2264 break;
2265 case Q_TYPE_FSTN:
2266 /* for "save place" FSTNs, look at QH entries
2267 * in the previous frame for completions.
2268 */
2269 q = q.qh->qh_next;
2270 modified = qh_completions (ehci, temp.qh);
2271 if (unlikely (list_empty (&temp.qh->qtd_list)))
2272 intr_deschedule (ehci, temp.qh);
2273 qh_put (temp.qh);
2274 break;
2275 case Q_TYPE_FSTN:
2276 /* for "save place" FSTNs, look at QH entries
2277 * in the previous frame for completions.
2278 */
2269 if (q.fstn->hw_prev != EHCI_LIST_END) {
2279 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2270 dbg ("ignoring completions from FSTNs");
2271 }
2280 dbg ("ignoring completions from FSTNs");
2281 }
2272 type = Q_NEXT_TYPE (q.fstn->hw_next);
2282 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2273 q = q.fstn->fstn_next;
2274 break;
2275 case Q_TYPE_ITD:
2276 /* skip itds for later in the frame */
2277 rmb ();
2278 for (uf = live ? uframes : 8; uf < 8; uf++) {
2279 if (0 == (q.itd->hw_transaction [uf]
2283 q = q.fstn->fstn_next;
2284 break;
2285 case Q_TYPE_ITD:
2286 /* skip itds for later in the frame */
2287 rmb ();
2288 for (uf = live ? uframes : 8; uf < 8; uf++) {
2289 if (0 == (q.itd->hw_transaction [uf]
2280 & ITD_ACTIVE))
2290 & ITD_ACTIVE(ehci)))
2281 continue;
2282 q_p = &q.itd->itd_next;
2283 hw_p = &q.itd->hw_next;
2291 continue;
2292 q_p = &q.itd->itd_next;
2293 hw_p = &q.itd->hw_next;
2284 type = Q_NEXT_TYPE (q.itd->hw_next);
2294 type = Q_NEXT_TYPE(ehci,
2295 q.itd->hw_next);
2285 q = *q_p;
2286 break;
2287 }
2288 if (uf != 8)
2289 break;
2290
2291 /* this one's ready ... HC won't cache the
2292 * pointer for much longer, if at all.
2293 */
2294 *q_p = q.itd->itd_next;
2295 *hw_p = q.itd->hw_next;
2296 q = *q_p;
2297 break;
2298 }
2299 if (uf != 8)
2300 break;
2301
2302 /* this one's ready ... HC won't cache the
2303 * pointer for much longer, if at all.
2304 */
2305 *q_p = q.itd->itd_next;
2306 *hw_p = q.itd->hw_next;
2296 type = Q_NEXT_TYPE (q.itd->hw_next);
2307 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2297 wmb();
2298 modified = itd_complete (ehci, q.itd);
2299 q = *q_p;
2300 break;
2301 case Q_TYPE_SITD:
2308 wmb();
2309 modified = itd_complete (ehci, q.itd);
2310 q = *q_p;
2311 break;
2312 case Q_TYPE_SITD:
2302 if ((q.sitd->hw_results & SITD_ACTIVE)
2313 if ((q.sitd->hw_results & SITD_ACTIVE(ehci))
2303 && live) {
2304 q_p = &q.sitd->sitd_next;
2305 hw_p = &q.sitd->hw_next;
2314 && live) {
2315 q_p = &q.sitd->sitd_next;
2316 hw_p = &q.sitd->hw_next;
2306 type = Q_NEXT_TYPE (q.sitd->hw_next);
2317 type = Q_NEXT_TYPE(ehci,
2318 q.sitd->hw_next);
2307 q = *q_p;
2308 break;
2309 }
2310 *q_p = q.sitd->sitd_next;
2311 *hw_p = q.sitd->hw_next;
2319 q = *q_p;
2320 break;
2321 }
2322 *q_p = q.sitd->sitd_next;
2323 *hw_p = q.sitd->hw_next;
2312 type = Q_NEXT_TYPE (q.sitd->hw_next);
2324 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2313 wmb();
2314 modified = sitd_complete (ehci, q.sitd);
2315 q = *q_p;
2316 break;
2317 default:
2318 dbg ("corrupt type %d frame %d shadow %p",
2319 type, frame, q.ptr);
2320 // BUG ();

--- 36 unchanged lines hidden --- 		2325 wmb();
2326 modified = sitd_complete (ehci, q.sitd);
2327 q = *q_p;
2328 break;
2329 default:
2330 dbg ("corrupt type %d frame %d shadow %p",
2331 type, frame, q.ptr);
2332 // BUG ();

--- 36 unchanged lines hidden ---