ehci-pci.c (abcc94480634f6fe9fc29b821261e8162c87ddd2) ehci-pci.c (188075211cc75a31190de4a19a084e3d83ee1c89)
1/*
2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
3 *
4 * Copyright (c) 2000-2004 by David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your

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53 pci_write_config_dword(pdev, where + 4, 0);
54 pci_write_config_byte(pdev, where + 2, 0);
55 } else
56 ehci_dbg(ehci, "BIOS handoff succeeded\n");
57 }
58 return 0;
59}
60
1/*
2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
3 *
4 * Copyright (c) 2000-2004 by David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your

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53 pci_write_config_dword(pdev, where + 4, 0);
54 pci_write_config_byte(pdev, where + 2, 0);
55 } else
56 ehci_dbg(ehci, "BIOS handoff succeeded\n");
57 }
58 return 0;
59}
60
61/* called by khubd or root hub init threads */
61/* called after powerup, by probe or system-pm "wakeup" */
62static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
63{
64 u32 temp;
65 int retval;
66 unsigned count = 256/4;
67
68 /* optional debug port, normally in the first BAR */
69 temp = pci_find_capability(pdev, 0x0a);
70 if (temp) {
71 pci_read_config_dword(pdev, temp, &temp);
72 temp >>= 16;
73 if ((temp & (3 << 13)) == (1 << 13)) {
74 temp &= 0x1fff;
75 ehci->debug = ehci_to_hcd(ehci)->regs + temp;
76 temp = readl(&ehci->debug->control);
77 ehci_info(ehci, "debug port %d%s\n",
78 HCS_DEBUG_PORT(ehci->hcs_params),
79 (temp & DBGP_ENABLED)
80 ? " IN USE"
81 : "");
82 if (!(temp & DBGP_ENABLED))
83 ehci->debug = NULL;
84 }
85 }
86
87 temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));
88
89 /* EHCI 0.96 and later may have "extended capabilities" */
90 while (temp && count--) {
91 u32 cap;
92
93 pci_read_config_dword(pdev, temp, &cap);
94 ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
95 switch (cap & 0xff) {
96 case 1: /* BIOS/SMM/... handoff */
97 if (bios_handoff(ehci, temp, cap) != 0)
98 return -EOPNOTSUPP;
99 break;
100 case 0: /* illegal reserved capability */
101 ehci_dbg(ehci, "illegal capability!\n");
102 cap = 0;
103 /* FALLTHROUGH */
104 default: /* unknown */
105 break;
106 }
107 temp = (cap >> 8) & 0xff;
108 }
109 if (!count) {
110 ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
111 return -EIO;
112 }
113
114 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
115 retval = pci_set_mwi(pdev);
116 if (!retval)
117 ehci_dbg(ehci, "MWI active\n");
118
119 ehci_port_power(ehci, 0);
120
121 return 0;
122}
123
124/* called by khubd or root hub (re)init threads; leaves HC in halt state */
62static int ehci_pci_reset(struct usb_hcd *hcd)
63{
64 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
65 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
66 u32 temp;
125static int ehci_pci_reset(struct usb_hcd *hcd)
126{
127 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
128 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
129 u32 temp;
67 unsigned count = 256/4;
130 int retval;
68
131
69 spin_lock_init (&ehci->lock);
70
71 ehci->caps = hcd->regs;
72 ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
73 dbg_hcs_params(ehci, "reset");
74 dbg_hcc_params(ehci, "reset");
75
76 /* cache this readonly data; minimize chip reads */
77 ehci->hcs_params = readl(&ehci->caps->hcs_params);
78
132 ehci->caps = hcd->regs;
133 ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
134 dbg_hcs_params(ehci, "reset");
135 dbg_hcc_params(ehci, "reset");
136
137 /* cache this readonly data; minimize chip reads */
138 ehci->hcs_params = readl(&ehci->caps->hcs_params);
139
140 retval = ehci_halt(ehci);
141 if (retval)
142 return retval;
143
79 /* NOTE: only the parts below this line are PCI-specific */
80
81 switch (pdev->vendor) {
82 case PCI_VENDOR_ID_TDI:
83 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
84 ehci->is_tdi_rh_tt = 1;
85 tdi_reset(ehci);
86 }

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106 DMA_31BIT_MASK) < 0)
107 ehci_warn(ehci, "can't enable NVidia "
108 "workaround for >2GB RAM\n");
109 break;
110 }
111 break;
112 }
113
144 /* NOTE: only the parts below this line are PCI-specific */
145
146 switch (pdev->vendor) {
147 case PCI_VENDOR_ID_TDI:
148 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
149 ehci->is_tdi_rh_tt = 1;
150 tdi_reset(ehci);
151 }

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171 DMA_31BIT_MASK) < 0)
172 ehci_warn(ehci, "can't enable NVidia "
173 "workaround for >2GB RAM\n");
174 break;
175 }
176 break;
177 }
178
114 /* optional debug port, normally in the first BAR */
115 temp = pci_find_capability(pdev, 0x0a);
116 if (temp) {
117 pci_read_config_dword(pdev, temp, &temp);
118 temp >>= 16;
119 if ((temp & (3 << 13)) == (1 << 13)) {
120 temp &= 0x1fff;
121 ehci->debug = hcd->regs + temp;
122 temp = readl(&ehci->debug->control);
123 ehci_info(ehci, "debug port %d%s\n",
124 HCS_DEBUG_PORT(ehci->hcs_params),
125 (temp & DBGP_ENABLED)
126 ? " IN USE"
127 : "");
128 if (!(temp & DBGP_ENABLED))
129 ehci->debug = NULL;
130 }
131 }
132
133 temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));
134
135 /* EHCI 0.96 and later may have "extended capabilities" */
136 while (temp && count--) {
137 u32 cap;
138
139 pci_read_config_dword(to_pci_dev(hcd->self.controller),
140 temp, &cap);
141 ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
142 switch (cap & 0xff) {
143 case 1: /* BIOS/SMM/... handoff */
144 if (bios_handoff(ehci, temp, cap) != 0)
145 return -EOPNOTSUPP;
146 break;
147 case 0: /* illegal reserved capability */
148 ehci_warn(ehci, "illegal capability!\n");
149 cap = 0;
150 /* FALLTHROUGH */
151 default: /* unknown */
152 break;
153 }
154 temp = (cap >> 8) & 0xff;
155 }
156 if (!count) {
157 ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
158 return -EIO;
159 }
160 if (ehci_is_TDI(ehci))
161 ehci_reset(ehci);
162
179 if (ehci_is_TDI(ehci))
180 ehci_reset(ehci);
181
163 ehci_port_power(ehci, 0);
164
165 /* at least the Genesys GL880S needs fixup here */
166 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
167 temp &= 0x0f;
168 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
169 ehci_dbg(ehci, "bogus port configuration: "
170 "cc=%d x pcc=%d < ports=%d\n",
171 HCS_N_CC(ehci->hcs_params),
172 HCS_N_PCC(ehci->hcs_params),

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179 ehci->hcs_params = temp;
180 break;
181 case PCI_VENDOR_ID_NVIDIA:
182 /* NF4: should be PCC=10 */
183 break;
184 }
185 }
186
182 /* at least the Genesys GL880S needs fixup here */
183 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
184 temp &= 0x0f;
185 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
186 ehci_dbg(ehci, "bogus port configuration: "
187 "cc=%d x pcc=%d < ports=%d\n",
188 HCS_N_CC(ehci->hcs_params),
189 HCS_N_PCC(ehci->hcs_params),

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196 ehci->hcs_params = temp;
197 break;
198 case PCI_VENDOR_ID_NVIDIA:
199 /* NF4: should be PCC=10 */
200 break;
201 }
202 }
203
187 /* force HC to halt state */
188 return ehci_halt(ehci);
189}
190
191static int ehci_pci_start(struct usb_hcd *hcd)
192{
193 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
194 int result = 0;
195 struct pci_dev *pdev;
196 u16 port_wake;
197
198 pdev = to_pci_dev(hcd->self.controller);
199
200 /* Serial Bus Release Number is at PCI 0x60 offset */
201 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
202
204 /* Serial Bus Release Number is at PCI 0x60 offset */
205 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
206
203 /* port wake capability, reported by boot firmware */
204 pci_read_config_word(pdev, 0x62, &port_wake);
205 hcd->can_wakeup = (port_wake & 1) != 0;
207 /* REVISIT: per-port wake capability (PCI 0x62) currently unused */
206
208
207 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
208 result = pci_set_mwi(pdev);
209 if (!result)
210 ehci_dbg(ehci, "MWI active\n");
209 retval = ehci_pci_reinit(ehci, pdev);
211
210
212 return ehci_run(hcd);
211 /* finish init */
212 return ehci_init(hcd);
213}
214
213}
214
215/* always called by thread; normally rmmod */
216
217static void ehci_pci_stop(struct usb_hcd *hcd)
218{
219 ehci_stop(hcd);
220}
221
222/*-------------------------------------------------------------------------*/
223
224#ifdef CONFIG_PM
225
226/* suspend/resume, section 4.3 */
227
228/* These routines rely on the PCI bus glue
229 * to handle powerdown and wakeup, and currently also on

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245 return 0;
246}
247
248static int ehci_pci_resume(struct usb_hcd *hcd)
249{
250 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
251 unsigned port;
252 struct usb_device *root = hcd->self.root_hub;
215/*-------------------------------------------------------------------------*/
216
217#ifdef CONFIG_PM
218
219/* suspend/resume, section 4.3 */
220
221/* These routines rely on the PCI bus glue
222 * to handle powerdown and wakeup, and currently also on

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238 return 0;
239}
240
241static int ehci_pci_resume(struct usb_hcd *hcd)
242{
243 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
244 unsigned port;
245 struct usb_device *root = hcd->self.root_hub;
246 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
253 int retval = -EINVAL;
254
255 // maybe restore FLADJ
256
257 if (time_before(jiffies, ehci->next_statechange))
258 msleep(100);
259
260 /* If CF is clear, we lost PCI Vaux power and need to restart. */
247 int retval = -EINVAL;
248
249 // maybe restore FLADJ
250
251 if (time_before(jiffies, ehci->next_statechange))
252 msleep(100);
253
254 /* If CF is clear, we lost PCI Vaux power and need to restart. */
261 if (readl(&ehci->regs->configured_flag) != cpu_to_le32(FLAG_CF))
255 if (readl(&ehci->regs->configured_flag) != FLAG_CF)
262 goto restart;
263
264 /* If any port is suspended (or owned by the companion),
265 * we know we can/must resume the HC (and mustn't reset it).
266 * We just defer that to the root hub code.
267 */
268 for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
269 u32 status;

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287 USB_STATE_NOTATTACHED);
288 }
289
290 /* Else reset, to cope with power loss or flush-to-storage
291 * style "resume" having let BIOS kick in during reboot.
292 */
293 (void) ehci_halt(ehci);
294 (void) ehci_reset(ehci);
256 goto restart;
257
258 /* If any port is suspended (or owned by the companion),
259 * we know we can/must resume the HC (and mustn't reset it).
260 * We just defer that to the root hub code.
261 */
262 for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
263 u32 status;

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281 USB_STATE_NOTATTACHED);
282 }
283
284 /* Else reset, to cope with power loss or flush-to-storage
285 * style "resume" having let BIOS kick in during reboot.
286 */
287 (void) ehci_halt(ehci);
288 (void) ehci_reset(ehci);
295 (void) ehci_pci_reset(hcd);
289 (void) ehci_pci_reinit(ehci, pdev);
296
297 /* emptying the schedule aborts any urbs */
298 spin_lock_irq(&ehci->lock);
299 if (ehci->reclaim)
300 ehci->reclaim_ready = 1;
301 ehci_work(ehci, NULL);
302 spin_unlock_irq(&ehci->lock);
303
304 /* restart; khubd will disconnect devices */
305 retval = ehci_run(hcd);
306
290
291 /* emptying the schedule aborts any urbs */
292 spin_lock_irq(&ehci->lock);
293 if (ehci->reclaim)
294 ehci->reclaim_ready = 1;
295 ehci_work(ehci, NULL);
296 spin_unlock_irq(&ehci->lock);
297
298 /* restart; khubd will disconnect devices */
299 retval = ehci_run(hcd);
300
307 /* here we "know" root ports should always stay powered;
308 * but some controllers may lose all power.
309 */
301 /* here we "know" root ports should always stay powered */
310 ehci_port_power(ehci, 1);
311
312 return retval;
313}
314#endif
315
316static const struct hc_driver ehci_pci_hc_driver = {
317 .description = hcd_name,

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323 */
324 .irq = ehci_irq,
325 .flags = HCD_MEMORY | HCD_USB2,
326
327 /*
328 * basic lifecycle operations
329 */
330 .reset = ehci_pci_reset,
302 ehci_port_power(ehci, 1);
303
304 return retval;
305}
306#endif
307
308static const struct hc_driver ehci_pci_hc_driver = {
309 .description = hcd_name,

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315 */
316 .irq = ehci_irq,
317 .flags = HCD_MEMORY | HCD_USB2,
318
319 /*
320 * basic lifecycle operations
321 */
322 .reset = ehci_pci_reset,
331 .start = ehci_pci_start,
323 .start = ehci_run,
332#ifdef CONFIG_PM
333 .suspend = ehci_pci_suspend,
334 .resume = ehci_pci_resume,
335#endif
324#ifdef CONFIG_PM
325 .suspend = ehci_pci_suspend,
326 .resume = ehci_pci_resume,
327#endif
336 .stop = ehci_pci_stop,
328 .stop = ehci_stop,
337
338 /*
339 * managing i/o requests and associated device resources
340 */
341 .urb_enqueue = ehci_urb_enqueue,
342 .urb_dequeue = ehci_urb_dequeue,
343 .endpoint_disable = ehci_endpoint_disable,
344

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330 /*
331 * managing i/o requests and associated device resources
332 */
333 .urb_enqueue = ehci_urb_enqueue,
334 .urb_dequeue = ehci_urb_dequeue,
335 .endpoint_disable = ehci_endpoint_disable,
336

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