| dwc3-pci.c (e492ce9bcaa1c9661cd3dd6cff0eedf2fa640f31) | dwc3-pci.c (73203bde3a95a48f27b2454dc6b955280c641afe) |
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| 1// SPDX-License-Identifier: GPL-2.0 2/** 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> --- 27 unchanged lines hidden (view full) --- 36#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37#define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39#define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e 40#define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41#define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 42#define PCI_DEVICE_ID_INTEL_JSP 0x4dee 43#define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 | 1// SPDX-License-Identifier: GPL-2.0 2/** 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> --- 27 unchanged lines hidden (view full) --- 36#define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37#define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38#define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39#define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e 40#define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41#define PCI_DEVICE_ID_INTEL_TGPH 0x43ee 42#define PCI_DEVICE_ID_INTEL_JSP 0x4dee 43#define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 |
| 44#define PCI_DEVICE_ID_INTEL_TGL 0x9a15 |
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| 44 45#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 46#define PCI_INTEL_BXT_FUNC_PMU_PWR 4 47#define PCI_INTEL_BXT_STATE_D0 0 48#define PCI_INTEL_BXT_STATE_D3 3 49 50#define GP_RWBAR 1 51#define GP_RWREG1 0xa0 --- 327 unchanged lines hidden (view full) --- 379 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 380 381 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), 382 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 383 384 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS), 385 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 386 | 45 46#define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 47#define PCI_INTEL_BXT_FUNC_PMU_PWR 4 48#define PCI_INTEL_BXT_STATE_D0 0 49#define PCI_INTEL_BXT_STATE_D3 3 50 51#define GP_RWBAR 1 52#define GP_RWREG1 0xa0 --- 327 unchanged lines hidden (view full) --- 380 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 381 382 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), 383 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 384 385 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLS), 386 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 387 |
| 388 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL), 389 (kernel_ulong_t) &dwc3_pci_intel_swnode, }, 390 |
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| 387 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 388 (kernel_ulong_t) &dwc3_pci_amd_swnode, }, 389 { } /* Terminating Entry */ 390}; 391MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 392 393#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 394static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) --- 87 unchanged lines hidden --- | 391 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 392 (kernel_ulong_t) &dwc3_pci_amd_swnode, }, 393 { } /* Terminating Entry */ 394}; 395MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 396 397#if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 398static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) --- 87 unchanged lines hidden --- |