| Kconfig (ba1773fb7de92498d3cd51a1cb5a8855b8996912) | Kconfig (9cecca75b5a0da1bb70465ed3863db5cbf00850b) |
|---|---|
| 1config USB_DWC3 2 tristate "DesignWare USB3 DRD Core Support" 3 depends on (USB || USB_GADGET) && HAS_DMA 4 select USB_XHCI_PLATFORM if USB_XHCI_HCD 5 help 6 Say Y or M here if your system has a Dual Role SuperSpeed 7 USB controller based on the DesignWare USB3 IP Core. 8 --- 56 unchanged lines hidden (view full) --- 65 depends on (ARCH_EXYNOS || COMPILE_TEST) && OF 66 default USB_DWC3 67 help 68 Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside, 69 say 'Y' or 'M' if you have one such device. 70 71config USB_DWC3_PCI 72 tristate "PCIe-based Platforms" | 1config USB_DWC3 2 tristate "DesignWare USB3 DRD Core Support" 3 depends on (USB || USB_GADGET) && HAS_DMA 4 select USB_XHCI_PLATFORM if USB_XHCI_HCD 5 help 6 Say Y or M here if your system has a Dual Role SuperSpeed 7 USB controller based on the DesignWare USB3 IP Core. 8 --- 56 unchanged lines hidden (view full) --- 65 depends on (ARCH_EXYNOS || COMPILE_TEST) && OF 66 default USB_DWC3 67 help 68 Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside, 69 say 'Y' or 'M' if you have one such device. 70 71config USB_DWC3_PCI 72 tristate "PCIe-based Platforms" |
| 73 depends on PCI | 73 depends on PCI && ACPI |
| 74 default USB_DWC3 75 help 76 If you're using the DesignWare Core IP with a PCIe, please say 77 'Y' or 'M' here. 78 79 One such PCIe-based platform is Synopsys' PCIe HAPS model of 80 this IP. 81 --- 27 unchanged lines hidden --- | 74 default USB_DWC3 75 help 76 If you're using the DesignWare Core IP with a PCIe, please say 77 'Y' or 'M' here. 78 79 One such PCIe-based platform is Synopsys' PCIe HAPS model of 80 this IP. 81 --- 27 unchanged lines hidden --- |