hcd.c (5f9e60c06175c3525c2f7ae1d6807f7d6c61efe3) hcd.c (d37b939cf41f6a211d6c5611915c5dd4552cd935)
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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3293 * Return: non-zero if failed to enter suspend mode for host.
3294 *
3295 * This function is for entering Host mode suspend.
3296 * Must NOT be called with interrupt disabled or spinlock held.
3297 */
3298int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3299{
3300 unsigned long flags;
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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3293 * Return: non-zero if failed to enter suspend mode for host.
3294 *
3295 * This function is for entering Host mode suspend.
3296 * Must NOT be called with interrupt disabled or spinlock held.
3297 */
3298int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3299{
3300 unsigned long flags;
3301 u32 hprt0;
3302 u32 pcgctl;
3303 u32 gotgctl;
3304 int ret = 0;
3305
3306 dev_dbg(hsotg->dev, "%s()\n", __func__);
3307
3308 spin_lock_irqsave(&hsotg->lock, flags);
3309

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3318 case DWC2_POWER_DOWN_PARAM_PARTIAL:
3319 ret = dwc2_enter_partial_power_down(hsotg);
3320 if (ret)
3321 dev_err(hsotg->dev,
3322 "enter partial_power_down failed.\n");
3323 break;
3324 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
3325 case DWC2_POWER_DOWN_PARAM_NONE:
3301 u32 pcgctl;
3302 u32 gotgctl;
3303 int ret = 0;
3304
3305 dev_dbg(hsotg->dev, "%s()\n", __func__);
3306
3307 spin_lock_irqsave(&hsotg->lock, flags);
3308

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3317 case DWC2_POWER_DOWN_PARAM_PARTIAL:
3318 ret = dwc2_enter_partial_power_down(hsotg);
3319 if (ret)
3320 dev_err(hsotg->dev,
3321 "enter partial_power_down failed.\n");
3322 break;
3323 case DWC2_POWER_DOWN_PARAM_HIBERNATION:
3324 case DWC2_POWER_DOWN_PARAM_NONE:
3326 default:
3327 hprt0 = dwc2_read_hprt0(hsotg);
3328 hprt0 |= HPRT0_SUSP;
3329 dwc2_writel(hsotg, hprt0, HPRT0);
3330 hsotg->bus_suspended = true;
3331 /*
3325 /*
3332 * If power_down is supported, Phy clock will be suspended
3333 * after registers are backuped.
3326 * If not hibernation nor partial power down are supported,
3327 * clock gating is used to save power.
3334 */
3328 */
3335 if (!hsotg->params.power_down) {
3336 /* Suspend the Phy Clock */
3337 pcgctl = dwc2_readl(hsotg, PCGCTL);
3338 pcgctl |= PCGCTL_STOPPCLK;
3339 dwc2_writel(hsotg, pcgctl, PCGCTL);
3340 udelay(10);
3341 }
3329 dwc2_host_enter_clock_gating(hsotg);
3330 break;
3342 }
3343
3344 /* For HNP the bus must be suspended for at least 200ms */
3345 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3346 pcgctl = dwc2_readl(hsotg, PCGCTL);
3347 pcgctl &= ~PCGCTL_STOPPCLK;
3348 dwc2_writel(hsotg, pcgctl, PCGCTL);
3349

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3332
3333 /* For HNP the bus must be suspended for at least 200ms */
3334 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3335 pcgctl = dwc2_readl(hsotg, PCGCTL);
3336 pcgctl &= ~PCGCTL_STOPPCLK;
3337 dwc2_writel(hsotg, pcgctl, PCGCTL);
3338

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