gadget.c (b6afdbe8e841e20297a38e2af0a053d8eb26c19b) gadget.c (c00dd4a6ec20a58ed38be85f8e47efda40625f17)
1/**
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/

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60 writel(readl(ptr) | val, ptr);
61}
62
63static inline void __bic32(void __iomem *ptr, u32 val)
64{
65 writel(readl(ptr) & ~val, ptr);
66}
67
1/**
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/

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60 writel(readl(ptr) | val, ptr);
61}
62
63static inline void __bic32(void __iomem *ptr, u32 val)
64{
65 writel(readl(ptr) & ~val, ptr);
66}
67
68/* forward decleration of functions */
68static inline struct s3c_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
69 u32 ep_index, u32 dir_in)
70{
71 if (dir_in)
72 return hsotg->eps_in[ep_index];
73 else
74 return hsotg->eps_out[ep_index];
75}
76
77/* forward declaration of functions */
69static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg);
70
71/**
72 * using_dma - return the DMA status of the driver.
73 * @hsotg: The driver state.
74 *
75 * Return true if we're using DMA.
76 *
77 * Currently, we have the DMA support code worked into everywhere
78 * that needs it, but the AMBA DMA implementation in the hardware can
79 * only DMA from 32bit aligned addresses. This means that gadgets such
80 * as the CDC Ethernet cannot work as they often pass packets which are
81 * not 32bit aligned.
82 *
83 * Unfortunately the choice to use DMA or not is global to the controller
84 * and seems to be only settable when the controller is being put through
85 * a core reset. This means we either need to fix the gadgets to take
86 * account of DMA alignment, or add bounce buffers (yuerk).
87 *
78static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg);
79
80/**
81 * using_dma - return the DMA status of the driver.
82 * @hsotg: The driver state.
83 *
84 * Return true if we're using DMA.
85 *
86 * Currently, we have the DMA support code worked into everywhere
87 * that needs it, but the AMBA DMA implementation in the hardware can
88 * only DMA from 32bit aligned addresses. This means that gadgets such
89 * as the CDC Ethernet cannot work as they often pass packets which are
90 * not 32bit aligned.
91 *
92 * Unfortunately the choice to use DMA or not is global to the controller
93 * and seems to be only settable when the controller is being put through
94 * a core reset. This means we either need to fix the gadgets to take
95 * account of DMA alignment, or add bounce buffers (yuerk).
96 *
88 * Until this issue is sorted out, we always return 'false'.
97 * g_using_dma is set depending on dts flag.
89 */
90static inline bool using_dma(struct dwc2_hsotg *hsotg)
91{
98 */
99static inline bool using_dma(struct dwc2_hsotg *hsotg)
100{
92 return false; /* support is not complete */
101 return hsotg->g_using_dma;
93}
94
95/**
96 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
97 * @hsotg: The device state
98 * @ints: A bitmask of the interrupts to enable
99 */
100static void s3c_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)

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160/**
161 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
162 * @hsotg: The device instance.
163 */
164static void s3c_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
165{
166 unsigned int ep;
167 unsigned int addr;
102}
103
104/**
105 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
106 * @hsotg: The device state
107 * @ints: A bitmask of the interrupts to enable
108 */
109static void s3c_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)

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169/**
170 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
171 * @hsotg: The device instance.
172 */
173static void s3c_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
174{
175 unsigned int ep;
176 unsigned int addr;
168 unsigned int size;
169 int timeout;
170 u32 val;
171
177 int timeout;
178 u32 val;
179
172 /* set FIFO sizes to 2048/1024 */
180 /* Reset fifo map if not correctly cleared during previous session */
181 WARN_ON(hsotg->fifo_map);
182 hsotg->fifo_map = 0;
173
183
174 writel(2048, hsotg->regs + GRXFSIZ);
175 writel((2048 << FIFOSIZE_STARTADDR_SHIFT) |
176 (1024 << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ);
184 /* set RX/NPTX FIFO sizes */
185 writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
186 writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
187 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
188 hsotg->regs + GNPTXFSIZ);
177
178 /*
179 * arange all the rest of the TX FIFOs, as some versions of this
180 * block have overlapping default addresses. This also ensures
181 * that if the settings have been changed, then they are set to
182 * known values.
183 */
184
185 /* start at the end of the GNPTXFSIZ, rounded up */
189
190 /*
191 * arange all the rest of the TX FIFOs, as some versions of this
192 * block have overlapping default addresses. This also ensures
193 * that if the settings have been changed, then they are set to
194 * known values.
195 */
196
197 /* start at the end of the GNPTXFSIZ, rounded up */
186 addr = 2048 + 1024;
198 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
187
188 /*
199
200 /*
189 * Because we have not enough memory to have each TX FIFO of size at
190 * least 3072 bytes (the maximum single packet size), we create four
191 * FIFOs of lenght 1024, and four of length 3072 bytes, and assing
201 * Configure fifos sizes from provided configuration and assign
192 * them to endpoints dynamically according to maxpacket size value of
193 * given endpoint.
194 */
202 * them to endpoints dynamically according to maxpacket size value of
203 * given endpoint.
204 */
195
196 /* 256*4=1024 bytes FIFO length */
197 size = 256;
198 for (ep = 1; ep <= 4; ep++) {
205 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
206 if (!hsotg->g_tx_fifo_sz[ep])
207 continue;
199 val = addr;
208 val = addr;
200 val |= size << FIFOSIZE_DEPTH_SHIFT;
201 WARN_ONCE(addr + size > hsotg->fifo_mem,
209 val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
210 WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
202 "insufficient fifo memory");
211 "insufficient fifo memory");
203 addr += size;
212 addr += hsotg->g_tx_fifo_sz[ep];
204
205 writel(val, hsotg->regs + DPTXFSIZN(ep));
206 }
213
214 writel(val, hsotg->regs + DPTXFSIZN(ep));
215 }
207 /* 768*4=3072 bytes FIFO length */
208 size = 768;
209 for (ep = 5; ep <= 8; ep++) {
210 val = addr;
211 val |= size << FIFOSIZE_DEPTH_SHIFT;
212 WARN_ONCE(addr + size > hsotg->fifo_mem,
213 "insufficient fifo memory");
214 addr += size;
215
216
216 writel(val, hsotg->regs + DPTXFSIZN(ep));
217 }
218
219 /*
220 * according to p428 of the design guide, we need to ensure that
221 * all fifos are flushed before continuing
222 */
223
224 writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
225 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
226

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231
232 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
233 break;
234
235 if (--timeout == 0) {
236 dev_err(hsotg->dev,
237 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
238 __func__, val);
217 /*
218 * according to p428 of the design guide, we need to ensure that
219 * all fifos are flushed before continuing
220 */
221
222 writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
223 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
224

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229
230 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
231 break;
232
233 if (--timeout == 0) {
234 dev_err(hsotg->dev,
235 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
236 __func__, val);
237 break;
239 }
240
241 udelay(1);
242 }
243
244 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
245}
246

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599 if (dir_in && index != 0)
600 if (hs_ep->isochronous)
601 epsize = DXEPTSIZ_MC(packets);
602 else
603 epsize = DXEPTSIZ_MC(1);
604 else
605 epsize = 0;
606
238 }
239
240 udelay(1);
241 }
242
243 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
244}
245

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598 if (dir_in && index != 0)
599 if (hs_ep->isochronous)
600 epsize = DXEPTSIZ_MC(packets);
601 else
602 epsize = DXEPTSIZ_MC(1);
603 else
604 epsize = 0;
605
607 if (index != 0 && ureq->zero) {
608 /*
609 * test for the packets being exactly right for the
610 * transfer
611 */
612
613 if (length == (packets * hs_ep->ep.maxpacket))
614 packets++;
606 /*
607 * zero length packet should be programmed on its own and should not
608 * be counted in DIEPTSIZ.PktCnt with other packets.
609 */
610 if (dir_in && ureq->zero && !continuing) {
611 /* Test if zlp is actually required. */
612 if ((ureq->length >= hs_ep->ep.maxpacket) &&
613 !(ureq->length % hs_ep->ep.maxpacket))
614 hs_ep->send_zlp = 1;
615 }
616
617 epsize |= DXEPTSIZ_PKTCNT(packets);
618 epsize |= DXEPTSIZ_XFERSIZE(length);
619
620 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
621 __func__, packets, length, ureq->length, epsize, epsize_reg);
622

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639
640 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
641 __func__, &ureq->dma, dma_reg);
642 }
643
644 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
645 ctrl |= DXEPCTL_USBACTEP;
646
615 }
616
617 epsize |= DXEPTSIZ_PKTCNT(packets);
618 epsize |= DXEPTSIZ_XFERSIZE(length);
619
620 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
621 __func__, packets, length, ureq->length, epsize, epsize_reg);
622

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639
640 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
641 __func__, &ureq->dma, dma_reg);
642 }
643
644 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
645 ctrl |= DXEPCTL_USBACTEP;
646
647 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
647 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
648
649 /* For Setup request do not clear NAK */
648
649 /* For Setup request do not clear NAK */
650 if (hsotg->setup && index == 0)
651 hsotg->setup = 0;
652 else
650 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
653 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
654
651 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
652
655
656 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
657 writel(ctrl, hsotg->regs + epctrl_reg);
658
659 /*
660 * set these, it seems that DMA support increments past the end
661 * of the packet buffer so we need to calculate the length from
662 * this information.
663 */

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681
682 /*
683 * Note, trying to clear the NAK here causes problems with transmit
684 * on the S3C6400 ending up with the TXFIFO becoming full.
685 */
686
687 /* check ep is enabled */
688 if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
653 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
654 writel(ctrl, hsotg->regs + epctrl_reg);
655
656 /*
657 * set these, it seems that DMA support increments past the end
658 * of the packet buffer so we need to calculate the length from
659 * this information.
660 */

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678
679 /*
680 * Note, trying to clear the NAK here causes problems with transmit
681 * on the S3C6400 ending up with the TXFIFO becoming full.
682 */
683
684 /* check ep is enabled */
685 if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
689 dev_warn(hsotg->dev,
686 dev_dbg(hsotg->dev,
690 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
691 index, readl(hsotg->regs + epctrl_reg));
692
693 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
694 __func__, readl(hsotg->regs + epctrl_reg));
695
696 /* enable ep interrupts */
697 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);

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814 * @windex: The control request wIndex field (in host order).
815 *
816 * Convert the given wIndex into a pointer to an driver endpoint
817 * structure, or return NULL if it is not a valid endpoint.
818 */
819static struct s3c_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
820 u32 windex)
821{
687 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
688 index, readl(hsotg->regs + epctrl_reg));
689
690 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
691 __func__, readl(hsotg->regs + epctrl_reg));
692
693 /* enable ep interrupts */
694 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);

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811 * @windex: The control request wIndex field (in host order).
812 *
813 * Convert the given wIndex into a pointer to an driver endpoint
814 * structure, or return NULL if it is not a valid endpoint.
815 */
816static struct s3c_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
817 u32 windex)
818{
822 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
819 struct s3c_hsotg_ep *ep;
823 int dir = (windex & USB_DIR_IN) ? 1 : 0;
824 int idx = windex & 0x7F;
825
826 if (windex >= 0x100)
827 return NULL;
828
829 if (idx > hsotg->num_of_eps)
830 return NULL;
831
820 int dir = (windex & USB_DIR_IN) ? 1 : 0;
821 int idx = windex & 0x7F;
822
823 if (windex >= 0x100)
824 return NULL;
825
826 if (idx > hsotg->num_of_eps)
827 return NULL;
828
829 ep = index_to_ep(hsotg, idx, dir);
830
832 if (idx && ep->dir_in != dir)
833 return NULL;
834
835 return ep;
836}
837
838/**
839 * s3c_hsotg_send_reply - send reply to control request

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859 hsotg->ep0_reply = req;
860 if (!req) {
861 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
862 return -ENOMEM;
863 }
864
865 req->buf = hsotg->ep0_buff;
866 req->length = length;
831 if (idx && ep->dir_in != dir)
832 return NULL;
833
834 return ep;
835}
836
837/**
838 * s3c_hsotg_send_reply - send reply to control request

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858 hsotg->ep0_reply = req;
859 if (!req) {
860 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
861 return -ENOMEM;
862 }
863
864 req->buf = hsotg->ep0_buff;
865 req->length = length;
867 req->zero = 1; /* always do zero-length final transfer */
866 /*
867 * zero flag is for sending zlp in DATA IN stage. It has no impact on
868 * STATUS stage.
869 */
870 req->zero = 0;
868 req->complete = s3c_hsotg_complete_oursetup;
869
870 if (length)
871 memcpy(req->buf, buff, length);
871 req->complete = s3c_hsotg_complete_oursetup;
872
873 if (length)
874 memcpy(req->buf, buff, length);
872 else
873 ep->sent_zlp = 1;
874
875 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
876 if (ret) {
877 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
878 return ret;
879 }
880
881 return 0;
882}
883
884/**
885 * s3c_hsotg_process_req_status - process request GET_STATUS
886 * @hsotg: The device state
887 * @ctrl: USB control request
888 */
889static int s3c_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
890 struct usb_ctrlrequest *ctrl)
891{
875
876 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
877 if (ret) {
878 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
879 return ret;
880 }
881
882 return 0;
883}
884
885/**
886 * s3c_hsotg_process_req_status - process request GET_STATUS
887 * @hsotg: The device state
888 * @ctrl: USB control request
889 */
890static int s3c_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
891 struct usb_ctrlrequest *ctrl)
892{
892 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
893 struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0];
893 struct s3c_hsotg_ep *ep;
894 __le16 reply;
895 int ret;
896
897 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
898
899 if (!ep0->dir_in) {
900 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);

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955/**
956 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
957 * @hsotg: The device state
958 * @ctrl: USB control request
959 */
960static int s3c_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
961 struct usb_ctrlrequest *ctrl)
962{
894 struct s3c_hsotg_ep *ep;
895 __le16 reply;
896 int ret;
897
898 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
899
900 if (!ep0->dir_in) {
901 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);

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956/**
957 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
958 * @hsotg: The device state
959 * @ctrl: USB control request
960 */
961static int s3c_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
962 struct usb_ctrlrequest *ctrl)
963{
963 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
964 struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0];
964 struct s3c_hsotg_req *hs_req;
965 bool restart;
966 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
967 struct s3c_hsotg_ep *ep;
968 int ret;
969 bool halted;
970
971 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",

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1001 /*
1002 * If we have request in progress,
1003 * then complete it
1004 */
1005 if (ep->req) {
1006 hs_req = ep->req;
1007 ep->req = NULL;
1008 list_del_init(&hs_req->queue);
965 struct s3c_hsotg_req *hs_req;
966 bool restart;
967 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
968 struct s3c_hsotg_ep *ep;
969 int ret;
970 bool halted;
971
972 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",

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1002 /*
1003 * If we have request in progress,
1004 * then complete it
1005 */
1006 if (ep->req) {
1007 hs_req = ep->req;
1008 ep->req = NULL;
1009 list_del_init(&hs_req->queue);
1009 usb_gadget_giveback_request(&ep->ep,
1010 &hs_req->req);
1010 if (hs_req->req.complete) {
1011 spin_unlock(&hsotg->lock);
1012 usb_gadget_giveback_request(
1013 &ep->ep, &hs_req->req);
1014 spin_lock(&hsotg->lock);
1015 }
1011 }
1012
1013 /* If we have pending request, then start it */
1016 }
1017
1018 /* If we have pending request, then start it */
1014 restart = !list_empty(&ep->queue);
1015 if (restart) {
1016 hs_req = get_ep_head(ep);
1017 s3c_hsotg_start_req(hsotg, ep,
1018 hs_req, false);
1019 if (!ep->req) {
1020 restart = !list_empty(&ep->queue);
1021 if (restart) {
1022 hs_req = get_ep_head(ep);
1023 s3c_hsotg_start_req(hsotg, ep,
1024 hs_req, false);
1025 }
1019 }
1020 }
1021
1022 break;
1023
1024 default:
1025 return -ENOENT;
1026 }

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1035/**
1036 * s3c_hsotg_stall_ep0 - stall ep0
1037 * @hsotg: The device state
1038 *
1039 * Set stall for ep0 as response for setup request.
1040 */
1041static void s3c_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1042{
1026 }
1027 }
1028
1029 break;
1030
1031 default:
1032 return -ENOENT;
1033 }

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1042/**
1043 * s3c_hsotg_stall_ep0 - stall ep0
1044 * @hsotg: The device state
1045 *
1046 * Set stall for ep0 as response for setup request.
1047 */
1048static void s3c_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1049{
1043 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1050 struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0];
1044 u32 reg;
1045 u32 ctrl;
1046
1047 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1048 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1049
1050 /*
1051 * DxEPCTL_Stall will be cleared by EP once it has

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1075 *
1076 * The controller has received the SETUP phase of a control request, and
1077 * needs to work out what to do next (and whether to pass it on to the
1078 * gadget driver).
1079 */
1080static void s3c_hsotg_process_control(struct dwc2_hsotg *hsotg,
1081 struct usb_ctrlrequest *ctrl)
1082{
1051 u32 reg;
1052 u32 ctrl;
1053
1054 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1055 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1056
1057 /*
1058 * DxEPCTL_Stall will be cleared by EP once it has

--- 23 unchanged lines hidden (view full) ---

1082 *
1083 * The controller has received the SETUP phase of a control request, and
1084 * needs to work out what to do next (and whether to pass it on to the
1085 * gadget driver).
1086 */
1087static void s3c_hsotg_process_control(struct dwc2_hsotg *hsotg,
1088 struct usb_ctrlrequest *ctrl)
1089{
1083 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1090 struct s3c_hsotg_ep *ep0 = hsotg->eps_out[0];
1084 int ret = 0;
1085 u32 dcfg;
1086
1091 int ret = 0;
1092 u32 dcfg;
1093
1087 ep0->sent_zlp = 0;
1088
1089 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1090 ctrl->bRequest, ctrl->bRequestType,
1091 ctrl->wValue, ctrl->wLength);
1092
1094 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1095 ctrl->bRequest, ctrl->bRequestType,
1096 ctrl->wValue, ctrl->wLength);
1097
1093 /*
1094 * record the direction of the request, for later use when enquing
1095 * packets onto EP0.
1096 */
1097
1098 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1099 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1100
1101 /*
1102 * if we've no data with this request, then the last part of the
1103 * transaction is going to implicitly be IN.
1104 */
1105 if (ctrl->wLength == 0)
1098 if (ctrl->wLength == 0) {
1106 ep0->dir_in = 1;
1099 ep0->dir_in = 1;
1100 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1101 } else if (ctrl->bRequestType & USB_DIR_IN) {
1102 ep0->dir_in = 1;
1103 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1104 } else {
1105 ep0->dir_in = 0;
1106 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1107 }
1107
1108 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1109 switch (ctrl->bRequest) {
1110 case USB_REQ_SET_ADDRESS:
1108
1109 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1110 switch (ctrl->bRequest) {
1111 case USB_REQ_SET_ADDRESS:
1112 hsotg->connected = 1;
1111 dcfg = readl(hsotg->regs + DCFG);
1112 dcfg &= ~DCFG_DEVADDR_MASK;
1113 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1114 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1115 writel(dcfg, hsotg->regs + DCFG);
1116
1117 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1118

--- 77 unchanged lines hidden (view full) ---

1196 req->buf = hsotg->ctrl_buff;
1197 req->complete = s3c_hsotg_complete_setup;
1198
1199 if (!list_empty(&hs_req->queue)) {
1200 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1201 return;
1202 }
1203
1113 dcfg = readl(hsotg->regs + DCFG);
1114 dcfg &= ~DCFG_DEVADDR_MASK;
1115 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1116 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1117 writel(dcfg, hsotg->regs + DCFG);
1118
1119 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1120

--- 77 unchanged lines hidden (view full) ---

1198 req->buf = hsotg->ctrl_buff;
1199 req->complete = s3c_hsotg_complete_setup;
1200
1201 if (!list_empty(&hs_req->queue)) {
1202 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1203 return;
1204 }
1205
1204 hsotg->eps[0].dir_in = 0;
1206 hsotg->eps_out[0]->dir_in = 0;
1207 hsotg->eps_out[0]->send_zlp = 0;
1208 hsotg->ep0_state = DWC2_EP0_SETUP;
1205
1209
1206 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1210 ret = s3c_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1207 if (ret < 0) {
1208 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1209 /*
1210 * Don't think there's much we can do other than watch the
1211 * driver fail.
1212 */
1213 }
1214}
1215
1211 if (ret < 0) {
1212 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1213 /*
1214 * Don't think there's much we can do other than watch the
1215 * driver fail.
1216 */
1217 }
1218}
1219
1220static void s3c_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1221 struct s3c_hsotg_ep *hs_ep)
1222{
1223 u32 ctrl;
1224 u8 index = hs_ep->index;
1225 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1226 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1227
1228 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n", index);
1229
1230 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1231 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1232 epsiz_reg);
1233
1234 ctrl = readl(hsotg->regs + epctl_reg);
1235 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1236 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1237 ctrl |= DXEPCTL_USBACTEP;
1238 writel(ctrl, hsotg->regs + epctl_reg);
1239}
1240
1216/**
1217 * s3c_hsotg_complete_request - complete a request given to us
1218 * @hsotg: The device state.
1219 * @hs_ep: The endpoint the request was on.
1220 * @hs_req: The request to complete.
1221 * @result: The result code (0 => Ok, otherwise errno)
1222 *
1223 * The given request has finished, so call the necessary completion

--- 64 unchanged lines hidden (view full) ---

1288 * @size: The size of data in the fifo, in bytes
1289 *
1290 * The FIFO status shows there is data to read from the FIFO for a given
1291 * endpoint, so sort out whether we need to read the data into a request
1292 * that has been made for that endpoint.
1293 */
1294static void s3c_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1295{
1241/**
1242 * s3c_hsotg_complete_request - complete a request given to us
1243 * @hsotg: The device state.
1244 * @hs_ep: The endpoint the request was on.
1245 * @hs_req: The request to complete.
1246 * @result: The result code (0 => Ok, otherwise errno)
1247 *
1248 * The given request has finished, so call the necessary completion

--- 64 unchanged lines hidden (view full) ---

1313 * @size: The size of data in the fifo, in bytes
1314 *
1315 * The FIFO status shows there is data to read from the FIFO for a given
1316 * endpoint, so sort out whether we need to read the data into a request
1317 * that has been made for that endpoint.
1318 */
1319static void s3c_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1320{
1296 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1321 struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1297 struct s3c_hsotg_req *hs_req = hs_ep->req;
1298 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1299 int to_read;
1300 int max_req;
1301 int read_ptr;
1302
1303
1304 if (!hs_req) {
1305 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1306 int ptr;
1307
1322 struct s3c_hsotg_req *hs_req = hs_ep->req;
1323 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1324 int to_read;
1325 int max_req;
1326 int read_ptr;
1327
1328
1329 if (!hs_req) {
1330 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1331 int ptr;
1332
1308 dev_warn(hsotg->dev,
1333 dev_dbg(hsotg->dev,
1309 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1310 __func__, size, ep_idx, epctl);
1311
1312 /* dump the data from the FIFO, we've nothing we can do */
1313 for (ptr = 0; ptr < size; ptr += 4)
1314 (void)readl(fifo);
1315
1316 return;

--- 23 unchanged lines hidden (view full) ---

1340 /*
1341 * note, we might over-write the buffer end by 3 bytes depending on
1342 * alignment of the data.
1343 */
1344 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1345}
1346
1347/**
1334 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1335 __func__, size, ep_idx, epctl);
1336
1337 /* dump the data from the FIFO, we've nothing we can do */
1338 for (ptr = 0; ptr < size; ptr += 4)
1339 (void)readl(fifo);
1340
1341 return;

--- 23 unchanged lines hidden (view full) ---

1365 /*
1366 * note, we might over-write the buffer end by 3 bytes depending on
1367 * alignment of the data.
1368 */
1369 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1370}
1371
1372/**
1348 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1373 * s3c_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1349 * @hsotg: The device instance
1374 * @hsotg: The device instance
1350 * @req: The request currently on this endpoint
1375 * @dir_in: If IN zlp
1351 *
1352 * Generate a zero-length IN packet request for terminating a SETUP
1353 * transaction.
1354 *
1355 * Note, since we don't write any data to the TxFIFO, then it is
1356 * currently believed that we do not need to wait for any space in
1357 * the TxFIFO.
1358 */
1376 *
1377 * Generate a zero-length IN packet request for terminating a SETUP
1378 * transaction.
1379 *
1380 * Note, since we don't write any data to the TxFIFO, then it is
1381 * currently believed that we do not need to wait for any space in
1382 * the TxFIFO.
1383 */
1359static void s3c_hsotg_send_zlp(struct dwc2_hsotg *hsotg,
1360 struct s3c_hsotg_req *req)
1384static void s3c_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
1361{
1385{
1362 u32 ctrl;
1386 /* eps_out[0] is used in both directions */
1387 hsotg->eps_out[0]->dir_in = dir_in;
1388 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
1363
1389
1364 if (!req) {
1365 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1366 return;
1367 }
1368
1369 if (req->req.length == 0) {
1370 hsotg->eps[0].sent_zlp = 1;
1371 s3c_hsotg_enqueue_setup(hsotg);
1372 return;
1373 }
1374
1375 hsotg->eps[0].dir_in = 1;
1376 hsotg->eps[0].sent_zlp = 1;
1377
1378 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1379
1380 /* issue a zero-sized packet to terminate this */
1381 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1382 DXEPTSIZ_XFERSIZE(0), hsotg->regs + DIEPTSIZ(0));
1383
1384 ctrl = readl(hsotg->regs + DIEPCTL0);
1385 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1386 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1387 ctrl |= DXEPCTL_USBACTEP;
1388 writel(ctrl, hsotg->regs + DIEPCTL0);
1390 s3c_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
1389}
1390
1391/**
1392 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1393 * @hsotg: The device instance
1394 * @epnum: The endpoint received from
1391}
1392
1393/**
1394 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1395 * @hsotg: The device instance
1396 * @epnum: The endpoint received from
1395 * @was_setup: Set if processing a SetupDone event.
1396 *
1397 * The RXFIFO has delivered an OutDone event, which means that the data
1398 * transfer for an OUT endpoint has been completed, either by a short
1399 * packet or by the finish of a transfer.
1400 */
1397 *
1398 * The RXFIFO has delivered an OutDone event, which means that the data
1399 * transfer for an OUT endpoint has been completed, either by a short
1400 * packet or by the finish of a transfer.
1401 */
1401static void s3c_hsotg_handle_outdone(struct dwc2_hsotg *hsotg,
1402 int epnum, bool was_setup)
1402static void s3c_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1403{
1404 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1403{
1404 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1405 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1405 struct s3c_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1406 struct s3c_hsotg_req *hs_req = hs_ep->req;
1407 struct usb_request *req = &hs_req->req;
1408 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1409 int result = 0;
1410
1411 if (!hs_req) {
1412 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1413 return;
1414 }
1415
1406 struct s3c_hsotg_req *hs_req = hs_ep->req;
1407 struct usb_request *req = &hs_req->req;
1408 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1409 int result = 0;
1410
1411 if (!hs_req) {
1412 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1413 return;
1414 }
1415
1416 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1417 dev_dbg(hsotg->dev, "zlp packet received\n");
1418 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1419 s3c_hsotg_enqueue_setup(hsotg);
1420 return;
1421 }
1422
1416 if (using_dma(hsotg)) {
1417 unsigned size_done;
1418
1419 /*
1420 * Calculate the size of the transfer by checking how much
1421 * is left in the endpoint size register and then working it
1422 * out from the amount we loaded for the transfer.
1423 *

--- 6 unchanged lines hidden (view full) ---

1430
1431 req->actual = size_done;
1432 }
1433
1434 /* if there is more request to do, schedule new transfer */
1435 if (req->actual < req->length && size_left == 0) {
1436 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1437 return;
1423 if (using_dma(hsotg)) {
1424 unsigned size_done;
1425
1426 /*
1427 * Calculate the size of the transfer by checking how much
1428 * is left in the endpoint size register and then working it
1429 * out from the amount we loaded for the transfer.
1430 *

--- 6 unchanged lines hidden (view full) ---

1437
1438 req->actual = size_done;
1439 }
1440
1441 /* if there is more request to do, schedule new transfer */
1442 if (req->actual < req->length && size_left == 0) {
1443 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1444 return;
1438 } else if (epnum == 0) {
1439 /*
1440 * After was_setup = 1 =>
1441 * set CNAK for non Setup requests
1442 */
1443 hsotg->setup = was_setup ? 0 : 1;
1444 }
1445
1446 if (req->actual < req->length && req->short_not_ok) {
1447 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1448 __func__, req->actual, req->length);
1449
1450 /*
1451 * todo - what should we return here? there's no one else
1452 * even bothering to check the status.
1453 */
1454 }
1455
1445 }
1446
1447 if (req->actual < req->length && req->short_not_ok) {
1448 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1449 __func__, req->actual, req->length);
1450
1451 /*
1452 * todo - what should we return here? there's no one else
1453 * even bothering to check the status.
1454 */
1455 }
1456
1456 if (epnum == 0) {
1457 /*
1458 * Condition req->complete != s3c_hsotg_complete_setup says:
1459 * send ZLP when we have an asynchronous request from gadget
1460 */
1461 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1462 s3c_hsotg_send_zlp(hsotg, hs_req);
1457 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1458 /* Move to STATUS IN */
1459 s3c_hsotg_ep0_zlp(hsotg, true);
1460 return;
1463 }
1464
1465 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1466}
1467
1468/**
1469 * s3c_hsotg_read_frameno - read current frame number
1470 * @hsotg: The device instance

--- 49 unchanged lines hidden (view full) ---

1520 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1521 break;
1522
1523 case GRXSTS_PKTSTS_OUTDONE:
1524 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1525 s3c_hsotg_read_frameno(hsotg));
1526
1527 if (!using_dma(hsotg))
1461 }
1462
1463 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1464}
1465
1466/**
1467 * s3c_hsotg_read_frameno - read current frame number
1468 * @hsotg: The device instance

--- 49 unchanged lines hidden (view full) ---

1518 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1519 break;
1520
1521 case GRXSTS_PKTSTS_OUTDONE:
1522 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1523 s3c_hsotg_read_frameno(hsotg));
1524
1525 if (!using_dma(hsotg))
1528 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1526 s3c_hsotg_handle_outdone(hsotg, epnum);
1529 break;
1530
1531 case GRXSTS_PKTSTS_SETUPDONE:
1532 dev_dbg(hsotg->dev,
1533 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1534 s3c_hsotg_read_frameno(hsotg),
1535 readl(hsotg->regs + DOEPCTL(0)));
1527 break;
1528
1529 case GRXSTS_PKTSTS_SETUPDONE:
1530 dev_dbg(hsotg->dev,
1531 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1532 s3c_hsotg_read_frameno(hsotg),
1533 readl(hsotg->regs + DOEPCTL(0)));
1536
1537 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1534 /*
1535 * Call s3c_hsotg_handle_outdone here if it was not called from
1536 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1537 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1538 */
1539 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1540 s3c_hsotg_handle_outdone(hsotg, epnum);
1538 break;
1539
1540 case GRXSTS_PKTSTS_OUTRX:
1541 s3c_hsotg_rx_data(hsotg, epnum, size);
1542 break;
1543
1544 case GRXSTS_PKTSTS_SETUPRX:
1545 dev_dbg(hsotg->dev,
1546 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1547 s3c_hsotg_read_frameno(hsotg),
1548 readl(hsotg->regs + DOEPCTL(0)));
1549
1541 break;
1542
1543 case GRXSTS_PKTSTS_OUTRX:
1544 s3c_hsotg_rx_data(hsotg, epnum, size);
1545 break;
1546
1547 case GRXSTS_PKTSTS_SETUPRX:
1548 dev_dbg(hsotg->dev,
1549 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1550 s3c_hsotg_read_frameno(hsotg),
1551 readl(hsotg->regs + DOEPCTL(0)));
1552
1553 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1554
1550 s3c_hsotg_rx_data(hsotg, epnum, size);
1551 break;
1552
1553 default:
1554 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1555 __func__, grxstsr);
1556
1557 s3c_hsotg_dump(hsotg);

--- 28 unchanged lines hidden (view full) ---

1586 * @hsotg: The driver state.
1587 * @ep: The index number of the endpoint
1588 * @mps: The maximum packet size in bytes
1589 *
1590 * Configure the maximum packet size for the given endpoint, updating
1591 * the hardware control registers to reflect this.
1592 */
1593static void s3c_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1555 s3c_hsotg_rx_data(hsotg, epnum, size);
1556 break;
1557
1558 default:
1559 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1560 __func__, grxstsr);
1561
1562 s3c_hsotg_dump(hsotg);

--- 28 unchanged lines hidden (view full) ---

1591 * @hsotg: The driver state.
1592 * @ep: The index number of the endpoint
1593 * @mps: The maximum packet size in bytes
1594 *
1595 * Configure the maximum packet size for the given endpoint, updating
1596 * the hardware control registers to reflect this.
1597 */
1598static void s3c_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1594 unsigned int ep, unsigned int mps)
1599 unsigned int ep, unsigned int mps, unsigned int dir_in)
1595{
1600{
1596 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1601 struct s3c_hsotg_ep *hs_ep;
1597 void __iomem *regs = hsotg->regs;
1598 u32 mpsval;
1599 u32 mcval;
1600 u32 reg;
1601
1602 void __iomem *regs = hsotg->regs;
1603 u32 mpsval;
1604 u32 mcval;
1605 u32 reg;
1606
1607 hs_ep = index_to_ep(hsotg, ep, dir_in);
1608 if (!hs_ep)
1609 return;
1610
1602 if (ep == 0) {
1603 /* EP0 is a special case */
1604 mpsval = s3c_hsotg_ep0_mps(mps);
1605 if (mpsval > 3)
1606 goto bad_mps;
1607 hs_ep->ep.maxpacket = mps;
1608 hs_ep->mc = 1;
1609 } else {
1610 mpsval = mps & DXEPCTL_MPS_MASK;
1611 if (mpsval > 1024)
1612 goto bad_mps;
1613 mcval = ((mps >> 11) & 0x3) + 1;
1614 hs_ep->mc = mcval;
1615 if (mcval > 3)
1616 goto bad_mps;
1617 hs_ep->ep.maxpacket = mpsval;
1618 }
1619
1611 if (ep == 0) {
1612 /* EP0 is a special case */
1613 mpsval = s3c_hsotg_ep0_mps(mps);
1614 if (mpsval > 3)
1615 goto bad_mps;
1616 hs_ep->ep.maxpacket = mps;
1617 hs_ep->mc = 1;
1618 } else {
1619 mpsval = mps & DXEPCTL_MPS_MASK;
1620 if (mpsval > 1024)
1621 goto bad_mps;
1622 mcval = ((mps >> 11) & 0x3) + 1;
1623 hs_ep->mc = mcval;
1624 if (mcval > 3)
1625 goto bad_mps;
1626 hs_ep->ep.maxpacket = mpsval;
1627 }
1628
1620 /*
1621 * update both the in and out endpoint controldir_ registers, even
1622 * if one of the directions may not be in use.
1623 */
1624
1625 reg = readl(regs + DIEPCTL(ep));
1626 reg &= ~DXEPCTL_MPS_MASK;
1627 reg |= mpsval;
1628 writel(reg, regs + DIEPCTL(ep));
1629
1630 if (ep) {
1629 if (dir_in) {
1630 reg = readl(regs + DIEPCTL(ep));
1631 reg &= ~DXEPCTL_MPS_MASK;
1632 reg |= mpsval;
1633 writel(reg, regs + DIEPCTL(ep));
1634 } else {
1631 reg = readl(regs + DOEPCTL(ep));
1632 reg &= ~DXEPCTL_MPS_MASK;
1633 reg |= mpsval;
1634 writel(reg, regs + DOEPCTL(ep));
1635 }
1636
1637 return;
1638

--- 83 unchanged lines hidden (view full) ---

1722 int size_left, size_done;
1723
1724 if (!hs_req) {
1725 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1726 return;
1727 }
1728
1729 /* Finish ZLP handling for IN EP0 transactions */
1635 reg = readl(regs + DOEPCTL(ep));
1636 reg &= ~DXEPCTL_MPS_MASK;
1637 reg |= mpsval;
1638 writel(reg, regs + DOEPCTL(ep));
1639 }
1640
1641 return;
1642

--- 83 unchanged lines hidden (view full) ---

1726 int size_left, size_done;
1727
1728 if (!hs_req) {
1729 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1730 return;
1731 }
1732
1733 /* Finish ZLP handling for IN EP0 transactions */
1730 if (hsotg->eps[0].sent_zlp) {
1731 dev_dbg(hsotg->dev, "zlp packet received\n");
1734 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1735 dev_dbg(hsotg->dev, "zlp packet sent\n");
1732 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1736 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1737 s3c_hsotg_enqueue_setup(hsotg);
1733 return;
1734 }
1735
1736 /*
1737 * Calculate the size of the transfer by checking how much is left
1738 * in the endpoint size register and then working it out from
1739 * the amount we loaded for the transfer.
1740 *

--- 10 unchanged lines hidden (view full) ---

1751 if (hs_req->req.actual != size_done)
1752 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1753 __func__, hs_req->req.actual, size_done);
1754
1755 hs_req->req.actual = size_done;
1756 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1757 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1758
1738 return;
1739 }
1740
1741 /*
1742 * Calculate the size of the transfer by checking how much is left
1743 * in the endpoint size register and then working it out from
1744 * the amount we loaded for the transfer.
1745 *

--- 10 unchanged lines hidden (view full) ---

1756 if (hs_req->req.actual != size_done)
1757 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1758 __func__, hs_req->req.actual, size_done);
1759
1760 hs_req->req.actual = size_done;
1761 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1762 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1763
1759 /*
1760 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1761 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1762 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1763 * inform the host that no more data is available.
1764 * The state of req.zero member is checked to be sure that the value to
1765 * send is smaller than wValue expected from host.
1766 * Check req.length to NOT send another ZLP when the current one is
1767 * under completion (the one for which this completion has been called).
1768 */
1769 if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero &&
1770 hs_req->req.length == hs_req->req.actual &&
1771 !(hs_req->req.length % hs_ep->ep.maxpacket)) {
1764 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1765 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1766 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1767 return;
1768 }
1772
1769
1773 dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n");
1774 s3c_hsotg_send_zlp(hsotg, hs_req);
1770 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
1771 if (hs_ep->send_zlp) {
1772 s3c_hsotg_program_zlp(hsotg, hs_ep);
1773 hs_ep->send_zlp = 0;
1774 /* transfer will be completed on next complete interrupt */
1775 return;
1776 }
1775
1777
1778 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
1779 /* Move to STATUS OUT */
1780 s3c_hsotg_ep0_zlp(hsotg, false);
1776 return;
1777 }
1778
1781 return;
1782 }
1783
1779 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1780 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1781 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1782 } else
1783 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1784 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1784}
1785
1786/**
1787 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1788 * @hsotg: The driver state
1789 * @idx: The index for the endpoint (0..15)
1790 * @dir_in: Set if this is an IN endpoint
1791 *
1792 * Process and clear any interrupt pending for an individual endpoint
1793 */
1794static void s3c_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
1795 int dir_in)
1796{
1785}
1786
1787/**
1788 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1789 * @hsotg: The driver state
1790 * @idx: The index for the endpoint (0..15)
1791 * @dir_in: Set if this is an IN endpoint
1792 *
1793 * Process and clear any interrupt pending for an individual endpoint
1794 */
1795static void s3c_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
1796 int dir_in)
1797{
1797 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1798 struct s3c_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
1798 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1799 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1800 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1801 u32 ints;
1802 u32 ctrl;
1803
1804 ints = readl(hsotg->regs + epint_reg);
1805 ctrl = readl(hsotg->regs + epctl_reg);
1806
1807 /* Clear endpoint interrupts */
1808 writel(ints, hsotg->regs + epint_reg);
1809
1799 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1800 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1801 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1802 u32 ints;
1803 u32 ctrl;
1804
1805 ints = readl(hsotg->regs + epint_reg);
1806 ctrl = readl(hsotg->regs + epctl_reg);
1807
1808 /* Clear endpoint interrupts */
1809 writel(ints, hsotg->regs + epint_reg);
1810
1811 if (!hs_ep) {
1812 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
1813 __func__, idx, dir_in ? "in" : "out");
1814 return;
1815 }
1816
1810 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1811 __func__, idx, dir_in ? "in" : "out", ints);
1812
1817 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1818 __func__, idx, dir_in ? "in" : "out", ints);
1819
1820 /* Don't process XferCompl interrupt if it is a setup packet */
1821 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
1822 ints &= ~DXEPINT_XFERCOMPL;
1823
1813 if (ints & DXEPINT_XFERCOMPL) {
1814 if (hs_ep->isochronous && hs_ep->interval == 1) {
1815 if (ctrl & DXEPCTL_EOFRNUM)
1816 ctrl |= DXEPCTL_SETEVENFR;
1817 else
1818 ctrl |= DXEPCTL_SETODDFR;
1819 writel(ctrl, hsotg->regs + epctl_reg);
1820 }

--- 13 unchanged lines hidden (view full) ---

1834 if (idx == 0 && !hs_ep->req)
1835 s3c_hsotg_enqueue_setup(hsotg);
1836 } else if (using_dma(hsotg)) {
1837 /*
1838 * We're using DMA, we need to fire an OutDone here
1839 * as we ignore the RXFIFO.
1840 */
1841
1824 if (ints & DXEPINT_XFERCOMPL) {
1825 if (hs_ep->isochronous && hs_ep->interval == 1) {
1826 if (ctrl & DXEPCTL_EOFRNUM)
1827 ctrl |= DXEPCTL_SETEVENFR;
1828 else
1829 ctrl |= DXEPCTL_SETODDFR;
1830 writel(ctrl, hsotg->regs + epctl_reg);
1831 }

--- 13 unchanged lines hidden (view full) ---

1845 if (idx == 0 && !hs_ep->req)
1846 s3c_hsotg_enqueue_setup(hsotg);
1847 } else if (using_dma(hsotg)) {
1848 /*
1849 * We're using DMA, we need to fire an OutDone here
1850 * as we ignore the RXFIFO.
1851 */
1852
1842 s3c_hsotg_handle_outdone(hsotg, idx, false);
1853 s3c_hsotg_handle_outdone(hsotg, idx);
1843 }
1844 }
1845
1846 if (ints & DXEPINT_EPDISBLD) {
1847 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1848
1849 if (dir_in) {
1850 int epctl = readl(hsotg->regs + epctl_reg);

--- 22 unchanged lines hidden (view full) ---

1873 * setup packet. In non-DMA mode we'd get this
1874 * from the RXFIFO, instead we need to process
1875 * the setup here.
1876 */
1877
1878 if (dir_in)
1879 WARN_ON_ONCE(1);
1880 else
1854 }
1855 }
1856
1857 if (ints & DXEPINT_EPDISBLD) {
1858 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1859
1860 if (dir_in) {
1861 int epctl = readl(hsotg->regs + epctl_reg);

--- 22 unchanged lines hidden (view full) ---

1884 * setup packet. In non-DMA mode we'd get this
1885 * from the RXFIFO, instead we need to process
1886 * the setup here.
1887 */
1888
1889 if (dir_in)
1890 WARN_ON_ONCE(1);
1891 else
1881 s3c_hsotg_handle_outdone(hsotg, 0, true);
1892 s3c_hsotg_handle_outdone(hsotg, 0);
1882 }
1883 }
1884
1885 if (ints & DXEPINT_BACK2BACKSETUP)
1886 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1887
1888 if (dir_in && !hs_ep->isochronous) {
1889 /* not sure if this is important, but we'll clear it anyway */

--- 74 unchanged lines hidden (view full) ---

1964
1965 /*
1966 * we should now know the maximum packet size for an
1967 * endpoint, so set the endpoints to a default value.
1968 */
1969
1970 if (ep0_mps) {
1971 int i;
1893 }
1894 }
1895
1896 if (ints & DXEPINT_BACK2BACKSETUP)
1897 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1898
1899 if (dir_in && !hs_ep->isochronous) {
1900 /* not sure if this is important, but we'll clear it anyway */

--- 74 unchanged lines hidden (view full) ---

1975
1976 /*
1977 * we should now know the maximum packet size for an
1978 * endpoint, so set the endpoints to a default value.
1979 */
1980
1981 if (ep0_mps) {
1982 int i;
1972 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1973 for (i = 1; i < hsotg->num_of_eps; i++)
1974 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1983 /* Initialize ep0 for both in and out directions */
1984 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
1985 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
1986 for (i = 1; i < hsotg->num_of_eps; i++) {
1987 if (hsotg->eps_in[i])
1988 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
1989 if (hsotg->eps_out[i])
1990 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
1991 }
1975 }
1976
1977 /* ensure after enumeration our EP0 is active */
1978
1979 s3c_hsotg_enqueue_setup(hsotg);
1980
1981 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1982 readl(hsotg->regs + DIEPCTL0),
1983 readl(hsotg->regs + DOEPCTL0));
1984}
1985
1986/**
1987 * kill_all_requests - remove all requests from the endpoint's queue
1988 * @hsotg: The device state.
1989 * @ep: The endpoint the requests may be on.
1990 * @result: The result code to use.
1992 }
1993
1994 /* ensure after enumeration our EP0 is active */
1995
1996 s3c_hsotg_enqueue_setup(hsotg);
1997
1998 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1999 readl(hsotg->regs + DIEPCTL0),
2000 readl(hsotg->regs + DOEPCTL0));
2001}
2002
2003/**
2004 * kill_all_requests - remove all requests from the endpoint's queue
2005 * @hsotg: The device state.
2006 * @ep: The endpoint the requests may be on.
2007 * @result: The result code to use.
1991 * @force: Force removal of any current requests
1992 *
1993 * Go through the requests on the given endpoint and mark them
1994 * completed with the given result code.
1995 */
1996static void kill_all_requests(struct dwc2_hsotg *hsotg,
1997 struct s3c_hsotg_ep *ep,
2008 *
2009 * Go through the requests on the given endpoint and mark them
2010 * completed with the given result code.
2011 */
2012static void kill_all_requests(struct dwc2_hsotg *hsotg,
2013 struct s3c_hsotg_ep *ep,
1998 int result, bool force)
2014 int result)
1999{
2000 struct s3c_hsotg_req *req, *treq;
2001 unsigned size;
2002
2015{
2016 struct s3c_hsotg_req *req, *treq;
2017 unsigned size;
2018
2003 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2004 /*
2005 * currently, we can't do much about an already
2006 * running request on an in endpoint
2007 */
2019 ep->req = NULL;
2008
2020
2009 if (ep->req == req && ep->dir_in && !force)
2010 continue;
2011
2021 list_for_each_entry_safe(req, treq, &ep->queue, queue)
2012 s3c_hsotg_complete_request(hsotg, ep, req,
2013 result);
2022 s3c_hsotg_complete_request(hsotg, ep, req,
2023 result);
2014 }
2024
2015 if (!hsotg->dedicated_fifos)
2016 return;
2017 size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2018 if (size < ep->fifo_size)
2019 s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2020}
2021
2022/**

--- 7 unchanged lines hidden (view full) ---

2030void s3c_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2031{
2032 unsigned ep;
2033
2034 if (!hsotg->connected)
2035 return;
2036
2037 hsotg->connected = 0;
2025 if (!hsotg->dedicated_fifos)
2026 return;
2027 size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2028 if (size < ep->fifo_size)
2029 s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2030}
2031
2032/**

--- 7 unchanged lines hidden (view full) ---

2040void s3c_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2041{
2042 unsigned ep;
2043
2044 if (!hsotg->connected)
2045 return;
2046
2047 hsotg->connected = 0;
2038 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2039 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2040
2048
2049 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2050 if (hsotg->eps_in[ep])
2051 kill_all_requests(hsotg, hsotg->eps_in[ep],
2052 -ESHUTDOWN);
2053 if (hsotg->eps_out[ep])
2054 kill_all_requests(hsotg, hsotg->eps_out[ep],
2055 -ESHUTDOWN);
2056 }
2057
2041 call_gadget(hsotg, disconnect);
2042}
2043EXPORT_SYMBOL_GPL(s3c_hsotg_disconnect);
2044
2045/**
2046 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2047 * @hsotg: The device state:
2048 * @periodic: True if this is a periodic FIFO interrupt
2049 */
2050static void s3c_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2051{
2052 struct s3c_hsotg_ep *ep;
2053 int epno, ret;
2054
2055 /* look through for any more data to transmit */
2058 call_gadget(hsotg, disconnect);
2059}
2060EXPORT_SYMBOL_GPL(s3c_hsotg_disconnect);
2061
2062/**
2063 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2064 * @hsotg: The device state:
2065 * @periodic: True if this is a periodic FIFO interrupt
2066 */
2067static void s3c_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2068{
2069 struct s3c_hsotg_ep *ep;
2070 int epno, ret;
2071
2072 /* look through for any more data to transmit */
2056
2057 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2073 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2058 ep = &hsotg->eps[epno];
2074 ep = index_to_ep(hsotg, epno, 1);
2059
2075
2076 if (!ep)
2077 continue;
2078
2060 if (!ep->dir_in)
2061 continue;
2062
2063 if ((periodic && !ep->periodic) ||
2064 (!periodic && ep->periodic))
2065 continue;
2066
2067 ret = s3c_hsotg_trytx(hsotg, ep);

--- 90 unchanged lines hidden (view full) ---

2158 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2159 GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
2160 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2161 GINTSTS_USBSUSP | GINTSTS_WKUPINT,
2162 hsotg->regs + GINTMSK);
2163
2164 if (using_dma(hsotg))
2165 writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2079 if (!ep->dir_in)
2080 continue;
2081
2082 if ((periodic && !ep->periodic) ||
2083 (!periodic && ep->periodic))
2084 continue;
2085
2086 ret = s3c_hsotg_trytx(hsotg, ep);

--- 90 unchanged lines hidden (view full) ---

2177 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2178 GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
2179 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2180 GINTSTS_USBSUSP | GINTSTS_WKUPINT,
2181 hsotg->regs + GINTMSK);
2182
2183 if (using_dma(hsotg))
2184 writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2166 GAHBCFG_HBSTLEN_INCR4,
2185 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2167 hsotg->regs + GAHBCFG);
2168 else
2169 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
2170 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2171 GAHBCFG_GLBL_INTR_EN,
2172 hsotg->regs + GAHBCFG);
2173
2174 /*
2175 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2176 * when we have no data to transfer. Otherwise we get being flooded by
2177 * interrupts.
2178 */
2179
2186 hsotg->regs + GAHBCFG);
2187 else
2188 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
2189 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2190 GAHBCFG_GLBL_INTR_EN,
2191 hsotg->regs + GAHBCFG);
2192
2193 /*
2194 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2195 * when we have no data to transfer. Otherwise we get being flooded by
2196 * interrupts.
2197 */
2198
2180 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY |
2181 DIEPMSK_INTKNTXFEMPMSK : 0) |
2199 writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
2200 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
2182 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2183 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2184 DIEPMSK_INTKNEPMISMSK,
2185 hsotg->regs + DIEPMSK);
2186
2187 /*
2188 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2189 * DMA mode we may need this.

--- 35 unchanged lines hidden (view full) ---

2225 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2226 * writing to the EPCTL register..
2227 */
2228
2229 /* set to read 1 8byte packet */
2230 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2231 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2232
2201 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2202 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2203 DIEPMSK_INTKNEPMISMSK,
2204 hsotg->regs + DIEPMSK);
2205
2206 /*
2207 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2208 * DMA mode we may need this.

--- 35 unchanged lines hidden (view full) ---

2244 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2245 * writing to the EPCTL register..
2246 */
2247
2248 /* set to read 1 8byte packet */
2249 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2250 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2251
2233 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2252 writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2234 DXEPCTL_CNAK | DXEPCTL_EPENA |
2235 DXEPCTL_USBACTEP,
2236 hsotg->regs + DOEPCTL0);
2237
2238 /* enable, but don't activate EP0in */
2253 DXEPCTL_CNAK | DXEPCTL_EPENA |
2254 DXEPCTL_USBACTEP,
2255 hsotg->regs + DOEPCTL0);
2256
2257 /* enable, but don't activate EP0in */
2239 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2258 writel(s3c_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2240 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2241
2242 s3c_hsotg_enqueue_setup(hsotg);
2243
2244 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2245 readl(hsotg->regs + DIEPCTL0),
2246 readl(hsotg->regs + DOEPCTL0));
2247

--- 40 unchanged lines hidden (view full) ---

2288 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2289
2290 gintsts &= gintmsk;
2291
2292 if (gintsts & GINTSTS_ENUMDONE) {
2293 writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2294
2295 s3c_hsotg_irq_enumdone(hsotg);
2259 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2260
2261 s3c_hsotg_enqueue_setup(hsotg);
2262
2263 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2264 readl(hsotg->regs + DIEPCTL0),
2265 readl(hsotg->regs + DOEPCTL0));
2266

--- 40 unchanged lines hidden (view full) ---

2307 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2308
2309 gintsts &= gintmsk;
2310
2311 if (gintsts & GINTSTS_ENUMDONE) {
2312 writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2313
2314 s3c_hsotg_irq_enumdone(hsotg);
2296 hsotg->connected = 1;
2297 }
2298
2299 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2300 u32 daint = readl(hsotg->regs + DAINT);
2301 u32 daintmsk = readl(hsotg->regs + DAINTMSK);
2302 u32 daint_out, daint_in;
2303 int ep;
2304
2305 daint &= daintmsk;
2306 daint_out = daint >> DAINT_OUTEP_SHIFT;
2307 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2308
2309 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2310
2315 }
2316
2317 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2318 u32 daint = readl(hsotg->regs + DAINT);
2319 u32 daintmsk = readl(hsotg->regs + DAINTMSK);
2320 u32 daint_out, daint_in;
2321 int ep;
2322
2323 daint &= daintmsk;
2324 daint_out = daint >> DAINT_OUTEP_SHIFT;
2325 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2326
2327 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2328
2311 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2329 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2330 ep++, daint_out >>= 1) {
2312 if (daint_out & 1)
2313 s3c_hsotg_epint(hsotg, ep, 0);
2314 }
2315
2331 if (daint_out & 1)
2332 s3c_hsotg_epint(hsotg, ep, 0);
2333 }
2334
2316 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2335 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2336 ep++, daint_in >>= 1) {
2317 if (daint_in & 1)
2318 s3c_hsotg_epint(hsotg, ep, 1);
2319 }
2320 }
2321
2322 if (gintsts & GINTSTS_USBRST) {
2323
2324 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2325
2326 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2327 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2328 readl(hsotg->regs + GNPTXSTS));
2329
2330 writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2331
2337 if (daint_in & 1)
2338 s3c_hsotg_epint(hsotg, ep, 1);
2339 }
2340 }
2341
2342 if (gintsts & GINTSTS_USBRST) {
2343
2344 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2345
2346 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2347 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2348 readl(hsotg->regs + GNPTXSTS));
2349
2350 writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2351
2352 /* Report disconnection if it is not already done. */
2353 s3c_hsotg_disconnect(hsotg);
2354
2332 if (usb_status & GOTGCTL_BSESVLD) {
2333 if (time_after(jiffies, hsotg->last_rst +
2334 msecs_to_jiffies(200))) {
2335
2355 if (usb_status & GOTGCTL_BSESVLD) {
2356 if (time_after(jiffies, hsotg->last_rst +
2357 msecs_to_jiffies(200))) {
2358
2336 kill_all_requests(hsotg, &hsotg->eps[0],
2337 -ECONNRESET, true);
2359 kill_all_requests(hsotg, hsotg->eps_out[0],
2360 -ECONNRESET);
2338
2339 s3c_hsotg_core_init_disconnected(hsotg);
2340 s3c_hsotg_core_connect(hsotg);
2341 }
2342 }
2343 }
2344
2345 /* check both FIFOs */

--- 78 unchanged lines hidden (view full) ---

2424 * This is called from the USB gadget code's usb_ep_enable().
2425 */
2426static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2427 const struct usb_endpoint_descriptor *desc)
2428{
2429 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2430 struct dwc2_hsotg *hsotg = hs_ep->parent;
2431 unsigned long flags;
2361
2362 s3c_hsotg_core_init_disconnected(hsotg);
2363 s3c_hsotg_core_connect(hsotg);
2364 }
2365 }
2366 }
2367
2368 /* check both FIFOs */

--- 78 unchanged lines hidden (view full) ---

2447 * This is called from the USB gadget code's usb_ep_enable().
2448 */
2449static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2450 const struct usb_endpoint_descriptor *desc)
2451{
2452 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2453 struct dwc2_hsotg *hsotg = hs_ep->parent;
2454 unsigned long flags;
2432 int index = hs_ep->index;
2455 unsigned int index = hs_ep->index;
2433 u32 epctrl_reg;
2434 u32 epctrl;
2435 u32 mps;
2456 u32 epctrl_reg;
2457 u32 epctrl;
2458 u32 mps;
2436 int dir_in;
2437 int i, val, size;
2459 unsigned int dir_in;
2460 unsigned int i, val, size;
2438 int ret = 0;
2439
2440 dev_dbg(hsotg->dev,
2441 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2442 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2443 desc->wMaxPacketSize, desc->bInterval);
2444
2445 /* not to be called for EP0 */

--- 31 unchanged lines hidden (view full) ---

2477 * do something with data that we've yet got a request to process
2478 * since the RXFIFO will take data for an endpoint even if the
2479 * size register hasn't been set.
2480 */
2481
2482 epctrl |= DXEPCTL_SNAK;
2483
2484 /* update the endpoint state */
2461 int ret = 0;
2462
2463 dev_dbg(hsotg->dev,
2464 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2465 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2466 desc->wMaxPacketSize, desc->bInterval);
2467
2468 /* not to be called for EP0 */

--- 31 unchanged lines hidden (view full) ---

2500 * do something with data that we've yet got a request to process
2501 * since the RXFIFO will take data for an endpoint even if the
2502 * size register hasn't been set.
2503 */
2504
2505 epctrl |= DXEPCTL_SNAK;
2506
2507 /* update the endpoint state */
2485 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps);
2508 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
2486
2487 /* default, set to non-periodic */
2488 hs_ep->isochronous = 0;
2489 hs_ep->periodic = 0;
2490 hs_ep->halted = 0;
2491 hs_ep->interval = desc->bInterval;
2492
2493 if (hs_ep->interval > 1 && hs_ep->mc > 1)

--- 19 unchanged lines hidden (view full) ---

2513 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2514 break;
2515
2516 case USB_ENDPOINT_XFER_CONTROL:
2517 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2518 break;
2519 }
2520
2509
2510 /* default, set to non-periodic */
2511 hs_ep->isochronous = 0;
2512 hs_ep->periodic = 0;
2513 hs_ep->halted = 0;
2514 hs_ep->interval = desc->bInterval;
2515
2516 if (hs_ep->interval > 1 && hs_ep->mc > 1)

--- 19 unchanged lines hidden (view full) ---

2536 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2537 break;
2538
2539 case USB_ENDPOINT_XFER_CONTROL:
2540 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2541 break;
2542 }
2543
2544 /* If fifo is already allocated for this ep */
2545 if (hs_ep->fifo_index) {
2546 size = hs_ep->ep.maxpacket * hs_ep->mc;
2547 /* If bigger fifo is required deallocate current one */
2548 if (size > hs_ep->fifo_size) {
2549 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
2550 hs_ep->fifo_index = 0;
2551 hs_ep->fifo_size = 0;
2552 }
2553 }
2554
2521 /*
2522 * if the hardware has dedicated fifos, we must give each IN EP
2523 * a unique tx-fifo even if it is non-periodic.
2524 */
2555 /*
2556 * if the hardware has dedicated fifos, we must give each IN EP
2557 * a unique tx-fifo even if it is non-periodic.
2558 */
2525 if (dir_in && hsotg->dedicated_fifos) {
2559 if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) {
2560 u32 fifo_index = 0;
2561 u32 fifo_size = UINT_MAX;
2526 size = hs_ep->ep.maxpacket*hs_ep->mc;
2562 size = hs_ep->ep.maxpacket*hs_ep->mc;
2527 for (i = 1; i <= 8; ++i) {
2563 for (i = 1; i < hsotg->num_of_eps; ++i) {
2528 if (hsotg->fifo_map & (1<<i))
2529 continue;
2530 val = readl(hsotg->regs + DPTXFSIZN(i));
2531 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2532 if (val < size)
2533 continue;
2564 if (hsotg->fifo_map & (1<<i))
2565 continue;
2566 val = readl(hsotg->regs + DPTXFSIZN(i));
2567 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2568 if (val < size)
2569 continue;
2534 hsotg->fifo_map |= 1<<i;
2535
2536 epctrl |= DXEPCTL_TXFNUM(i);
2537 hs_ep->fifo_index = i;
2538 hs_ep->fifo_size = val;
2539 break;
2570 /* Search for smallest acceptable fifo */
2571 if (val < fifo_size) {
2572 fifo_size = val;
2573 fifo_index = i;
2574 }
2540 }
2575 }
2541 if (i == 8) {
2576 if (!fifo_index) {
2577 dev_err(hsotg->dev,
2578 "%s: No suitable fifo found\n", __func__);
2542 ret = -ENOMEM;
2543 goto error;
2544 }
2579 ret = -ENOMEM;
2580 goto error;
2581 }
2582 hsotg->fifo_map |= 1 << fifo_index;
2583 epctrl |= DXEPCTL_TXFNUM(fifo_index);
2584 hs_ep->fifo_index = fifo_index;
2585 hs_ep->fifo_size = fifo_size;
2545 }
2546
2547 /* for non control endpoints, set PID to D0 */
2548 if (index)
2549 epctrl |= DXEPCTL_SETD0PID;
2550
2551 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2552 __func__, epctrl);

--- 21 unchanged lines hidden (view full) ---

2574 int dir_in = hs_ep->dir_in;
2575 int index = hs_ep->index;
2576 unsigned long flags;
2577 u32 epctrl_reg;
2578 u32 ctrl;
2579
2580 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2581
2586 }
2587
2588 /* for non control endpoints, set PID to D0 */
2589 if (index)
2590 epctrl |= DXEPCTL_SETD0PID;
2591
2592 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2593 __func__, epctrl);

--- 21 unchanged lines hidden (view full) ---

2615 int dir_in = hs_ep->dir_in;
2616 int index = hs_ep->index;
2617 unsigned long flags;
2618 u32 epctrl_reg;
2619 u32 ctrl;
2620
2621 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2622
2582 if (ep == &hsotg->eps[0].ep) {
2623 if (ep == &hsotg->eps_out[0]->ep) {
2583 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2584 return -EINVAL;
2585 }
2586
2587 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2588
2589 spin_lock_irqsave(&hsotg->lock, flags);
2624 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2625 return -EINVAL;
2626 }
2627
2628 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2629
2630 spin_lock_irqsave(&hsotg->lock, flags);
2590 /* terminate all requests with shutdown */
2591 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, force);
2592
2593 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2594 hs_ep->fifo_index = 0;
2595 hs_ep->fifo_size = 0;
2596
2597 ctrl = readl(hsotg->regs + epctrl_reg);
2598 ctrl &= ~DXEPCTL_EPENA;
2599 ctrl &= ~DXEPCTL_USBACTEP;
2600 ctrl |= DXEPCTL_SNAK;
2601
2602 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2603 writel(ctrl, hsotg->regs + epctrl_reg);
2604
2605 /* disable endpoint interrupts */
2606 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2607
2631
2632 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2633 hs_ep->fifo_index = 0;
2634 hs_ep->fifo_size = 0;
2635
2636 ctrl = readl(hsotg->regs + epctrl_reg);
2637 ctrl &= ~DXEPCTL_EPENA;
2638 ctrl &= ~DXEPCTL_USBACTEP;
2639 ctrl |= DXEPCTL_SNAK;
2640
2641 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2642 writel(ctrl, hsotg->regs + epctrl_reg);
2643
2644 /* disable endpoint interrupts */
2645 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2646
2647 /* terminate all requests with shutdown */
2648 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
2649
2608 spin_unlock_irqrestore(&hsotg->lock, flags);
2609 return 0;
2610}
2611
2612static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2613{
2614 return s3c_hsotg_ep_disable_force(ep, false);
2615}

--- 61 unchanged lines hidden (view full) ---

2677 if (value)
2678 s3c_hsotg_stall_ep0(hs);
2679 else
2680 dev_warn(hs->dev,
2681 "%s: can't clear halt on ep0\n", __func__);
2682 return 0;
2683 }
2684
2650 spin_unlock_irqrestore(&hsotg->lock, flags);
2651 return 0;
2652}
2653
2654static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2655{
2656 return s3c_hsotg_ep_disable_force(ep, false);
2657}

--- 61 unchanged lines hidden (view full) ---

2719 if (value)
2720 s3c_hsotg_stall_ep0(hs);
2721 else
2722 dev_warn(hs->dev,
2723 "%s: can't clear halt on ep0\n", __func__);
2724 return 0;
2725 }
2726
2685 /* write both IN and OUT control registers */
2727 if (hs_ep->dir_in) {
2728 epreg = DIEPCTL(index);
2729 epctl = readl(hs->regs + epreg);
2686
2730
2687 epreg = DIEPCTL(index);
2688 epctl = readl(hs->regs + epreg);
2689
2690 if (value) {
2691 epctl |= DXEPCTL_STALL + DXEPCTL_SNAK;
2692 if (epctl & DXEPCTL_EPENA)
2693 epctl |= DXEPCTL_EPDIS;
2731 if (value) {
2732 epctl |= DXEPCTL_STALL + DXEPCTL_SNAK;
2733 if (epctl & DXEPCTL_EPENA)
2734 epctl |= DXEPCTL_EPDIS;
2735 } else {
2736 epctl &= ~DXEPCTL_STALL;
2737 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2738 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2739 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2740 epctl |= DXEPCTL_SETD0PID;
2741 }
2742 writel(epctl, hs->regs + epreg);
2694 } else {
2743 } else {
2695 epctl &= ~DXEPCTL_STALL;
2696 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2697 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2698 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2699 epctl |= DXEPCTL_SETD0PID;
2700 }
2701
2744
2702 writel(epctl, hs->regs + epreg);
2745 epreg = DOEPCTL(index);
2746 epctl = readl(hs->regs + epreg);
2703
2747
2704 epreg = DOEPCTL(index);
2705 epctl = readl(hs->regs + epreg);
2706
2707 if (value)
2708 epctl |= DXEPCTL_STALL;
2709 else {
2710 epctl &= ~DXEPCTL_STALL;
2711 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2712 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2713 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2714 epctl |= DXEPCTL_SETD0PID;
2748 if (value)
2749 epctl |= DXEPCTL_STALL;
2750 else {
2751 epctl &= ~DXEPCTL_STALL;
2752 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2753 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2754 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2755 epctl |= DXEPCTL_SETD0PID;
2756 }
2757 writel(epctl, hs->regs + epreg);
2715 }
2716
2758 }
2759
2717 writel(epctl, hs->regs + epreg);
2718
2719 hs_ep->halted = value;
2720
2721 return 0;
2722}
2723
2724/**
2725 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2726 * @ep: The endpoint to set halt.

--- 102 unchanged lines hidden (view full) ---

2829 readl(hsotg->regs + GNPTXFSIZ));
2830
2831 s3c_hsotg_init_fifo(hsotg);
2832
2833 /* set the PLL on, remove the HNP/SRP and set the PHY */
2834 writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10),
2835 hsotg->regs + GUSBCFG);
2836
2760 hs_ep->halted = value;
2761
2762 return 0;
2763}
2764
2765/**
2766 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2767 * @ep: The endpoint to set halt.

--- 102 unchanged lines hidden (view full) ---

2870 readl(hsotg->regs + GNPTXFSIZ));
2871
2872 s3c_hsotg_init_fifo(hsotg);
2873
2874 /* set the PLL on, remove the HNP/SRP and set the PHY */
2875 writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10),
2876 hsotg->regs + GUSBCFG);
2877
2837 writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0,
2838 hsotg->regs + GAHBCFG);
2878 if (using_dma(hsotg))
2879 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
2839}
2840
2841/**
2842 * s3c_hsotg_udc_start - prepare the udc for work
2843 * @gadget: The usb gadget state
2844 * @driver: The usb gadget driver
2845 *
2846 * Perform initialization to prepare udc device and driver

--- 37 unchanged lines hidden (view full) ---

2884 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
2885 hsotg->supplies);
2886 if (ret) {
2887 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
2888 goto err;
2889 }
2890
2891 s3c_hsotg_phy_enable(hsotg);
2880}
2881
2882/**
2883 * s3c_hsotg_udc_start - prepare the udc for work
2884 * @gadget: The usb gadget state
2885 * @driver: The usb gadget driver
2886 *
2887 * Perform initialization to prepare udc device and driver

--- 37 unchanged lines hidden (view full) ---

2925 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
2926 hsotg->supplies);
2927 if (ret) {
2928 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
2929 goto err;
2930 }
2931
2932 s3c_hsotg_phy_enable(hsotg);
2933 if (!IS_ERR_OR_NULL(hsotg->uphy))
2934 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
2892
2893 spin_lock_irqsave(&hsotg->lock, flags);
2894 s3c_hsotg_init(hsotg);
2895 s3c_hsotg_core_init_disconnected(hsotg);
2896 hsotg->enabled = 0;
2897 spin_unlock_irqrestore(&hsotg->lock, flags);
2898
2899 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);

--- 22 unchanged lines hidden (view full) ---

2922 int ep;
2923
2924 if (!hsotg)
2925 return -ENODEV;
2926
2927 mutex_lock(&hsotg->init_mutex);
2928
2929 /* all endpoints should be shutdown */
2935
2936 spin_lock_irqsave(&hsotg->lock, flags);
2937 s3c_hsotg_init(hsotg);
2938 s3c_hsotg_core_init_disconnected(hsotg);
2939 hsotg->enabled = 0;
2940 spin_unlock_irqrestore(&hsotg->lock, flags);
2941
2942 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);

--- 22 unchanged lines hidden (view full) ---

2965 int ep;
2966
2967 if (!hsotg)
2968 return -ENODEV;
2969
2970 mutex_lock(&hsotg->init_mutex);
2971
2972 /* all endpoints should be shutdown */
2930 for (ep = 1; ep < hsotg->num_of_eps; ep++)
2931 s3c_hsotg_ep_disable_force(&hsotg->eps[ep].ep, true);
2973 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
2974 if (hsotg->eps_in[ep])
2975 s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
2976 if (hsotg->eps_out[ep])
2977 s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
2978 }
2932
2933 spin_lock_irqsave(&hsotg->lock, flags);
2934
2935 hsotg->driver = NULL;
2936 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2937 hsotg->enabled = 0;
2938
2939 spin_unlock_irqrestore(&hsotg->lock, flags);
2940
2979
2980 spin_lock_irqsave(&hsotg->lock, flags);
2981
2982 hsotg->driver = NULL;
2983 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2984 hsotg->enabled = 0;
2985
2986 spin_unlock_irqrestore(&hsotg->lock, flags);
2987
2988 if (!IS_ERR_OR_NULL(hsotg->uphy))
2989 otg_set_peripheral(hsotg->uphy->otg, NULL);
2941 s3c_hsotg_phy_disable(hsotg);
2942
2943 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
2944
2945 clk_disable(hsotg->clk);
2946
2947 mutex_unlock(&hsotg->init_mutex);
2948

--- 28 unchanged lines hidden (view full) ---

2977 mutex_lock(&hsotg->init_mutex);
2978 spin_lock_irqsave(&hsotg->lock, flags);
2979 if (is_on) {
2980 clk_enable(hsotg->clk);
2981 hsotg->enabled = 1;
2982 s3c_hsotg_core_connect(hsotg);
2983 } else {
2984 s3c_hsotg_core_disconnect(hsotg);
2990 s3c_hsotg_phy_disable(hsotg);
2991
2992 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
2993
2994 clk_disable(hsotg->clk);
2995
2996 mutex_unlock(&hsotg->init_mutex);
2997

--- 28 unchanged lines hidden (view full) ---

3026 mutex_lock(&hsotg->init_mutex);
3027 spin_lock_irqsave(&hsotg->lock, flags);
3028 if (is_on) {
3029 clk_enable(hsotg->clk);
3030 hsotg->enabled = 1;
3031 s3c_hsotg_core_connect(hsotg);
3032 } else {
3033 s3c_hsotg_core_disconnect(hsotg);
3034 s3c_hsotg_disconnect(hsotg);
2985 hsotg->enabled = 0;
2986 clk_disable(hsotg->clk);
2987 }
2988
2989 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2990 spin_unlock_irqrestore(&hsotg->lock, flags);
2991 mutex_unlock(&hsotg->init_mutex);
2992
2993 return 0;
2994}
2995
3035 hsotg->enabled = 0;
3036 clk_disable(hsotg->clk);
3037 }
3038
3039 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3040 spin_unlock_irqrestore(&hsotg->lock, flags);
3041 mutex_unlock(&hsotg->init_mutex);
3042
3043 return 0;
3044}
3045
3046static int s3c_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
3047{
3048 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3049 unsigned long flags;
3050
3051 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3052 spin_lock_irqsave(&hsotg->lock, flags);
3053
3054 if (is_active) {
3055 /* Kill any ep0 requests as controller will be reinitialized */
3056 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3057 s3c_hsotg_core_init_disconnected(hsotg);
3058 if (hsotg->enabled)
3059 s3c_hsotg_core_connect(hsotg);
3060 } else {
3061 s3c_hsotg_core_disconnect(hsotg);
3062 s3c_hsotg_disconnect(hsotg);
3063 }
3064
3065 spin_unlock_irqrestore(&hsotg->lock, flags);
3066 return 0;
3067}
3068
3069/**
3070 * s3c_hsotg_vbus_draw - report bMaxPower field
3071 * @gadget: The usb gadget state
3072 * @mA: Amount of current
3073 *
3074 * Report how much power the device may consume to the phy.
3075 */
3076static int s3c_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
3077{
3078 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3079
3080 if (IS_ERR_OR_NULL(hsotg->uphy))
3081 return -ENOTSUPP;
3082 return usb_phy_set_power(hsotg->uphy, mA);
3083}
3084
2996static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2997 .get_frame = s3c_hsotg_gadget_getframe,
2998 .udc_start = s3c_hsotg_udc_start,
2999 .udc_stop = s3c_hsotg_udc_stop,
3000 .pullup = s3c_hsotg_pullup,
3085static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
3086 .get_frame = s3c_hsotg_gadget_getframe,
3087 .udc_start = s3c_hsotg_udc_start,
3088 .udc_stop = s3c_hsotg_udc_stop,
3089 .pullup = s3c_hsotg_pullup,
3090 .vbus_session = s3c_hsotg_vbus_session,
3091 .vbus_draw = s3c_hsotg_vbus_draw,
3001};
3002
3003/**
3004 * s3c_hsotg_initep - initialise a single endpoint
3005 * @hsotg: The device state.
3006 * @hs_ep: The endpoint to be initialised.
3007 * @epnum: The endpoint number
3008 *
3009 * Initialise the given endpoint (as part of the probe and device state
3010 * creation) to give to the gadget driver. Setup the endpoint name, any
3011 * direction information and other state that may be required.
3012 */
3013static void s3c_hsotg_initep(struct dwc2_hsotg *hsotg,
3014 struct s3c_hsotg_ep *hs_ep,
3092};
3093
3094/**
3095 * s3c_hsotg_initep - initialise a single endpoint
3096 * @hsotg: The device state.
3097 * @hs_ep: The endpoint to be initialised.
3098 * @epnum: The endpoint number
3099 *
3100 * Initialise the given endpoint (as part of the probe and device state
3101 * creation) to give to the gadget driver. Setup the endpoint name, any
3102 * direction information and other state that may be required.
3103 */
3104static void s3c_hsotg_initep(struct dwc2_hsotg *hsotg,
3105 struct s3c_hsotg_ep *hs_ep,
3015 int epnum)
3106 int epnum,
3107 bool dir_in)
3016{
3017 char *dir;
3018
3019 if (epnum == 0)
3020 dir = "";
3108{
3109 char *dir;
3110
3111 if (epnum == 0)
3112 dir = "";
3021 else if ((epnum % 2) == 0) {
3022 dir = "out";
3023 } else {
3113 else if (dir_in)
3024 dir = "in";
3114 dir = "in";
3025 hs_ep->dir_in = 1;
3026 }
3115 else
3116 dir = "out";
3027
3117
3118 hs_ep->dir_in = dir_in;
3028 hs_ep->index = epnum;
3029
3030 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3031
3032 INIT_LIST_HEAD(&hs_ep->queue);
3033 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3034
3035 /* add to the list of endpoints known by the gadget driver */

--- 7 unchanged lines hidden (view full) ---

3043
3044 /*
3045 * if we're using dma, we need to set the next-endpoint pointer
3046 * to be something valid.
3047 */
3048
3049 if (using_dma(hsotg)) {
3050 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3119 hs_ep->index = epnum;
3120
3121 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3122
3123 INIT_LIST_HEAD(&hs_ep->queue);
3124 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3125
3126 /* add to the list of endpoints known by the gadget driver */

--- 7 unchanged lines hidden (view full) ---

3134
3135 /*
3136 * if we're using dma, we need to set the next-endpoint pointer
3137 * to be something valid.
3138 */
3139
3140 if (using_dma(hsotg)) {
3141 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3051 writel(next, hsotg->regs + DIEPCTL(epnum));
3052 writel(next, hsotg->regs + DOEPCTL(epnum));
3142 if (dir_in)
3143 writel(next, hsotg->regs + DIEPCTL(epnum));
3144 else
3145 writel(next, hsotg->regs + DOEPCTL(epnum));
3053 }
3054}
3055
3056/**
3057 * s3c_hsotg_hw_cfg - read HW configuration registers
3058 * @param: The device state
3059 *
3060 * Read the USB core HW configuration registers
3061 */
3146 }
3147}
3148
3149/**
3150 * s3c_hsotg_hw_cfg - read HW configuration registers
3151 * @param: The device state
3152 *
3153 * Read the USB core HW configuration registers
3154 */
3062static void s3c_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3155static int s3c_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3063{
3156{
3064 u32 cfg2, cfg3, cfg4;
3157 u32 cfg;
3158 u32 ep_type;
3159 u32 i;
3160
3065 /* check hardware configuration */
3066
3161 /* check hardware configuration */
3162
3067 cfg2 = readl(hsotg->regs + 0x48);
3068 hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
3163 cfg = readl(hsotg->regs + GHWCFG2);
3164 hsotg->num_of_eps = (cfg >> 10) & 0xF;
3165 /* Add ep0 */
3166 hsotg->num_of_eps++;
3069
3167
3070 cfg3 = readl(hsotg->regs + 0x4C);
3071 hsotg->fifo_mem = (cfg3 >> 16);
3168 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct s3c_hsotg_ep),
3169 GFP_KERNEL);
3170 if (!hsotg->eps_in[0])
3171 return -ENOMEM;
3172 /* Same s3c_hsotg_ep is used in both directions for ep0 */
3173 hsotg->eps_out[0] = hsotg->eps_in[0];
3072
3174
3073 cfg4 = readl(hsotg->regs + 0x50);
3074 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
3175 cfg = readl(hsotg->regs + GHWCFG1);
3176 for (i = 1; i < hsotg->num_of_eps; i++, cfg >>= 2) {
3177 ep_type = cfg & 3;
3178 /* Direction in or both */
3179 if (!(ep_type & 2)) {
3180 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
3181 sizeof(struct s3c_hsotg_ep), GFP_KERNEL);
3182 if (!hsotg->eps_in[i])
3183 return -ENOMEM;
3184 }
3185 /* Direction out or both */
3186 if (!(ep_type & 1)) {
3187 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
3188 sizeof(struct s3c_hsotg_ep), GFP_KERNEL);
3189 if (!hsotg->eps_out[i])
3190 return -ENOMEM;
3191 }
3192 }
3075
3193
3194 cfg = readl(hsotg->regs + GHWCFG3);
3195 hsotg->fifo_mem = (cfg >> 16);
3196
3197 cfg = readl(hsotg->regs + GHWCFG4);
3198 hsotg->dedicated_fifos = (cfg >> 25) & 1;
3199
3076 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3077 hsotg->num_of_eps,
3078 hsotg->dedicated_fifos ? "dedicated" : "shared",
3079 hsotg->fifo_mem);
3200 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3201 hsotg->num_of_eps,
3202 hsotg->dedicated_fifos ? "dedicated" : "shared",
3203 hsotg->fifo_mem);
3204 return 0;
3080}
3081
3082/**
3083 * s3c_hsotg_dump - dump state of the udc
3084 * @param: The device state
3085 */
3086static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg)
3087{

--- 10 unchanged lines hidden (view full) ---

3098 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3099 readl(regs + GAHBCFG), readl(regs + 0x44));
3100
3101 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3102 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3103
3104 /* show periodic fifo settings */
3105
3205}
3206
3207/**
3208 * s3c_hsotg_dump - dump state of the udc
3209 * @param: The device state
3210 */
3211static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg)
3212{

--- 10 unchanged lines hidden (view full) ---

3223 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3224 readl(regs + GAHBCFG), readl(regs + 0x44));
3225
3226 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3227 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3228
3229 /* show periodic fifo settings */
3230
3106 for (idx = 1; idx <= 15; idx++) {
3231 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3107 val = readl(regs + DPTXFSIZN(idx));
3108 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3109 val >> FIFOSIZE_DEPTH_SHIFT,
3110 val & FIFOSIZE_STARTADDR_MASK);
3111 }
3112
3232 val = readl(regs + DPTXFSIZN(idx));
3233 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3234 val >> FIFOSIZE_DEPTH_SHIFT,
3235 val & FIFOSIZE_STARTADDR_MASK);
3236 }
3237
3113 for (idx = 0; idx < 15; idx++) {
3238 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3114 dev_info(dev,
3115 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3116 readl(regs + DIEPCTL(idx)),
3117 readl(regs + DIEPTSIZ(idx)),
3118 readl(regs + DIEPDMA(idx)));
3119
3120 val = readl(regs + DOEPCTL(idx));
3121 dev_info(dev,

--- 41 unchanged lines hidden (view full) ---

3163 readl(regs + DAINT));
3164
3165 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3166 readl(regs + GNPTXSTS),
3167 readl(regs + GRXSTSR));
3168
3169 seq_puts(seq, "\nEndpoint status:\n");
3170
3239 dev_info(dev,
3240 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3241 readl(regs + DIEPCTL(idx)),
3242 readl(regs + DIEPTSIZ(idx)),
3243 readl(regs + DIEPDMA(idx)));
3244
3245 val = readl(regs + DOEPCTL(idx));
3246 dev_info(dev,

--- 41 unchanged lines hidden (view full) ---

3288 readl(regs + DAINT));
3289
3290 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3291 readl(regs + GNPTXSTS),
3292 readl(regs + GRXSTSR));
3293
3294 seq_puts(seq, "\nEndpoint status:\n");
3295
3171 for (idx = 0; idx < 15; idx++) {
3296 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3172 u32 in, out;
3173
3174 in = readl(regs + DIEPCTL(idx));
3175 out = readl(regs + DOEPCTL(idx));
3176
3177 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3178 idx, in, out);
3179

--- 42 unchanged lines hidden (view full) ---

3222
3223 val = readl(regs + GNPTXFSIZ);
3224 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3225 val >> FIFOSIZE_DEPTH_SHIFT,
3226 val & FIFOSIZE_DEPTH_MASK);
3227
3228 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
3229
3297 u32 in, out;
3298
3299 in = readl(regs + DIEPCTL(idx));
3300 out = readl(regs + DOEPCTL(idx));
3301
3302 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3303 idx, in, out);
3304

--- 42 unchanged lines hidden (view full) ---

3347
3348 val = readl(regs + GNPTXFSIZ);
3349 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3350 val >> FIFOSIZE_DEPTH_SHIFT,
3351 val & FIFOSIZE_DEPTH_MASK);
3352
3353 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
3354
3230 for (idx = 1; idx <= 15; idx++) {
3355 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3231 val = readl(regs + DPTXFSIZN(idx));
3232
3233 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3234 val >> FIFOSIZE_DEPTH_SHIFT,
3235 val & FIFOSIZE_STARTADDR_MASK);
3236 }
3237
3238 return 0;

--- 127 unchanged lines hidden (view full) ---

3366 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3367
3368 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3369 hsotg, &fifo_fops);
3370
3371 if (IS_ERR(hsotg->debug_fifo))
3372 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3373
3356 val = readl(regs + DPTXFSIZN(idx));
3357
3358 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3359 val >> FIFOSIZE_DEPTH_SHIFT,
3360 val & FIFOSIZE_STARTADDR_MASK);
3361 }
3362
3363 return 0;

--- 127 unchanged lines hidden (view full) ---

3491 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3492
3493 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3494 hsotg, &fifo_fops);
3495
3496 if (IS_ERR(hsotg->debug_fifo))
3497 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3498
3374 /* create one file for each endpoint */
3375
3499 /* Create one file for each out endpoint */
3376 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3500 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3377 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3501 struct s3c_hsotg_ep *ep;
3378
3502
3379 ep->debugfs = debugfs_create_file(ep->name, 0444,
3380 root, ep, &ep_fops);
3503 ep = hsotg->eps_out[epidx];
3504 if (ep) {
3505 ep->debugfs = debugfs_create_file(ep->name, 0444,
3506 root, ep, &ep_fops);
3381
3507
3382 if (IS_ERR(ep->debugfs))
3383 dev_err(hsotg->dev, "failed to create %s debug file\n",
3384 ep->name);
3508 if (IS_ERR(ep->debugfs))
3509 dev_err(hsotg->dev, "failed to create %s debug file\n",
3510 ep->name);
3511 }
3385 }
3512 }
3513 /* Create one file for each in endpoint. EP0 is handled with out eps */
3514 for (epidx = 1; epidx < hsotg->num_of_eps; epidx++) {
3515 struct s3c_hsotg_ep *ep;
3516
3517 ep = hsotg->eps_in[epidx];
3518 if (ep) {
3519 ep->debugfs = debugfs_create_file(ep->name, 0444,
3520 root, ep, &ep_fops);
3521
3522 if (IS_ERR(ep->debugfs))
3523 dev_err(hsotg->dev, "failed to create %s debug file\n",
3524 ep->name);
3525 }
3526 }
3386}
3387
3388/**
3389 * s3c_hsotg_delete_debug - cleanup debugfs entries
3390 * @hsotg: The driver state
3391 *
3392 * Cleanup (remove) the debugfs files for use on module exit.
3393 */
3394static void s3c_hsotg_delete_debug(struct dwc2_hsotg *hsotg)
3395{
3396 unsigned epidx;
3397
3398 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3527}
3528
3529/**
3530 * s3c_hsotg_delete_debug - cleanup debugfs entries
3531 * @hsotg: The driver state
3532 *
3533 * Cleanup (remove) the debugfs files for use on module exit.
3534 */
3535static void s3c_hsotg_delete_debug(struct dwc2_hsotg *hsotg)
3536{
3537 unsigned epidx;
3538
3539 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3399 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3400 debugfs_remove(ep->debugfs);
3540 if (hsotg->eps_in[epidx])
3541 debugfs_remove(hsotg->eps_in[epidx]->debugfs);
3542 if (hsotg->eps_out[epidx])
3543 debugfs_remove(hsotg->eps_out[epidx]->debugfs);
3401 }
3402
3403 debugfs_remove(hsotg->debug_file);
3404 debugfs_remove(hsotg->debug_fifo);
3405 debugfs_remove(hsotg->debug_root);
3406}
3407
3544 }
3545
3546 debugfs_remove(hsotg->debug_file);
3547 debugfs_remove(hsotg->debug_fifo);
3548 debugfs_remove(hsotg->debug_root);
3549}
3550
3551#ifdef CONFIG_OF
3552static void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg)
3553{
3554 struct device_node *np = hsotg->dev->of_node;
3555 u32 len = 0;
3556 u32 i = 0;
3557
3558 /* Enable dma if requested in device tree */
3559 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
3560
3561 /*
3562 * Register TX periodic fifo size per endpoint.
3563 * EP0 is excluded since it has no fifo configuration.
3564 */
3565 if (!of_find_property(np, "g-tx-fifo-size", &len))
3566 goto rx_fifo;
3567
3568 len /= sizeof(u32);
3569
3570 /* Read tx fifo sizes other than ep0 */
3571 if (of_property_read_u32_array(np, "g-tx-fifo-size",
3572 &hsotg->g_tx_fifo_sz[1], len))
3573 goto rx_fifo;
3574
3575 /* Add ep0 */
3576 len++;
3577
3578 /* Make remaining TX fifos unavailable */
3579 if (len < MAX_EPS_CHANNELS) {
3580 for (i = len; i < MAX_EPS_CHANNELS; i++)
3581 hsotg->g_tx_fifo_sz[i] = 0;
3582 }
3583
3584rx_fifo:
3585 /* Register RX fifo size */
3586 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3587
3588 /* Register NPTX fifo size */
3589 of_property_read_u32(np, "g-np-tx-fifo-size",
3590 &hsotg->g_np_g_tx_fifo_sz);
3591}
3592#else
3593static inline void s3c_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
3594#endif
3595
3408/**
3409 * dwc2_gadget_init - init function for gadget
3410 * @dwc2: The data structure for the DWC2 driver.
3411 * @irq: The IRQ number for the controller.
3412 */
3413int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3414{
3415 struct device *dev = hsotg->dev;
3416 struct s3c_hsotg_plat *plat = dev->platform_data;
3596/**
3597 * dwc2_gadget_init - init function for gadget
3598 * @dwc2: The data structure for the DWC2 driver.
3599 * @irq: The IRQ number for the controller.
3600 */
3601int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3602{
3603 struct device *dev = hsotg->dev;
3604 struct s3c_hsotg_plat *plat = dev->platform_data;
3417 struct phy *phy;
3418 struct usb_phy *uphy;
3419 struct s3c_hsotg_ep *eps;
3420 int epnum;
3421 int ret;
3422 int i;
3605 int epnum;
3606 int ret;
3607 int i;
3608 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
3423
3424 /* Set default UTMI width */
3425 hsotg->phyif = GUSBCFG_PHYIF16;
3426
3609
3610 /* Set default UTMI width */
3611 hsotg->phyif = GUSBCFG_PHYIF16;
3612
3613 s3c_hsotg_of_probe(hsotg);
3614
3615 /* Initialize to legacy fifo configuration values */
3616 hsotg->g_rx_fifo_sz = 2048;
3617 hsotg->g_np_g_tx_fifo_sz = 1024;
3618 memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
3619 /* Device tree specific probe */
3620 s3c_hsotg_of_probe(hsotg);
3621 /* Dump fifo information */
3622 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3623 hsotg->g_np_g_tx_fifo_sz);
3624 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3625 for (i = 0; i < MAX_EPS_CHANNELS; i++)
3626 dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
3627 hsotg->g_tx_fifo_sz[i]);
3427 /*
3628 /*
3428 * Attempt to find a generic PHY, then look for an old style
3429 * USB PHY, finally fall back to pdata
3629 * If platform probe couldn't find a generic PHY or an old style
3630 * USB PHY, fall back to pdata
3430 */
3631 */
3431 phy = devm_phy_get(dev, "usb2-phy");
3432 if (IS_ERR(phy)) {
3433 uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
3434 if (IS_ERR(uphy)) {
3435 /* Fallback for pdata */
3436 plat = dev_get_platdata(dev);
3437 if (!plat) {
3438 dev_err(dev,
3439 "no platform data or transceiver defined\n");
3440 return -EPROBE_DEFER;
3441 }
3442 hsotg->plat = plat;
3443 } else
3444 hsotg->uphy = uphy;
3445 } else {
3446 hsotg->phy = phy;
3632 if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) {
3633 plat = dev_get_platdata(dev);
3634 if (!plat) {
3635 dev_err(dev,
3636 "no platform data or transceiver defined\n");
3637 return -EPROBE_DEFER;
3638 }
3639 hsotg->plat = plat;
3640 } else if (hsotg->phy) {
3447 /*
3448 * If using the generic PHY framework, check if the PHY bus
3449 * width is 8-bit and set the phyif appropriately.
3450 */
3641 /*
3642 * If using the generic PHY framework, check if the PHY bus
3643 * width is 8-bit and set the phyif appropriately.
3644 */
3451 if (phy_get_bus_width(phy) == 8)
3645 if (phy_get_bus_width(hsotg->phy) == 8)
3452 hsotg->phyif = GUSBCFG_PHYIF8;
3453 }
3454
3455 hsotg->clk = devm_clk_get(dev, "otg");
3456 if (IS_ERR(hsotg->clk)) {
3457 hsotg->clk = NULL;
3458 dev_dbg(dev, "cannot get otg clock\n");
3459 }

--- 23 unchanged lines hidden (view full) ---

3483 goto err_clk;
3484 }
3485
3486 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3487 hsotg->supplies);
3488
3489 if (ret) {
3490 dev_err(dev, "failed to enable supplies: %d\n", ret);
3646 hsotg->phyif = GUSBCFG_PHYIF8;
3647 }
3648
3649 hsotg->clk = devm_clk_get(dev, "otg");
3650 if (IS_ERR(hsotg->clk)) {
3651 hsotg->clk = NULL;
3652 dev_dbg(dev, "cannot get otg clock\n");
3653 }

--- 23 unchanged lines hidden (view full) ---

3677 goto err_clk;
3678 }
3679
3680 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3681 hsotg->supplies);
3682
3683 if (ret) {
3684 dev_err(dev, "failed to enable supplies: %d\n", ret);
3491 goto err_supplies;
3685 goto err_clk;
3492 }
3493
3494 /* usb phy enable */
3495 s3c_hsotg_phy_enable(hsotg);
3496
3686 }
3687
3688 /* usb phy enable */
3689 s3c_hsotg_phy_enable(hsotg);
3690
3691 /*
3692 * Force Device mode before initialization.
3693 * This allows correctly configuring fifo for device mode.
3694 */
3695 __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEHOSTMODE);
3696 __orr32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE);
3697
3698 /*
3699 * According to Synopsys databook, this sleep is needed for the force
3700 * device mode to take effect.
3701 */
3702 msleep(25);
3703
3497 s3c_hsotg_corereset(hsotg);
3704 s3c_hsotg_corereset(hsotg);
3498 s3c_hsotg_hw_cfg(hsotg);
3705 ret = s3c_hsotg_hw_cfg(hsotg);
3706 if (ret) {
3707 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
3708 goto err_clk;
3709 }
3710
3499 s3c_hsotg_init(hsotg);
3500
3711 s3c_hsotg_init(hsotg);
3712
3713 /* Switch back to default configuration */
3714 __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE);
3715
3716 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3717 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3718 if (!hsotg->ctrl_buff) {
3719 dev_err(dev, "failed to allocate ctrl request buff\n");
3720 ret = -ENOMEM;
3721 goto err_supplies;
3722 }
3723
3724 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3725 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3726 if (!hsotg->ep0_buff) {
3727 dev_err(dev, "failed to allocate ctrl reply buff\n");
3728 ret = -ENOMEM;
3729 goto err_supplies;
3730 }
3731
3501 ret = devm_request_irq(hsotg->dev, irq, s3c_hsotg_irq, IRQF_SHARED,
3502 dev_name(hsotg->dev), hsotg);
3503 if (ret < 0) {
3504 s3c_hsotg_phy_disable(hsotg);
3505 clk_disable_unprepare(hsotg->clk);
3506 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3507 hsotg->supplies);
3508 dev_err(dev, "cannot claim IRQ for gadget\n");
3732 ret = devm_request_irq(hsotg->dev, irq, s3c_hsotg_irq, IRQF_SHARED,
3733 dev_name(hsotg->dev), hsotg);
3734 if (ret < 0) {
3735 s3c_hsotg_phy_disable(hsotg);
3736 clk_disable_unprepare(hsotg->clk);
3737 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3738 hsotg->supplies);
3739 dev_err(dev, "cannot claim IRQ for gadget\n");
3509 goto err_clk;
3740 goto err_supplies;
3510 }
3511
3512 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3513
3514 if (hsotg->num_of_eps == 0) {
3515 dev_err(dev, "wrong number of EPs (zero)\n");
3516 ret = -EINVAL;
3517 goto err_supplies;
3518 }
3519
3741 }
3742
3743 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3744
3745 if (hsotg->num_of_eps == 0) {
3746 dev_err(dev, "wrong number of EPs (zero)\n");
3747 ret = -EINVAL;
3748 goto err_supplies;
3749 }
3750
3520 eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep),
3521 GFP_KERNEL);
3522 if (!eps) {
3523 ret = -ENOMEM;
3524 goto err_supplies;
3525 }
3526
3527 hsotg->eps = eps;
3528
3529 /* setup endpoint information */
3530
3531 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3751 /* setup endpoint information */
3752
3753 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3532 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3754 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
3533
3534 /* allocate EP0 request */
3535
3755
3756 /* allocate EP0 request */
3757
3536 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3758 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
3537 GFP_KERNEL);
3538 if (!hsotg->ctrl_req) {
3539 dev_err(dev, "failed to allocate ctrl req\n");
3540 ret = -ENOMEM;
3759 GFP_KERNEL);
3760 if (!hsotg->ctrl_req) {
3761 dev_err(dev, "failed to allocate ctrl req\n");
3762 ret = -ENOMEM;
3541 goto err_ep_mem;
3763 goto err_supplies;
3542 }
3543
3544 /* initialise the endpoints now the core has been initialised */
3764 }
3765
3766 /* initialise the endpoints now the core has been initialised */
3545 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++)
3546 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3767 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3768 if (hsotg->eps_in[epnum])
3769 s3c_hsotg_initep(hsotg, hsotg->eps_in[epnum],
3770 epnum, 1);
3771 if (hsotg->eps_out[epnum])
3772 s3c_hsotg_initep(hsotg, hsotg->eps_out[epnum],
3773 epnum, 0);
3774 }
3547
3548 /* disable power and clock */
3549 s3c_hsotg_phy_disable(hsotg);
3550
3551 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3552 hsotg->supplies);
3553 if (ret) {
3554 dev_err(dev, "failed to disable supplies: %d\n", ret);
3775
3776 /* disable power and clock */
3777 s3c_hsotg_phy_disable(hsotg);
3778
3779 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3780 hsotg->supplies);
3781 if (ret) {
3782 dev_err(dev, "failed to disable supplies: %d\n", ret);
3555 goto err_ep_mem;
3783 goto err_supplies;
3556 }
3557
3558 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3559 if (ret)
3784 }
3785
3786 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3787 if (ret)
3560 goto err_ep_mem;
3788 goto err_supplies;
3561
3562 s3c_hsotg_create_debug(hsotg);
3563
3564 s3c_hsotg_dump(hsotg);
3565
3566 return 0;
3567
3789
3790 s3c_hsotg_create_debug(hsotg);
3791
3792 s3c_hsotg_dump(hsotg);
3793
3794 return 0;
3795
3568err_ep_mem:
3569 kfree(eps);
3570err_supplies:
3571 s3c_hsotg_phy_disable(hsotg);
3572err_clk:
3573 clk_disable_unprepare(hsotg->clk);
3574
3575 return ret;
3576}
3577EXPORT_SYMBOL_GPL(dwc2_gadget_init);

--- 29 unchanged lines hidden (view full) ---

3607 if (hsotg->enabled)
3608 s3c_hsotg_core_disconnect(hsotg);
3609 s3c_hsotg_disconnect(hsotg);
3610 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3611 spin_unlock_irqrestore(&hsotg->lock, flags);
3612
3613 s3c_hsotg_phy_disable(hsotg);
3614
3796err_supplies:
3797 s3c_hsotg_phy_disable(hsotg);
3798err_clk:
3799 clk_disable_unprepare(hsotg->clk);
3800
3801 return ret;
3802}
3803EXPORT_SYMBOL_GPL(dwc2_gadget_init);

--- 29 unchanged lines hidden (view full) ---

3833 if (hsotg->enabled)
3834 s3c_hsotg_core_disconnect(hsotg);
3835 s3c_hsotg_disconnect(hsotg);
3836 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3837 spin_unlock_irqrestore(&hsotg->lock, flags);
3838
3839 s3c_hsotg_phy_disable(hsotg);
3840
3615 for (ep = 0; ep < hsotg->num_of_eps; ep++)
3616 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
3841 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3842 if (hsotg->eps_in[ep])
3843 s3c_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3844 if (hsotg->eps_out[ep])
3845 s3c_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3846 }
3617
3618 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3619 hsotg->supplies);
3620 clk_disable(hsotg->clk);
3621 }
3622
3623 mutex_unlock(&hsotg->init_mutex);
3624

--- 32 unchanged lines hidden --- 		3847
3848 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3849 hsotg->supplies);
3850 clk_disable(hsotg->clk);
3851 }
3852
3853 mutex_unlock(&hsotg->init_mutex);
3854

--- 32 unchanged lines hidden ---