sifive.c (b75c1da925d991acae8b2abbb2e5ea321b9bbefb) sifive.c (9b8fef6345d5487137d4193bb0a0eae2203c284e)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * SiFive UART driver
4 * Copyright (C) 2018 Paul Walmsley <paul@pwsan.com>
5 * Copyright (C) 2018-2019 SiFive
6 *
7 * Based partially on:
8 * - drivers/tty/serial/pxa.c

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397 *
398 * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
399 * to by @ssp and pass them up to the Linux serial layer.
400 *
401 * Context: Expects ssp->port.lock to be held by caller.
402 */
403static void __ssp_receive_chars(struct sifive_serial_port *ssp)
404{
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * SiFive UART driver
4 * Copyright (C) 2018 Paul Walmsley <paul@pwsan.com>
5 * Copyright (C) 2018-2019 SiFive
6 *
7 * Based partially on:
8 * - drivers/tty/serial/pxa.c

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397 *
398 * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
399 * to by @ssp and pass them up to the Linux serial layer.
400 *
401 * Context: Expects ssp->port.lock to be held by caller.
402 */
403static void __ssp_receive_chars(struct sifive_serial_port *ssp)
404{
405 unsigned char ch;
405 char is_empty;
406 int c;
406 char is_empty;
407 int c;
407 u8 ch;
408
409 for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) {
410 ch = __ssp_receive_char(ssp, &is_empty);
411 if (is_empty)
412 break;
413
414 ssp->port.icount.rx++;
415 uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);

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806
807 __ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp);
808
809 if (locked)
810 spin_unlock(&ssp->port.lock);
811 local_irq_restore(flags);
812}
813
408
409 for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) {
410 ch = __ssp_receive_char(ssp, &is_empty);
411 if (is_empty)
412 break;
413
414 ssp->port.icount.rx++;
415 uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);

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806
807 __ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp);
808
809 if (locked)
810 spin_unlock(&ssp->port.lock);
811 local_irq_restore(flags);
812}
813
814static int __init sifive_serial_console_setup(struct console *co, char *options)
814static int sifive_serial_console_setup(struct console *co, char *options)
815{
816 struct sifive_serial_port *ssp;
817 int baud = SIFIVE_DEFAULT_BAUD_RATE;
818 int bits = 8;
819 int parity = 'n';
820 int flow = 'n';
821
822 if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS)

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912 struct clk *clk;
913 void __iomem *base;
914 int irq, id, r;
915
916 irq = platform_get_irq(pdev, 0);
917 if (irq < 0)
918 return -EPROBE_DEFER;
919
815{
816 struct sifive_serial_port *ssp;
817 int baud = SIFIVE_DEFAULT_BAUD_RATE;
818 int bits = 8;
819 int parity = 'n';
820 int flow = 'n';
821
822 if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS)

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912 struct clk *clk;
913 void __iomem *base;
914 int irq, id, r;
915
916 irq = platform_get_irq(pdev, 0);
917 if (irq < 0)
918 return -EPROBE_DEFER;
919
920 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
921 if (IS_ERR(base))
920 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
921 base = devm_ioremap_resource(&pdev->dev, mem);
922 if (IS_ERR(base)) {
923 dev_err(&pdev->dev, "could not acquire device memory\n");
922 return PTR_ERR(base);
924 return PTR_ERR(base);
925 }
923
924 clk = devm_clk_get_enabled(&pdev->dev, NULL);
925 if (IS_ERR(clk)) {
926 dev_err(&pdev->dev, "unable to find controller clock\n");
927 return PTR_ERR(clk);
928 }
929
930 id = of_alias_get_id(pdev->dev.of_node, "serial");

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927 clk = devm_clk_get_enabled(&pdev->dev, NULL);
928 if (IS_ERR(clk)) {
929 dev_err(&pdev->dev, "unable to find controller clock\n");
930 return PTR_ERR(clk);
931 }
932
933 id = of_alias_get_id(pdev->dev.of_node, "serial");

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