omap-serial.c (0c49cd295d42d0032af11d55e2140dbec11dc8d0) omap-serial.c (391f93f2ec9f857c83bdd21a14dcf7e699f38579)
1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>

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58#define OMAP_UART_TX_WAKEUP_EN BIT(7)
59
60/* Feature flags */
61#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
62
63#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
64#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
65
1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>

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58#define OMAP_UART_TX_WAKEUP_EN BIT(7)
59
60/* Feature flags */
61#define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
62
63#define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
64#define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
65
66#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
66#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
67
68/* SCR register bitmasks */
69#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
70#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
71#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
72
73/* FCR register bitmasks */
74#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)

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88#define OMAP_UART_DMA_CH_FREE -1
89
90#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
91#define OMAP_MODE13X_SPEED 230400
92
93/* WER = 0x7F
94 * Enable module level wakeup in WER reg
95 */
67
68/* SCR register bitmasks */
69#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
70#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
71#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
72
73/* FCR register bitmasks */
74#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)

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88#define OMAP_UART_DMA_CH_FREE -1
89
90#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
91#define OMAP_MODE13X_SPEED 230400
92
93/* WER = 0x7F
94 * Enable module level wakeup in WER reg
95 */
96#define OMAP_UART_WER_MOD_WKUP 0X7F
96#define OMAP_UART_WER_MOD_WKUP 0x7F
97
98/* Enable XON/XOFF flow control on output */
99#define OMAP_UART_SW_TX 0x08
100
101/* Enable XON/XOFF flow control on input */
102#define OMAP_UART_SW_RX 0x02
103
104#define OMAP_UART_SW_CLR 0xF0

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109 u8 uart_dma_tx;
110 u8 uart_dma_rx;
111 int rx_dma_channel;
112 int tx_dma_channel;
113 dma_addr_t rx_buf_dma_phys;
114 dma_addr_t tx_buf_dma_phys;
115 unsigned int uart_base;
116 /*
97
98/* Enable XON/XOFF flow control on output */
99#define OMAP_UART_SW_TX 0x08
100
101/* Enable XON/XOFF flow control on input */
102#define OMAP_UART_SW_RX 0x02
103
104#define OMAP_UART_SW_CLR 0xF0

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109 u8 uart_dma_tx;
110 u8 uart_dma_rx;
111 int rx_dma_channel;
112 int tx_dma_channel;
113 dma_addr_t rx_buf_dma_phys;
114 dma_addr_t tx_buf_dma_phys;
115 unsigned int uart_base;
116 /*
117 * Buffer for rx dma.It is not required for tx because the buffer
117 * Buffer for rx dma. It is not required for tx because the buffer
118 * comes from port structure.
119 */
120 unsigned char *rx_buf;
121 unsigned int prev_rx_dma_pos;
122 int tx_buf_size;
123 int tx_dma_used;
124 int rx_dma_used;
125 spinlock_t tx_lock;

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146 unsigned char dlh;
147 unsigned char mdr1;
148 unsigned char scr;
149 unsigned char wer;
150
151 int use_dma;
152 /*
153 * Some bits in registers are cleared on a read, so they must
118 * comes from port structure.
119 */
120 unsigned char *rx_buf;
121 unsigned int prev_rx_dma_pos;
122 int tx_buf_size;
123 int tx_dma_used;
124 int rx_dma_used;
125 spinlock_t tx_lock;

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146 unsigned char dlh;
147 unsigned char mdr1;
148 unsigned char scr;
149 unsigned char wer;
150
151 int use_dma;
152 /*
153 * Some bits in registers are cleared on a read, so they must
154 * be saved whenever the register is read but the bits will not
154 * be saved whenever the register is read, but the bits will not
155 * be immediately processed.
156 */
157 unsigned int lsr_break_flag;
158 unsigned char msr_saved_flags;
159 char name[20];
160 unsigned long port_activity;
161 int context_loss_cnt;
162 u32 errata;

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1048
1049 /* Enable access to TCR/TLR */
1050 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1051 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1052 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1053
1054 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1055
155 * be immediately processed.
156 */
157 unsigned int lsr_break_flag;
158 unsigned char msr_saved_flags;
159 char name[20];
160 unsigned long port_activity;
161 int context_loss_cnt;
162 u32 errata;

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1048
1049 /* Enable access to TCR/TLR */
1050 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1051 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1052 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1053
1054 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1055
1056 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
1057
1056 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1057 /* Enable AUTORTS and AUTOCTS */
1058 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1059 /* Enable AUTORTS and AUTOCTS */
1060 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1058 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1059
1060 /* Ensure MCR RTS is asserted */
1061 up->mcr |= UART_MCR_RTS;
1062 } else {
1063 /* Disable AUTORTS and AUTOCTS */
1064 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1065 }

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1076 if (termios->c_iflag & IXON)
1077 up->efr |= OMAP_UART_SW_RX;
1078
1079 /*
1080 * IXOFF Flag:
1081 * Enable XON/XOFF flow control on output.
1082 * Transmit XON1, XOFF1
1083 */
1061 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1062
1063 /* Ensure MCR RTS is asserted */
1064 up->mcr |= UART_MCR_RTS;
1065 } else {
1066 /* Disable AUTORTS and AUTOCTS */
1067 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1068 }

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1079 if (termios->c_iflag & IXON)
1080 up->efr |= OMAP_UART_SW_RX;
1081
1082 /*
1083 * IXOFF Flag:
1084 * Enable XON/XOFF flow control on output.
1085 * Transmit XON1, XOFF1
1086 */
1084 if (termios->c_iflag & IXOFF)
1087 if (termios->c_iflag & IXOFF) {
1088 up->port.status |= UPSTAT_AUTOXOFF;
1085 up->efr |= OMAP_UART_SW_TX;
1089 up->efr |= OMAP_UART_SW_TX;
1090 }
1086
1087 /*
1088 * IXANY Flag:
1089 * Enable any character to restart output.
1090 * Operation resumes after receiving any
1091 * character after recognition of the XOFF character
1092 */
1093 if (termios->c_iflag & IXANY)

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1092 /*
1093 * IXANY Flag:
1094 * Enable any character to restart output.
1095 * Operation resumes after receiving any
1096 * character after recognition of the XOFF character
1097 */
1098 if (termios->c_iflag & IXANY)

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