fsl_lpuart.c (dd84cfff3cc3b79c9d616f85bd1178df135cbd1a) fsl_lpuart.c (0139da50dc53f0ce2804e83566d290c7e626fd17)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Freescale lpuart serial port driver
4 *
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 */
7
8#include <linux/clk.h>

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1350 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1351 kfree(sport->rx_ring.buf);
1352 sport->rx_ring.tail = 0;
1353 sport->rx_ring.head = 0;
1354 sport->dma_rx_desc = NULL;
1355 sport->dma_rx_cookie = -EINVAL;
1356}
1357
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Freescale lpuart serial port driver
4 *
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 */
7
8#include <linux/clk.h>

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1350 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1351 kfree(sport->rx_ring.buf);
1352 sport->rx_ring.tail = 0;
1353 sport->rx_ring.head = 0;
1354 sport->dma_rx_desc = NULL;
1355 sport->dma_rx_cookie = -EINVAL;
1356}
1357
1358static int lpuart_config_rs485(struct uart_port *port,
1358static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,
1359 struct serial_rs485 *rs485)
1360{
1361 struct lpuart_port *sport = container_of(port,
1362 struct lpuart_port, port);
1363
1364 u8 modem = readb(sport->port.membase + UARTMODEM) &
1365 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1366 writeb(modem, sport->port.membase + UARTMODEM);
1367
1359 struct serial_rs485 *rs485)
1360{
1361 struct lpuart_port *sport = container_of(port,
1362 struct lpuart_port, port);
1363
1364 u8 modem = readb(sport->port.membase + UARTMODEM) &
1365 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1366 writeb(modem, sport->port.membase + UARTMODEM);
1367
1368 /* clear unsupported configurations */
1369 rs485->delay_rts_before_send = 0;
1370 rs485->delay_rts_after_send = 0;
1371 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1372
1373 if (rs485->flags & SER_RS485_ENABLED) {
1374 /* Enable auto RS-485 RTS mode */
1375 modem |= UARTMODEM_TXRTSE;
1376
1377 /*
1378 * The hardware defaults to RTS logic HIGH while transfer.
1379 * Switch polarity in case RTS shall be logic HIGH
1380 * after transfer.

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1385 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1386 modem |= UARTMODEM_TXRTSPOL;
1387 }
1388
1389 writeb(modem, sport->port.membase + UARTMODEM);
1390 return 0;
1391}
1392
1368 if (rs485->flags & SER_RS485_ENABLED) {
1369 /* Enable auto RS-485 RTS mode */
1370 modem |= UARTMODEM_TXRTSE;
1371
1372 /*
1373 * The hardware defaults to RTS logic HIGH while transfer.
1374 * Switch polarity in case RTS shall be logic HIGH
1375 * after transfer.

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1380 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1381 modem |= UARTMODEM_TXRTSPOL;
1382 }
1383
1384 writeb(modem, sport->port.membase + UARTMODEM);
1385 return 0;
1386}
1387
1393static int lpuart32_config_rs485(struct uart_port *port,
1388static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios,
1394 struct serial_rs485 *rs485)
1395{
1396 struct lpuart_port *sport = container_of(port,
1397 struct lpuart_port, port);
1398
1399 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1400 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1401 lpuart32_write(&sport->port, modem, UARTMODIR);
1402
1389 struct serial_rs485 *rs485)
1390{
1391 struct lpuart_port *sport = container_of(port,
1392 struct lpuart_port, port);
1393
1394 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1395 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1396 lpuart32_write(&sport->port, modem, UARTMODIR);
1397
1403 /* clear unsupported configurations */
1404 rs485->delay_rts_before_send = 0;
1405 rs485->delay_rts_after_send = 0;
1406 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1407
1408 if (rs485->flags & SER_RS485_ENABLED) {
1409 /* Enable auto RS-485 RTS mode */
1410 modem |= UARTMODEM_TXRTSE;
1411
1412 /*
1413 * The hardware defaults to RTS logic HIGH while transfer.
1414 * Switch polarity in case RTS shall be logic HIGH
1415 * after transfer.

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2616static struct uart_driver lpuart_reg = {
2617 .owner = THIS_MODULE,
2618 .driver_name = DRIVER_NAME,
2619 .dev_name = DEV_NAME,
2620 .nr = ARRAY_SIZE(lpuart_ports),
2621 .cons = LPUART_CONSOLE,
2622};
2623
1398 if (rs485->flags & SER_RS485_ENABLED) {
1399 /* Enable auto RS-485 RTS mode */
1400 modem |= UARTMODEM_TXRTSE;
1401
1402 /*
1403 * The hardware defaults to RTS logic HIGH while transfer.
1404 * Switch polarity in case RTS shall be logic HIGH
1405 * after transfer.

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2606static struct uart_driver lpuart_reg = {
2607 .owner = THIS_MODULE,
2608 .driver_name = DRIVER_NAME,
2609 .dev_name = DEV_NAME,
2610 .nr = ARRAY_SIZE(lpuart_ports),
2611 .cons = LPUART_CONSOLE,
2612};
2613
2614static const struct serial_rs485 lpuart_rs485_supported = {
2615 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
2616 /* delay_rts_* and RX_DURING_TX are not supported */
2617};
2618
2624static int lpuart_probe(struct platform_device *pdev)
2625{
2626 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2627 struct device_node *np = pdev->dev.of_node;
2628 struct lpuart_port *sport;
2629 struct resource *res;
2630 irq_handler_t handler;
2631 int ret;

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2655 sport->port.ops = &lpuart_pops;
2656 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2657 sport->port.flags = UPF_BOOT_AUTOCONF;
2658
2659 if (lpuart_is_32(sport))
2660 sport->port.rs485_config = lpuart32_config_rs485;
2661 else
2662 sport->port.rs485_config = lpuart_config_rs485;
2619static int lpuart_probe(struct platform_device *pdev)
2620{
2621 const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2622 struct device_node *np = pdev->dev.of_node;
2623 struct lpuart_port *sport;
2624 struct resource *res;
2625 irq_handler_t handler;
2626 int ret;

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2650 sport->port.ops = &lpuart_pops;
2651 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2652 sport->port.flags = UPF_BOOT_AUTOCONF;
2653
2654 if (lpuart_is_32(sport))
2655 sport->port.rs485_config = lpuart32_config_rs485;
2656 else
2657 sport->port.rs485_config = lpuart_config_rs485;
2658 sport->port.rs485_supported = lpuart_rs485_supported;
2663
2664 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2665 if (IS_ERR(sport->ipg_clk)) {
2666 ret = PTR_ERR(sport->ipg_clk);
2667 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2668 return ret;
2669 }
2670

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2712 ret = lpuart_global_reset(sport);
2713 if (ret)
2714 goto failed_reset;
2715
2716 ret = uart_get_rs485_mode(&sport->port);
2717 if (ret)
2718 goto failed_get_rs485;
2719
2659
2660 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2661 if (IS_ERR(sport->ipg_clk)) {
2662 ret = PTR_ERR(sport->ipg_clk);
2663 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2664 return ret;
2665 }
2666

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2708 ret = lpuart_global_reset(sport);
2709 if (ret)
2710 goto failed_reset;
2711
2712 ret = uart_get_rs485_mode(&sport->port);
2713 if (ret)
2714 goto failed_get_rs485;
2715
2720 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2721 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2716 uart_rs485_config(&sport->port);
2722
2717
2723 if (sport->port.rs485.delay_rts_before_send ||
2724 sport->port.rs485.delay_rts_after_send)
2725 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2726
2727 sport->port.rs485_config(&sport->port, &sport->port.rs485);
2728
2729 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2730 DRIVER_NAME, sport);
2731 if (ret)
2732 goto failed_irq_request;
2733
2734 return 0;
2735
2736failed_irq_request:

--- 152 unchanged lines hidden --- 		2718 ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2719 DRIVER_NAME, sport);
2720 if (ret)
2721 goto failed_irq_request;
2722
2723 return 0;
2724
2725failed_irq_request:

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