amba-pl011.c (cc9263874b42bf98209dce0afe698b550648e770) amba-pl011.c (0e125a5facf857567f8bb6dbb1ceefac14b2fa64)
1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA

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88 [REG_ICR] = UART011_ICR,
89 [REG_DMACR] = UART011_DMACR,
90};
91
92/* There is by now at least one vendor with differing details, so handle it */
93struct vendor_data {
94 const u16 *reg_offset;
95 unsigned int ifls;
1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA

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88 [REG_ICR] = UART011_ICR,
89 [REG_DMACR] = UART011_DMACR,
90};
91
92/* There is by now at least one vendor with differing details, so handle it */
93struct vendor_data {
94 const u16 *reg_offset;
95 unsigned int ifls;
96 unsigned int fr_busy;
97 unsigned int fr_dsr;
98 unsigned int fr_cts;
99 unsigned int fr_ri;
96 bool access_32b;
97 bool oversampling;
98 bool dma_threshold;
99 bool cts_event_workaround;
100 bool always_enabled;
101 bool fixed_options;
102
103 unsigned int (*get_fifosize)(struct amba_device *dev);
104};
105
106static unsigned int get_fifosize_arm(struct amba_device *dev)
107{
108 return amba_rev(dev) < 3 ? 16 : 32;
109}
110
111static struct vendor_data vendor_arm = {
112 .reg_offset = pl011_std_offsets,
113 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
100 bool access_32b;
101 bool oversampling;
102 bool dma_threshold;
103 bool cts_event_workaround;
104 bool always_enabled;
105 bool fixed_options;
106
107 unsigned int (*get_fifosize)(struct amba_device *dev);
108};
109
110static unsigned int get_fifosize_arm(struct amba_device *dev)
111{
112 return amba_rev(dev) < 3 ? 16 : 32;
113}
114
115static struct vendor_data vendor_arm = {
116 .reg_offset = pl011_std_offsets,
117 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
118 .fr_busy = UART01x_FR_BUSY,
119 .fr_dsr = UART01x_FR_DSR,
120 .fr_cts = UART01x_FR_CTS,
121 .fr_ri = UART011_FR_RI,
114 .oversampling = false,
115 .dma_threshold = false,
116 .cts_event_workaround = false,
117 .always_enabled = false,
118 .fixed_options = false,
119 .get_fifosize = get_fifosize_arm,
120};
121
122static struct vendor_data vendor_sbsa = {
123 .reg_offset = pl011_std_offsets,
122 .oversampling = false,
123 .dma_threshold = false,
124 .cts_event_workaround = false,
125 .always_enabled = false,
126 .fixed_options = false,
127 .get_fifosize = get_fifosize_arm,
128};
129
130static struct vendor_data vendor_sbsa = {
131 .reg_offset = pl011_std_offsets,
132 .fr_busy = UART01x_FR_BUSY,
133 .fr_dsr = UART01x_FR_DSR,
134 .fr_cts = UART01x_FR_CTS,
135 .fr_ri = UART011_FR_RI,
124 .access_32b = true,
125 .oversampling = false,
126 .dma_threshold = false,
127 .cts_event_workaround = false,
128 .always_enabled = true,
129 .fixed_options = true,
130};
131

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159static unsigned int get_fifosize_st(struct amba_device *dev)
160{
161 return 64;
162}
163
164static struct vendor_data vendor_st = {
165 .reg_offset = pl011_st_offsets,
166 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
136 .access_32b = true,
137 .oversampling = false,
138 .dma_threshold = false,
139 .cts_event_workaround = false,
140 .always_enabled = true,
141 .fixed_options = true,
142};
143

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171static unsigned int get_fifosize_st(struct amba_device *dev)
172{
173 return 64;
174}
175
176static struct vendor_data vendor_st = {
177 .reg_offset = pl011_st_offsets,
178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
179 .fr_busy = UART01x_FR_BUSY,
180 .fr_dsr = UART01x_FR_DSR,
181 .fr_cts = UART01x_FR_CTS,
182 .fr_ri = UART011_FR_RI,
167 .oversampling = true,
168 .dma_threshold = true,
169 .cts_event_workaround = true,
170 .always_enabled = false,
171 .fixed_options = false,
172 .get_fifosize = get_fifosize_st,
173};
174

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187 [REG_ICR] = ZX_UART011_ICR,
188 [REG_DMACR] = ZX_UART011_DMACR,
189};
190
191static struct vendor_data vendor_zte __maybe_unused = {
192 .reg_offset = pl011_zte_offsets,
193 .access_32b = true,
194 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
183 .oversampling = true,
184 .dma_threshold = true,
185 .cts_event_workaround = true,
186 .always_enabled = false,
187 .fixed_options = false,
188 .get_fifosize = get_fifosize_st,
189};
190

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203 [REG_ICR] = ZX_UART011_ICR,
204 [REG_DMACR] = ZX_UART011_DMACR,
205};
206
207static struct vendor_data vendor_zte __maybe_unused = {
208 .reg_offset = pl011_zte_offsets,
209 .access_32b = true,
210 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
211 .fr_busy = ZX_UART01x_FR_BUSY,
212 .fr_dsr = ZX_UART01x_FR_DSR,
213 .fr_cts = ZX_UART01x_FR_CTS,
214 .fr_ri = ZX_UART011_FR_RI,
195 .get_fifosize = get_fifosize_arm,
196};
197
198/* Deals with DMA transactions */
199
200struct pl011_sgbuf {
201 struct scatterlist sg;
202 char *buf;

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1162}
1163
1164static void pl011_dma_shutdown(struct uart_amba_port *uap)
1165{
1166 if (!(uap->using_tx_dma || uap->using_rx_dma))
1167 return;
1168
1169 /* Disable RX and TX DMA */
215 .get_fifosize = get_fifosize_arm,
216};
217
218/* Deals with DMA transactions */
219
220struct pl011_sgbuf {
221 struct scatterlist sg;
222 char *buf;

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1182}
1183
1184static void pl011_dma_shutdown(struct uart_amba_port *uap)
1185{
1186 if (!(uap->using_tx_dma || uap->using_rx_dma))
1187 return;
1188
1189 /* Disable RX and TX DMA */
1170 while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY)
1190 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1171 cpu_relax();
1172
1173 spin_lock_irq(&uap->port.lock);
1174 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1175 pl011_write(uap->dmacr, uap, REG_DMACR);
1176 spin_unlock_irq(&uap->port.lock);
1177
1178 if (uap->using_tx_dma) {

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1411 uap->old_status = status;
1412
1413 if (!delta)
1414 return;
1415
1416 if (delta & UART01x_FR_DCD)
1417 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1418
1191 cpu_relax();
1192
1193 spin_lock_irq(&uap->port.lock);
1194 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1195 pl011_write(uap->dmacr, uap, REG_DMACR);
1196 spin_unlock_irq(&uap->port.lock);
1197
1198 if (uap->using_tx_dma) {

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1431 uap->old_status = status;
1432
1433 if (!delta)
1434 return;
1435
1436 if (delta & UART01x_FR_DCD)
1437 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1438
1419 if (delta & UART01x_FR_DSR)
1439 if (delta & uap->vendor->fr_dsr)
1420 uap->port.icount.dsr++;
1421
1440 uap->port.icount.dsr++;
1441
1422 if (delta & UART01x_FR_CTS)
1423 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1442 if (delta & uap->vendor->fr_cts)
1443 uart_handle_cts_change(&uap->port,
1444 status & uap->vendor->fr_cts);
1424
1425 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1426}
1427
1428static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1429{
1430 unsigned int dummy_read;
1431

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1488 return IRQ_RETVAL(handled);
1489}
1490
1491static unsigned int pl011_tx_empty(struct uart_port *port)
1492{
1493 struct uart_amba_port *uap =
1494 container_of(port, struct uart_amba_port, port);
1495 unsigned int status = pl011_read(uap, REG_FR);
1445
1446 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1447}
1448
1449static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1450{
1451 unsigned int dummy_read;
1452

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1509 return IRQ_RETVAL(handled);
1510}
1511
1512static unsigned int pl011_tx_empty(struct uart_port *port)
1513{
1514 struct uart_amba_port *uap =
1515 container_of(port, struct uart_amba_port, port);
1516 unsigned int status = pl011_read(uap, REG_FR);
1496 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1517 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1518 0 : TIOCSER_TEMT;
1497}
1498
1499static unsigned int pl011_get_mctrl(struct uart_port *port)
1500{
1501 struct uart_amba_port *uap =
1502 container_of(port, struct uart_amba_port, port);
1503 unsigned int result = 0;
1504 unsigned int status = pl011_read(uap, REG_FR);
1505
1506#define TIOCMBIT(uartbit, tiocmbit) \
1507 if (status & uartbit) \
1508 result |= tiocmbit
1509
1510 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1519}
1520
1521static unsigned int pl011_get_mctrl(struct uart_port *port)
1522{
1523 struct uart_amba_port *uap =
1524 container_of(port, struct uart_amba_port, port);
1525 unsigned int result = 0;
1526 unsigned int status = pl011_read(uap, REG_FR);
1527
1528#define TIOCMBIT(uartbit, tiocmbit) \
1529 if (status & uartbit) \
1530 result |= tiocmbit
1531
1532 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1511 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1512 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1513 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1533 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1534 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1535 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1514#undef TIOCMBIT
1515 return result;
1516}
1517
1518static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1519{
1520 struct uart_amba_port *uap =
1521 container_of(port, struct uart_amba_port, port);

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2186 }
2187
2188 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2189
2190 /*
2191 * Finally, wait for transmitter to become empty
2192 * and restore the TCR
2193 */
1536#undef TIOCMBIT
1537 return result;
1538}
1539
1540static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1541{
1542 struct uart_amba_port *uap =
1543 container_of(port, struct uart_amba_port, port);

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2208 }
2209
2210 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2211
2212 /*
2213 * Finally, wait for transmitter to become empty
2214 * and restore the TCR
2215 */
2194 while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY)
2216 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
2195 cpu_relax();
2196 if (!uap->vendor->always_enabled)
2197 pl011_write(old_cr, uap, REG_CR);
2198
2199 if (locked)
2200 spin_unlock(&uap->port.lock);
2201 local_irq_restore(flags);
2202

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2298 .index = -1,
2299 .data = &amba_reg,
2300};
2301
2302#define AMBA_CONSOLE (&amba_console)
2303
2304static void pl011_putc(struct uart_port *port, int c)
2305{
2217 cpu_relax();
2218 if (!uap->vendor->always_enabled)
2219 pl011_write(old_cr, uap, REG_CR);
2220
2221 if (locked)
2222 spin_unlock(&uap->port.lock);
2223 local_irq_restore(flags);
2224

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2320 .index = -1,
2321 .data = &amba_reg,
2322};
2323
2324#define AMBA_CONSOLE (&amba_console)
2325
2326static void pl011_putc(struct uart_port *port, int c)
2327{
2328 struct uart_amba_port *uap =
2329 container_of(port, struct uart_amba_port, port);
2330
2306 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2307 cpu_relax();
2308 if (port->iotype == UPIO_MEM32)
2309 writel(c, port->membase + UART01x_DR);
2310 else
2311 writeb(c, port->membase + UART01x_DR);
2331 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2332 cpu_relax();
2333 if (port->iotype == UPIO_MEM32)
2334 writel(c, port->membase + UART01x_DR);
2335 else
2336 writeb(c, port->membase + UART01x_DR);
2312 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2337 while (readl(port->membase + UART01x_FR) & uap->vendor->fr_busy)
2313 cpu_relax();
2314}
2315
2316static void pl011_early_write(struct console *con, const char *s, unsigned n)
2317{
2318 struct earlycon_device *dev = con->data;
2319
2320 uart_console_write(&dev->port, s, n, pl011_putc);

--- 344 unchanged lines hidden --- 		2338 cpu_relax();
2339}
2340
2341static void pl011_early_write(struct console *con, const char *s, unsigned n)
2342{
2343 struct earlycon_device *dev = con->data;
2344
2345 uart_console_write(&dev->port, s, n, pl011_putc);

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