amba-pl011.c (62f676ff7898f6c1bd26ce014564773a3dc00601) amba-pl011.c (2dd8a74fddd21b95dcc60a2d3c9eaec993419d69)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.

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1577}
1578
1579static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1580{
1581 struct uart_amba_port *uap =
1582 container_of(port, struct uart_amba_port, port);
1583 unsigned int cr;
1584
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.

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1577}
1578
1579static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1580{
1581 struct uart_amba_port *uap =
1582 container_of(port, struct uart_amba_port, port);
1583 unsigned int cr;
1584
1585 if (port->rs485.flags & SER_RS485_ENABLED) {
1586 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1587 mctrl &= ~TIOCM_RTS;
1588 else
1589 mctrl |= TIOCM_RTS;
1590 }
1591
1592 cr = pl011_read(uap, REG_CR);
1593
1594#define TIOCMBIT(tiocmbit, uartbit) \
1595 if (mctrl & tiocmbit) \
1596 cr |= uartbit; \
1597 else \
1598 cr &= ~uartbit
1599

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1807 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1808
1809 spin_lock_irq(&uap->port.lock);
1810
1811 cr = pl011_read(uap, REG_CR);
1812 cr &= UART011_CR_RTS | UART011_CR_DTR;
1813 cr |= UART01x_CR_UARTEN | UART011_CR_RXE;
1814
1585 cr = pl011_read(uap, REG_CR);
1586
1587#define TIOCMBIT(tiocmbit, uartbit) \
1588 if (mctrl & tiocmbit) \
1589 cr |= uartbit; \
1590 else \
1591 cr &= ~uartbit
1592

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1800 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1801
1802 spin_lock_irq(&uap->port.lock);
1803
1804 cr = pl011_read(uap, REG_CR);
1805 cr &= UART011_CR_RTS | UART011_CR_DTR;
1806 cr |= UART01x_CR_UARTEN | UART011_CR_RXE;
1807
1815 if (port->rs485.flags & SER_RS485_ENABLED) {
1816 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1817 cr &= ~UART011_CR_RTS;
1818 else
1819 cr |= UART011_CR_RTS;
1820 } else {
1808 if (!(port->rs485.flags & SER_RS485_ENABLED))
1821 cr |= UART011_CR_TXE;
1809 cr |= UART011_CR_TXE;
1822 }
1823
1824 pl011_write(cr, uap, REG_CR);
1825
1826 spin_unlock_irq(&uap->port.lock);
1827
1828 /*
1829 * initialise the old status of the modem signals
1830 */

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1811 pl011_write(cr, uap, REG_CR);
1812
1813 spin_unlock_irq(&uap->port.lock);
1814
1815 /*
1816 * initialise the old status of the modem signals
1817 */

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